Abstract: Memory cells which include a semiconductor substrate having a source region and a drain region separated by a channel region; a charge-trapping structure disposed above the channel region of the semiconductor substrate; a first gate disposed above the charge-trapping structure and proximate to the source region; and a second gate disposed above the charge-trapping structure and proximate to the drain region; where the first gate and the second gate are separated by a first nanospace are provided, along with arrays including a plurality of such cells, methods of manufacturing such cells and methods of operating such cells.

Abstract: In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier.

Abstract: The present invention relates to a method for programming a memory cell having a determined transconductance curve. The programming of the memory cell comprises a series of programming cycles each comprising a step of verifying the state of the memory cell. According to the present invention, the verify step comprises a first read of the memory cell with a first read voltage greater than a reference threshold voltage, and a second read of the memory cell with a second read voltage lower than or equal to the reference threshold voltage. The memory cell is considered not to be in the programmed state if first- and second-read currents flowing through the memory cell are above determined thresholds, and programming voltage pulses are applied to the memory cell while the latter is not in the programmed state. Application in particular to the programming of Flash memory cells.

Abstract: In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.

Abstract: A method and system for transferring information within a computer system is provided. The system includes a memory device that has a lower power mode in which data transfer circuitry is not driven by a clock signal, and a higher power mode in which data transfer circuitry is driven by a clock signal. The system further includes a memory controller that sends control signals to the memory device to initiate a data transfer transaction. The memory device receives the control signals asynchronously, and assumes the second mode in response to one of the control signals. While the memory device is in the second mode, the memory controller sends a control signal to identify a particular clock cycle. The memory device synchronously transfers the data. The memory device determines when to begin the data transfer based on the identified clock cycle and the type of data transfer that has been specified.

Abstract: A memory circuit includes a number of bit line structures, each including at least three bit lines; a number of word lines that intersect with the bit line structures at a number of sites; and a number of switching devices located at the sites. A number of column sense logic units are also provided, corresponding to the bit line structures. Each of the column sense logic units includes a first logic gate and a second logic gate. The first logic gate has a first input connected with a first one of the bit lines and a second input connected with a second one of the bit lines. The second logic gate has a first input interconnected with a third one of the bit lines, and a second input interconnected with the second one of the bit lines.

Abstract: A memory module having an array of memory devices, mounted thereon, that operate synchronously with a clock signal, wherein provisions are made to be able to fine-tune the clock phase in accordance with its use conditions. The memory module, having an array of memory devices mounted thereon that operate synchronously with the clock signal, includes; a phase-locked loop circuit which produces an output clock signal adjusted so that the phase of a feedback signal obtained by passing the output clock signal through a feedback loop matches the phase of an input clock signal; and a switching unit which selectively changes a load in the feedback loop in accordance with an external signal.

Abstract: A boost voltage generating circuit and method thereof. The example boost voltage generating circuit may include a voltage comparator comparing an input voltage and a reference voltage and generating a control signal based on a result of the voltage comparison, the input voltage based on a feedback boost voltage, a voltage generator generating a boost voltage in response to the control signal and a boost voltage controller including a first resistor with a first end connected to the boost voltage and a second end connected to the voltage comparator, the boost voltage controller controlling a level of current flowing through the first resistor based on one of a number of memory cells to be programmed and a number of cell groups including at least one memory cell to be programmed.

Abstract: Disclosed herein are an internal voltage generation control circuit and an internal voltage generation circuit using the same.

Abstract: A voltage pumping device is disclosed. The device comprises a reference voltage generator for generating a reference voltage having different levels depending on whether a semiconductor device is in a self-refresh mode or not, a voltage level detector for outputting a voltage pumping enabling signal in response to the reference voltage and a specific voltage fed back thereto, a voltage pump for performing a voltage pumping operation in response to the voltage pumping enabling signal to output the specific voltage, a discharge controller for outputting a discharge control signal in response to the reference voltage and the specific voltage, and a discharge circuit for discharging an output terminal of the voltage pump to a desired voltage level in response to the discharge control signal.

Abstract: An input circuit of a semiconductor memory device includes a data strobe circuit configured to buffer a data strobe signal to generate a first internal strobe signal and to generate a second internal strobe signal in response to the first internal strobe signal and an operating mode of the semiconductor memory device, and a data input circuit configured to perform data processing on input data in response to the first internal strobe signal, the second internal strobe signal and the operating mode to generate internal write data.

Abstract: A novel method for introducing delays in self timed memories is disclosed. In the proposed method, delays are introduced by introducing a capacitance on the path of signal to be delayed. The capacitances are realized by using idle lying metal layers in the circuit. The signal to be delayed is connected to these idle lying capacitances via programmable switches. The amount of delay introduced depends on the capacitance introduced in the path of signal which in turn depends on state of the switches. The state of the switches is controlled by delay codes provided externally to the delay introducing circuitry. Since, in the proposed method, idle-lying metal capacitances are utilized. the circuit can be implemented using minimum amount of additional hardware. Also delay provided by the proposed circuitry is a function of memory cell spice characteristics and core parasitic capacitances.

Abstract: A memory device compensates for delay time variations among multi-bit data. The device includes a first stage and a second stage of data storage units. The first stage of data storage units store first to nth data bits in response to a latch clock signal. The second stage of data storage units store the first to nth data contents output from the first stage of data storage units in response to a reference clock signal. The latch clock signal is obtained by delaying the reference clock signal. The latch clock signal includes first to nth sub latch signals. The sub latch signals are generated at different times according to propagation delay time periods of the corresponding first to nth data contents.

Abstract: An embedded memory and methods thereof are provided. The example embedded memory may include a first memory block configured to output data, selected by a first column select signal, on a first scan output line if the first memory block is determined to be non-defective and a second memory block configured to output data, selected by a second column select signal on a second scan output line if the first memory block is determined to be non-defective, the second memory block further configured to output data, selected by the first column select signal, on the first scan output line if the first memory block is determined to be defective.

Abstract: Provided is a sense amplifier circuit in a semiconductor memory device in which an under-drive is applied to a switching element of a pull-down side of a sense amplifier in order to compensate for poor driving capability in the case of performing a low voltage operation. The sense amplifier circuit includes: a sense amplifier which has a pull-down element composed of an NMOS transistor and a pull-up element composed of a PMOS transistor and is formed between bit lines to perform data exchange; and a drive controller which supplies a drive voltage for the use of pull-up and pull-down operations to the sense amplifier in order to perform the data exchange, and, during a specific time period included in a time for providing the drive voltage, performs an under-drive whereby the drive voltage for the use of the pull-down operation is used so that the sense amplifier is provided with a voltage that is lower than a voltage used in the pull-down operation in a normal state.

Abstract: A semiconductor memory apparatus includes a sense amplifier that receives a driving voltage through a sense amplifier power supply input terminal and detects and amplifies a difference between signals that are supplied to two input lines, a sense amplifier voltage supply unit that supplies a driving voltage and an overdriving voltage higher than the driving voltage to the sense amplifier through the sense amplifier power supply input terminal using a power supply voltage, and a driving voltage control unit that maintains a driving voltage level of the sense amplifier power supply input terminal in response to the level of the power supply voltage, after a voltage of the sense amplifier power supply input terminal is elevated to a power supply level responding to the overdriving voltage in order to perform the overdriving operation.

Abstract: According to the present invention, a memory circuit requiring refresh operations a first circuit which receives a command in synchronization with a clock signal, and which generates a first internal command internally and a second circuit which generates a second internal command, e.g., a refresh command, internally in a prescribed refresh cycle. And an internal circuit, according to said first internal command, executes corresponding control through clock-synchronous operations, and when said refresh command is issued, sequentially executes control corresponding to the refresh command and control corresponding to said first internal command through clock-asynchronous operations. According to the present invention, when a refresh timing signal is generated, the refresh operation can be intrupted among the external command operations.

Abstract: An apparatus and method of disconnecting or disabling an input/output terminal of an integrated circuit after packaging. Each input/output terminal of the integrated circuit includes a disabling device coupled thereto between the input/output terminal and the output driver of the respective input/output terminal. A DRAM module is disclosed having a plurality of partially good DRAM devices wherein the known bad input/output terminals are permanently disconnected using a disabling device, both the known good and known bad input/output terminals being coupled to conductive traces of a carrier substrate.

Abstract: A control circuit for a power supply device, a power supply device, and a control method thereof are provided where the output voltages to be supplied to various devices are determined and set up to optimum levels rapidly and efficiently. A control circuit 10A in a power supply device supplies a device 60, which supplies an initial voltage and then demands to receive a required level of voltage which is different from an initial voltage supplied beforehand, with the required level of voltage ranging from V1 to V3. The control circuit 10A comprises a communication unit 21 for receiving a demand level such as V1 and a storage unit 22, including REG1 to REG3, for storing an initial setting level beforehand for determining the initial voltage and the demand level received by the communication unit 21. The initial voltage or the required voltage ranging from V1 to V3 can controlled in response to the initial setting level or the demand level.

Abstract: A memory architecture and circuits for minimizing current leakage in the memory array. Subdivisions of the memory array each have local power grids that can be selectively connected to power supplies, such that only an accessed subdivision will receive power to execute the memory access operation. The memory array can further include databuses which are precharged to one voltage during idle times and a second voltage during active read cycles, which reduces leakage current in datapath circuitry connected to the databuses within the memory array blocks.

Abstract: A memory arrangement includes an interface configured to transmit data in the form of data packets according to a predefined protocol. The memory arrangement includes at least two memory banks. Each memory bank includes at least one memory cell. The memory arrangement includes at least two memory bank access devices configured to facilitate accessing the data of the at least one memory cell of each of the at least two memory banks. The memory arrangement includes at least two data packet processing devices configured to encode and/or decode the data packets. The at least two data packet processing devices are assigned to different memory bank access devices.

Abstract: A multi-port memory device providing various frequencies for ports is disclosed. The multi-port memory device includes a memory core, a clock generator and a plurality of ports. The clock generator generates an internal clock signal based on an external clock signal. Each of the ports has a local clock generator that generates a local clock signal having a predetermined frequency based on the internal clock signal and accesses the memory core in response to the local clock signal. The multi-port memory device may generate various frequencies for ports without increasing the number of pins for receiving clock signals.

Abstract: An integrated circuit device includes a first latch having a first input to receive a first predecode value, a second input to receive a first clock signal, and an output to provide a latched first predecode value responsive to an edge event of the first clock signal. The integrated circuit device further includes a memory component. The memory component includes an input to receive the latched first predecode value and the latched second predecode value, a first bit line, and a plurality of word lines coupled to the first bit line. Each word line is associated with a corresponding bit of the latched second predecode value. The integrated circuit device further includes logic having an input to receive the corresponding bit of the latched first predecode value. The logic is to precharge the first bit line directly responsive to only a value at the corresponding bit of the latched first predecode value.

Abstract: A semiconductor memory device includes a memory cell array, word lines, and a row decoder. The memory cell array includes memory cells arranged in a matrix. The memory cell includes a first MOS transistor having a charge accumulation layer and a control gate and a second MOS transistor. The word line connects the control gates of the first MOS transistors. The row decoder includes a first address decode circuit, a second address decode circuit, and a transfer gate. The first address decode circuit decodes m bits in a n-bit row address signal (m and n are a natural number satisfying the expression m<n). The second address decode circuit decodes (n?m) bits in the row address signal. The transfer gate supplies the output of the first address decode circuit to the word line according to the output of the second address decoded circuit.

Abstract: A signal sampling apparatus for a DRAM memory comprises a phase delay circuit adapted for receiving a data signal and delaying the data signal by a predetermined time to generate a delay signal; and a sampling circuit for sampling the data signal according to the delay signal.

Abstract: A system for improved dispensing of partially frozen beverages from a container. The system comprises a mechanical vibrator adapted to contact the outer wall of a container such as a blending pitcher. The interaction of the partially frozen beverage with the vibrating outer wall reduces the effective viscosity of the mixture as an aid to pouring.

Abstract: A vibratory head for a concrete vibrator includes an eccentric which rotates to convert rotational motion to vibratory motion.

Abstract: A method and apparatus for making non-staining coffee or tea includes an ion exchanger for removing heavy metals from the brewed coffee or tea or from the water used to brew the coffee or tea.

Abstract: Device and installation for injecting matter, particulate matter in particular, into an enclosure, and associated method. The device for injecting matter into a reaction enclosure in a treatment method using pressurized water comprises a pressurizing capacity (24) having an inner volume in which a mobile assembly (29) is arranged, e.g. a bellows which compartments it sealingly into two variable volumes, namely a pressurizing capacity (32) and a hydraulic pressurizing capacity (34). The variable, hydraulic pressurizing capacity of this device is connected to the outlet (15) of the aqueous phase of a liquid/gas separator (14) which separates the liquid and gaseous phases of an effluent leaving the reaction enclosure (2).

Abstract: An apparatus for manufacturing well treatment fluid is disclosed that includes a proppant storage and metering unit; a chemical storage and metering unit connected to a blending unit; and an electronic control system connected to the proppant storage and metering unit, the chemical storage and metering unit, and the blending unit; wherein the proppant storage and metering unit, chemical storage and metering unit, and blending unit are contained in a single land-based enclosure. A method for manufacturing well treatment fluid is disclosed that includes delivering to a blending unit a desired rate of proppant by weighing a proppant storage and metering unit storing the proppant; and adjusting the size of a calibrated aperture on the proppant storage and metering unit. A method for manufacturing multiple well treatment fluids at a single location is disclosed. Methods of monitoring the usage of well treatment components during the manufacture of well treatment components are disclosed.

Abstract: A blender base that may be used with a food processor container, a blender container, and a single use beverage container. The blender container includes a novel blade unit having a food processor-style blade and blender type blades. Programs with preprogrammed motor commands for desired operations are stored in memory and may be selected by a user on a user interface. The user interface may include a liquid crystal display, or function switches and light emitting diodes. Upon selection of a particular pre-defined function, the microcontroller retrieves the appropriate program from the read only memory and specifies the preprogrammed motor commands to accomplish the selected function.

Abstract: An anti-biofouling seismic streamer casing (100,100?) is provided that is formed by a flexible tubing (110) coated with a layer of a two-part heat cured silicone elastomer (120). The seismic streamer casing (100, 100?) is formed by a method that includes steps of providing a flexible tubing (200) and pre-treating the outer surface of the tubing (210). Two parts of a two-part silicone elastomer are then mixed together (220). The method also includes coating the mixed two-part silicone elastomer on the flexible tubing (230), and heating the flexible tubing to cure the coating (240).

Abstract: A decision feedback equalizer (DFE) structure which uses a reference signal based adaptive equalizer as forward filter and a blind adaptive equalizer as feedback filter is used for surface processing of mud pulse telemetry data.

Abstract: Pulse-echo ranging system are used in level measurement applications for determining the distance to a target object by measuring how long after transmission of a pulse an echo pulse is received. An echo profile is generated and then processed to determine the temporal position of the echo pulse on a temporal axis. Based on the fact that the peak portion and the trailing edge of the echo profile are susceptible to be affected by the measurement environment and the target object itself, the accuracy in determining the echo arrival time is increased, by the steps of fitting a branch of a parabola to a selected portion of the leading edge of the echo profile and determining the temporal position of the fitted parabola on the temporal axis.

Abstract: A timer cap is movable relative to a container holding a product to be applied to the skin, hair or other body part. Programs in a control microprocessor in the timer cap are actuated by opening and closing the container by the timer cap to initiate different programs relating to the time periods associated with application and usage of the product.

Abstract: In one embodiment, a computer readable medium is provided that includes a date time zone dimension table comprising a date key and a time zone key, the date key identifying a selected point in time relative to a selected temporal origin and the time zone key identifying one of a plurality of possible time zones, and at least one attribute, the at least one attribute describing time information for a selected date and time zone key pair.

Abstract: To provide a timepiece attached with a calendar mechanism capable of carrying out large date indication, having a degree of freedom of a date indicating position and capable of developing a design variation. A timepiece attached with a calendar mechanism of the invention includes a first date indicator for indicating a position of 1 of a date and a second date indicator for indicating a position of 10 of the date. The first indicator includes a first date indicator wheel portion for rotating the first date indicator by rotation of a top train wheel and a drive cam for rotating the second date indicator and determining a position of the second date indicator. It is preferable that the drive cam includes a cam circular arc portion constituted to be provided with a shape including four concentric circles respectively having different radii.

Abstract: The radio-controlled wristwatch comprises a memory unit (30) in which a table of more than four time signal transmitters (1 . . . 10) from more than two time zones (A . . . N) is stored. Attempts for receiving from the transmitters (1 . . . 10) filed in the table are made by a control device (28), and upon a successful reception of a time signal transmitter (1 . . . 10) from the table, the appurtenant time is displayed upon the display (32) of the wristwatch (20).

Abstract: An ergonomic watch case, time display and setting crown are provided, with the case shaped generally in the form of an obtuse triangle and attached to a watch strap. A horizontal bisector through the case and time display is offset by a predetermined angle out of perpendicularity with a vertical bisector through the watch strap to improve alignment with a viewer's line of sight when reading the time. An apical setting crown is located at the apex of one of the two acute angles of the case to improve rotation of a crown knob in either direction with minimal resistance or obstruction from the watch case. A chime melody and icon are provided to sound a pleasing wake up call or other time set to be heard.

Abstract: To provide a timepiece in which, when a rocking has been performed, a setting wheel does not run onto a gear wheel of a hand setting train wheel. A setting wheel meshes with a clutch whee at a time correction time, and a mesh with the clutch wheel is released at a time hand motion time while being placed upward than the time correction time. At the time correction time, in a minute wheel, a power mesh part receiving a power from the setting wheel meshes with the setting wheel. Further, at the time hand motion time, in the minute wheel, a mesh release prevention part having been provided in an upper part of the power mesh part prevents the mesh with the setting wheel from being released.

Abstract: A positive & negative directions independent driving and displaying wristwatch structure, which sets two groups of numbered face in reverse direction on face of wristwatch, each numbered face has hour, minute and second hand, wherein the independent active shaft respectively drives each group of hands, so that they can rotate in reverse direction, namely, as one hands group rotates clockwise while another hands group rotates anticlockwise, thereby, it is very interesting to watch time, moreover, owing to the clockwise and anticlockwise rotating numbered faces, you can get directly the correct left time by visual confirmation, which therefore promotes the operating function of wristwatch accordingly.

Abstract: Regulating element for wristwatch comprising: a balance, a magnetic return member for returning the balance to at least one stable equilibrium position, and an escapement for maintaining the oscillation of the balance around the equilibrium position.

Abstract: A disk access device records to and plays back from a disk on which data recording is performed according to the ZCLV format, and includes a head that reads/writes data from/to the disk. The disk access device calculates a deferment time period that begins upon completion of data reading/writing in the user area of a currently accessed zone and ends when the head enters a predetermined area of the guard track zone following the user area, and a setting time period for performing settings for data reading/writing in the zone to be accessed next. If the deferment time period is shorter than the setting time period, the disk access device moves the head back, when data reading or writing in the currently accessed zone ends, to a position such that the setting time period ends before the head advancing from the position arrives at the predetermined area.

Abstract: A CD changer includes a plurality of holders 19, a disk playback part, and a stopper part 100. A holder 19 holds a CD. The stopper part 100 includes a first stopper 103, a second stopper 104, a swing stopper 105, an up-down stopper 106, and an auxiliary stopper 107. When the disk playback part plays back the selected CD, the first stopper 103 supports the other CDs at the arrow K1 side, and the second stopper 104 and the auxiliary stopper 107 support the other CDs at the arrow K2 side. The swing stopper 105 supports the selected CD. When the selected CD is clamped, the swing stopper 105 is saved from the selected CD.

Abstract: A recording medium playback device, by which the number of parts can be prevented from increasing and a size of the device can be prevented from being enlarged, is provided. A CD changer includes a disk receiving part, disk carrying part, positioning part, motor, and transmission restricting part 74. The disk receiving part has a plurality of holders each for holding a CD. A plurality of the holders are arranged being piled on one another and movable along the arranging direction. The disk carrying part carries the CD. The positioning part moves the disk receiving part along the arranging direction. The motor supplies drive force to both the disk carrying part and the positioning part. The transmission restricting part 74 restricts the drive force of the motor to be transmitted to the positioning part when the disk carrying part carries the CD.

Abstract: Different formats, whose defect management methods differ based on the presence or absence of a cartridge, are adopted for information storage media having the same physical characteristics. An information processing apparatus is capable of mounting a storage medium having a data recording area. The data recording area includes a user area to which logical addresses are allocated in accordance with recording units.

Abstract: Even when binder repeats expansion and contraction by the time progress after a reliability test or mounting, and change of circumference environment, in the offered optical head, a gap of optical axis and exfoliation of binder are not generated. The optical head indicated has the housing in which the optical detector holder-board 1 holding the optical detector 3 which detects the catoptric light beam reflected in respect of information record of an optical disc is attached. With this optical head, the optical detector holder-board 1 has through-holes 1a and 1b having the flat portions 11 and 12 inside, and the supports 2a and 2b having the flat portions 15 and 16 outside are formed on housing. The optical detector holder-board 1 is inserted in supports 2a and 2b by the through-holes 1a and 1b, and the binder 4 and 5 is filled up into the space 31 or the space 32, and is fixed.

Abstract: An optical pickup actuator which includes a base, a blade having an objective lens mounted thereon, a plurality of suspensions supporting the blade to be movable with respect to the base and forming an electroconductive path, and a magnetic circuit driving the blade according to a driving signal applied through the respective suspensions. The magnetic circuit includes a magnet fixed to the base, and a fine pattern coil installed on the blade at a position facing the magnet and having a track pattern coil, a focus pattern coil, and a tilt pattern coil independently driven by current applied through the suspensions and providing driving forces in a track direction, a focus direction, and a tilt direction of the blade.

Abstract: A light source outputs an optical beam. A condensing unit condenses the optical beam to a first information-recording layer. An optical detecting unit detects a reflected optical beam reflected from the optical storage medium. A limiting element inputs a first reflected optical beam reflected from the first information-recording layer to the optical detecting unit, and limits or shields an input of a second reflected optical beam reflected from a second information-recording layer to the optical detecting unit.

Abstract: A method for radial tracking in an optical disc drive (1) is described. A DTD tracking error signal (S3) is derived from the wobble-induced signal components (WA, WB,WC, WD) of the optical detector signal (SR). This tracking error signal is relatively insensitive to beamlanding errors, and to differences in the signal amplitudes K of the output signal of individual detector segments. Further, the need for a 3-spot grating is eliminated. A distinction is made between on the one hand a situation where the track being followed is empty and on the other hand a situation where the track being followed is written. In case the track being followed is empty, a DTD tracking error signal is derived from the wobble-induced signal components of the optical detector signal, whereas, in case the track being followed is written, a DTD tracking error signal is derived from the datainduced signal components of the optical detector signal.