Abstract: A laser beam processing method for a semiconductor wafer having a low-dielectric insulating film formed on the front surface of a semiconductor substrate thereof, a plurality of circuits sectioned by streets into a lattice pattern, and metal patterns for testing formed partially on each street. The method includes a laser beam processing step for applying a laser beam to the positions of areas at which the metal patterns are located, and to the low-dielectric insulating film, under different processing conditions so as to remove the metal patterns and the low-dielectric insulating film without damaging the substrate and its circuits.

Abstract: A method of cutting an integrated circuit chip from a wafer having a plurality of integrated circuit chips is provided. An upper portion of the wafer is ablated using two laser beams to form two substantially parallel trenches that extend into the wafer from a top surface of the wafer through intermetal dielectric layers and at least partially into a substrate of the wafer. After the ablating to form the two trenches, cutting through the wafer between outer sidewalls of the two laser-ablated trenches with a saw blade is performed. A width between the outer sidewalls of the two laser-ablated trenches is greater than a cutting width of the saw blade. This may be particularly useful in lead-free packaging applications and/or applications where the intermetal dielectric layers use low-k dielectric materials, for example.

Abstract: To improve the reliability and yield of a thin-type semiconductor device as used for a stack-type flash memory, the semiconductor device is manufactured by upheaving each of semiconductor chips (semiconductor devices) obtained by dicing a semiconductor wafer on an adhesive sheet from a backside via the adhesive sheet using an upthrow jig to which ultrasonic vibration is applied so as not to break through the adhesive sheet, and by picking up each semiconductor chip.

Abstract: Numerous embodiments of a method for depositing a layer of nano-crystal silicon on a substrate. In one embodiment of the present invention, a substrate is placed in a single wafer chamber and heated to a temperature between about 300° C. to about 490° C. A silicon source is also fed into the single wafer chamber.

Abstract: Homogeneous and dense arrays of nanowires are described. The nanowires can be formed in solution and can have average diameters of 40-300 nm and lengths of 1-3 ?m. They can be formed on any suitable substrate. Photovoltaic devices are also described.

Abstract: A copper filled damascene structure and method for forming the same the method including providing a substrate comprising a semiconductor substrate; forming an insulator layer on the substrate; forming a damascene opening through a thickness portion of the insulator layer; forming a diffusion barrier layer to line the damascene opening; forming a first seed layer overlying the diffusion barrier; plasma treating the first seed layer in-situ with a first treatment plasma comprising plasma source gases selected from the group consisting of argon, nitrogen, hydrogen, and NH3; forming a second seed layer overlying the first seed layer; forming a copper layer overlying the second seed layer according to an electro-chemical plating (ECP) process to fill the damascene opening; and, planarizing the copper layer to form a metal interconnect structure.

Abstract: The present invention relates to a method for fabricating a semiconductor device with improved refresh time. The method includes the steps of: forming a plurality of gate lines on a substrate; forming a plurality of cell junctions by ion-implanting a first dopant with use of the gate lines as a mask; forming a buffer layer along a gate line profile; and forming a plurality of plug ion-implantation regions in the cell junctions by ion-implanting a second dopant into the substrate under the presence of the buffer layer to thereby from the plugs thereon.

Abstract: A cleaning solution selectively removes a titanium nitride layer and a non-reacting metal layer. The cleaning solution includes an acid solution and an oxidation agent with iodine. The cleaning solution also effectively removes a photoresist layer and organic materials. Moreover, the cleaning solution can be employed in tungsten gate electrode technologies that have been spotlighted because of the capability to improve device operation characteristics.

Abstract: A transistor and a method of fabricating the transistor are provided. The transistor includes a semiconductor material comprising drain regions and source regions formed in alternating rows or columns. The transistor also includes polysilicon chains overlaying the top of the semiconductor material, disconnected from and substantially parallel to one another, and separating the drain regions from the source regions. The method includes providing a semiconductor material, growing a first insulating layer on top of the semiconductor material, depositing a polysilicon layer on top of the first insulating layer, defining a plurality of chains in the polysilicon layer, the plurality of chains being disconnected from and substantially parallel to one another, and forming a plurality of drain regions and a plurality of source regions in the semiconductor material in alternating rows or columns. The plurality of chains separates the plurality of drain regions from the plurality of source regions.

Abstract: The present invention relates to a method for fabricating a semiconductor device with gate spacers. The method includes the steps of: forming a plurality of gate structures on a substrate; forming an insulation layer on the gate structures and the substrate; and etching the insulation layer to form gate spacers on sidewalls of the gate structures, wherein the gate spacers have top corners sloped by employing two different etch recipes providing different ranges of a pressure and a gas flow.

Abstract: Disclosed are methods for making microwave circuits using thickfilm components. In an embodiment, the method includes depositing a dielectric over a ground plane, and then forming a conductor on the dielectric. The conductor is formed by depositing a conductive thickfilm on the dielectric and then “subsintering” the conductive thickfilm. In one embodiment, before the subsintering, the conductive thickfilm is patterned to define at least one conductor. In another embodiment, after the subsintering, the conductive thickfilm is patterned to define at least one conductor. After subsintering, the conductive thickfilm is etched to expose the conductor(s), and the conductor(s) are then fired at a full sintering temperature.

Abstract: A process for forming bumps on electrode pads for a wiring board including a substrate and a plurality of electrode pads. The process (a) forms a laminated two-layer film on the wiring board and forms a pattern of apertures at positions corresponding to the electrode pads, the laminated two-layer film including a lower layer containing an alkali-soluble radiation-nonsensitive resin composition and an upper layer containing a negative radiation-sensitive resin composition; (b) fills a low-melting metal in the aperture pattern; (c) reflows the low-melting metal by pressing or heating to form bumps; and (d) peels and removes the laminated two-layer film from the board. The laminated film including two layers with different properties permits high resolution and easy peeling.

Abstract: A new method to form an integrated circuit device is achieved. The method comprises providing a substrate. A sacrificial layer is formed overlying the substrate. The sacrificial layer is patterned to form temporary vertical spacers where conductive bonding locations are planned. A conductive layer is deposited overlying the temporary vertical spacers and the substrate. The conductive layer is patterned to form conductive bonding locations overlying the temporary vertical spacers. The temporary vertical spacers are etched away to create voids underlying the conductive bonding locations.

Abstract: A solder ball 50 according to the present invention includes a spherical core 2 and a solder layer 4, which includes Sn and Ag and which is provided so as to wrap the core 2 up. The amount of water contained in the solder layer 4 is 100 ?l/g or less when represented by the amount of water vapor in standard conditions.

Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Abstract: A method and apparatus for forming layers on a substrate comprising depositing a metal seed layer on a substrate surface having apertures, depositing a transition metal layer over the copper seed layer, and depositing a bulk metal layer over the transition metal layer. Also a method and apparatus for forming a via through a dielectric to reveal metal at the base of the via, depositing a transition metal layer, and depositing a first metal layer on the transition metal layer. Additionally, a method and apparatus for depositing a transition metal layer on an exposed metal surface, and depositing a layer thereover selected from the group consisting of a capping layer and a low dielectric constant layer.

Abstract: The invention is a chemically grown oxide layer which prevents dopant diffusion between semiconductor layers. The chemically grown oxide layer may be so thin that it does not form a barrier to electrical conduction, and thus may be formed within active devices such as diodes or bipolar transistors. Such a chemically grown oxide film is advantageously used to prevent dopant diffusion in a vertically oriented polysilicon diode formed in a monolithic three dimensional memory array.

Abstract: A protection layer is formed on a semiconductor substrate having a cell array region and an alignment key region. A plurality of data storage elements are formed on the protection layer in the cell array region. An insulating layer is formed on the data storage elements, a barrier layer is formed on the insulating layer, and a sacrificial layer is formed on the barrier layer. The sacrificial layer, the barrier layer and the insulating layer are patterned to form contact holes that expose the data storage elements, and conductive plugs are formed in the contact holes. The sacrificial layer is etched to leave portions of the conductive plugs protruding from the barrier layer. The protruding portions of the conductive plugs are removed by polishing.

Abstract: A semiconductor memory device and manufacturing method, including a bit line connector and a lower electrode connector that respectively connect a bit line and a capacitor lower electrode of the device to active areas of a semiconductor substrate. The connectors are formed using a line-type self-aligned photoresist mask pattern positioned on an interlevel dielectric layer formed on the substrate, which exposes only a portion of the dielectric layer corresponding to a source region and which extends in a direction which a gate electrode extends, to provide a misalignment margin. The bit line connector and the lower electrode connector are respectively formed by one-time mask processes. A contact hole for the bit line connector in a cell area, and a contact hole for a metal wiring plug in a peripheral area are simultaneously formed, alleviating etching burden during subsequent forming of a metal wiring pad.

Abstract: The present invention is generally directed to various methods of forming conductive through-wafer vias. In one illustrative embodiment, the method comprises providing a layer of semiconducting material, forming a layer of metal on a first side of the layer of semiconducting material, forming an opening in the layer of semiconducting material to thereby expose a portion of the layer of metal, the opening extending from at least a second side of the layer of semiconducting material to the layer of metal, and performing a deposition process to form a conductive contact in the opening using the exposed portion of the metal layer as a seed layer.

Abstract: The present disclosure provides a method for removing photoresist residue from a low k dielectric above a semiconductor substrate. The method includes creating a first opening in the low k dielectric extending a first depth towards an underlying conductor, and applying and patterning a material above the low k dielectric. In-situ first and second plasma environments are provided, with a bias power being applied to the substrate to attract ion bombardment during the second plasma environment. Trenches can be etched in the low k dielectric, the trenches extending a second depth less than the first depth. Material for the first and second plasmas and the ion bombardment are selected for removing residue of the material from the low k dielectric.

Abstract: Disclosed herein is a chemical mechanical polishing (CMP) method for manufacturing a semiconductor device, comprising performing partial ion implantation of dopants at different concentrations into a plurality of at least two divided regions of a wafer having a planarization-target film, and subjecting the partially ion implanted-wafer to a chemical mechanical polishing process. In accordance with the present invention, non-uniformity of the removal rate in a chemical mechanical polishing process is countervailed by dopants which are implanted at different concentrations via partial ion implantation, and thereby it is possible to polish the target film at a uniform removal rate.

Abstract: The invention provides a method of chemically-mechanically polishing a substrate. A substrate comprising ruthenium and copper is contacted with a chemical-mechanical polishing system comprising a polishing component, hydrogen peroxide, an organic acid, at least one heterocyclic compound comprising at least one nitrogen atom, and water. The polishing component is moved relative to the substrate, and at least a portion of the substrate is abraded to polish the substrate. The pH of the polishing system is about 6 to about 12, the ruthenium and copper are in electrical contact, and the difference between the open circuit potential of copper and the open circuit potential of ruthenium in the polishing system is about 50 mV or less.

Abstract: A method for forming an opening in a semiconductor device is provided. In one embodiment, a bottom anti-reflective coating (BARC) layer is formed overlying an insulation layer of a substrate. A patterned photoresist layer including at least one opening therein is formed overlying the BARC layer.

Abstract: A method of etching a feature in a surface of a substrate. The substrate is provided. A photoresist layer is formed on the surface of the substrate. A thickness profile of the formed photoresist layer is determined. A grayscale scanning pattern is determined based on the feature and the thickness profile of the photoresist layer. The determined grayscale scanning pattern is laser written on the photoresist layer to expose a portion of the photoresist layer. The exposed portion of the photoresist layer is removed to form a grayscale pattern in the photoresist layer. The photoresist layer and the surface of the substrate are etched to form the feature in the surface of the substrate.

Abstract: A method of manufacturing a semiconductor device comprises, in patterning of a conductive film having a grain boundary on a very thin dielectric film, a first etching step of carrying out anisotropic etching until most of the conductive film in a flat portion disappears, and a second etching step of increasing a selective ratio to the dielectric film to etch the conductive film in an unnecessary portion such that a thickness of the dielectric film provided under the grain boundary can be held to prevent oxidation species from reaching an interface with a substrate after the first etching step.

Abstract: A FinFET includes a plurality of semiconductor fins. Over a semiconductor layer, patterned features (e.g. of minimum photolithographic size and spacing) are formed. In one example of fin formation, a first set of sidewall spacers are formed adjacent to the sides of these patterned features. A second set of sidewall spacers of a different material are formed adjacent to the sides of the first set of sidewall spacers. The first set of sidewall spacers are removed leaving the second set of sidewall spacers spaced from the patterned features. Both the second set of sidewall spacers and the patterned features are used as a mask to an etch that leaves semiconductor fins patterned as per the second set of sidewall spacers and the patterned features. These resulting semiconductor fins, which have sub-lithographic spacings, are then used for channels of a FinFET transistor.

Abstract: An improved method of etching very small contact holes through dielectric layers used to separate conducting layers in multilevel integrated circuits formed on semiconductor substrates has been developed. The method uses bi-level ARC coatings in the resist structure and a unique combination of gaseous components in a plasma etching process which is used to dry develop the bi-level resist mask as well as etch through a silicon oxide dielectric layer. The gaseous components comprise a mixture of a fluorine containing gas, such as C4F8, C5F8, C4F6, CHF3 or similar species, an inert gas, such as helium or argon, an optional weak oxidant, such as CO or O2 or similar species, and a nitrogen source, such as N2, N2O, or NH3 or similar species. The patterned masking layer can be used to reliably etch contact holes in silicon oxide layers on semiconductor substrates, where the holes have diameters of about 0.1 micron or less.

Abstract: Methods and apparatus for preparing a porous low-k dielectric material on a substrate are provided. The methods optionally involve the use of ultraviolet radiation to react with and remove porogen from a porogen containing precursor film leaving a porous dielectric matrix and further exposing the dielectric matrix to ultraviolet radiation to increase the mechanical strength of the dielectric matrix. Some methods involve activating a gas to create reactive gas species that can clean a reaction chamber. One disclosed apparatus includes an array of multiple ultraviolet sources that can be controlled such that different wavelengths of light can be used to irradiate a sample at a time.

Abstract: A process for depositing porous silicon oxide-based films using a sol-gel approach utilizing a precursor solution formulation which includes a purified nonionic surfactant and an additive among other components, where the additive is either an ionic additive or an amine additive which forms an ionic ammonium type salt in the acidic precursor solution. Using this precursor solution formulation enables formation of a film having a dielectric constant less than 2.5, appropriate mechanical properties, and minimal levels of alkali metal impurities. In one embodiment, this is achieved by purifying the surfactant and adding ionic or amine additives such as tetraalkylammonium salts and amines to the stock precursor solution.

Abstract: Embodiments of methods, apparatuses, devices, and/or systems for forming a component having dielectric sub-layers are described.

Abstract: In a method of manufacturing a semiconductor device, semiconductor circuit elements or wiring patterns are formed on a semiconductor substrate then, a porous semiconductor oxide film is formed as an interlayer insulating film on the semiconductor substrate including the semiconductor circuit elements or wiring patterns by oxidizing semiconductor substance in a mixture gas containing an oxygen gas in a chamber.

Abstract: A method for fabricating a dielectric layer doped with nitrogen is provided according to the present invention. According to the method, a dielectric layer is formed on a semiconductor substrate. Two steps of nitridation processes are then performed on the dielectric layer. Following that, one step or two steps of annealing processes are performed on the dielectric layer. Dielectric layer formed by the method has uniform nitrogen dopant, and thus has fine electric properties.

Abstract: A method and system are described for increasing the tensile stress in thin films formed on a substrate, such as silicon nitride films. The thin film may be a planar film, or a non-planar film, such as a nitride film formed over a NMOS gate. The thin film is exposed to collimated electro-magnetic (EM) radiation to anisotropically expose the film. The EM radiation can have a component having a wavelength less than about 500 nm. The EM source can include a multi-frequency source of radiation.

Abstract: A papermaking belt for dewatering and imprinting a paper web. The belt comprises two laminae joined together in a face to face relationship to form a unitary laminate. The first lamina comprises a foraminous imprinting member which may serve as a reinforcing structure for a patterned framework. The second lamina comprises a secondary base and a batting which is joined to the secondary base to form a dewatering felt. The two lamina are juxtaposed and attached such that batting from the second lamina extends through the foraminous imprinting member of the first lamina providing a hydraulic connection therebetween.

Abstract: Provided is a light-shielding sheet comprising a light-shielding material made of a white film having a light transmission of not more than 50% and a reinforcement made of a textile fabric or a nonwoven fabric. Preferred is a case where the white film is a film having therein voids formed through stretching of the film or a film having therein bubbles formed through foaming by use of a foaming agent, whereby a light-shielding sheet is provided which has a light weight, a high strength and a superior durability and which inhibits temperature increase caused by the heat resulting from sunlight absorption. The light-shielding sheet is employed suitably as a light-shielding material for agricultural use and horticultural use.

Abstract: The invention provides an opalescent forehearth color concentrate comprising a non-smelted agglomerated interspersion of particles for use in coloring glass, said concentrate comprising by weight from about 10% to about 70% of a glass component and from about 30% to about 90% of one or more opalescent pigments, the glass component comprising by weight from about 10% to about 50% ZnO and about 15 to about 60% SiO2. The invention also provides a method of using the color concentrate.

Abstract: Disclosed is a synthetic silica glass optical material having high resistance to optical damage by ultraviolet radiation in the ultraviolet wavelength range, particularly in the wavelength region of less than about 250 nm and particularly, exhibiting a low laser induced density change. The synthetic silica glass optical material of the present invention contains at least about 0.1 ppm of aluminum and H2 concentration levels greater than about 0.5×1017 molecules/cm2. Additionally, the synthetic silica optical material of the present invention exhibits an H2 to Al ratio of greater than about 1.2, as measured in ×1017/cm3 molecules H2 per ppm Al.

Abstract: A dielectric ceramic composition characterized as containing a dielectric material which contains a dielectric composition represented by the compositional formula a.Li2O-b.(CaO1?x—SrOx)-c.R2O3-d.TiO2 (wherein x satisfies 0?x<1; R is at least one selected from La, Y and other rare-earth metals; and a, b, c and d satisfy 0?a?20 mol %, 0?b?45 mol %, 0<c?20 mol % and 40?d?80 mol %) and at least one of oxides of Group 4 and Group 14 metallic elements of the Periodic Table.

Abstract: A dielectric ceramic composition includes a main component including a dielectric oxide expressed by a composition formula of {(Ca1-xSrx)O}m.(Zr1-yTiy)O2, wherein m, x and y indicating composition mole ratios in the composition formula are in relationships of 0.8?m?1.3, 0x?1.00 and 0.1?y?0.8; a first subcomponent including a V oxide; and a second subcomponent including an Al oxide; wherein ratios of respective components with respect to 100 moles of said main component are the first subcomponent: 0 mole<first subcomponent<7 moles (wherein the value is a V oxide value in terms of V2O5); and the second subcomponent: 0 mole<second subcomponent<15 moles (wherein the value is an Al oxide value in terms of Al2O3).

Abstract: An exhaust gas purifying catalyst formed by having a first rhodium-containing catalyst layer, a second zeolite-containing catalyst layer, and a third palladium-containing catalyst layer superposed sequentially on a carrier, and a process for purifying the exhaust gas from an internal combustion engine by using the catalyst. A catalyst possessing durability and excelling in the ability to adsorb hydrocarbon, the ability to purify, and the three-way performance is provided.

Abstract: Single step process for the preparation of lower ?-alkene polymerisation heterogeneous solid catalyst, wherein the procatalyst is obtained by reacting organomagnesium precursor and titanium tetrahalide or titanium haloalkoxo species of the formula Ti(OR)m Xn, with a hydrocarbon or halohydrocarbon solvent and internal electron donor and optionally an acid halide under microwave irradiation of 300 to 1200 W. The mole ratio of the organomagnesium precursor to the titanium tetrachloride or titanium haloalko species is 1:6 to 1:20 and the mole ratios of the electron donor and acid halide to titanium is 0.3 to 1.5 and 0.02 to 0.2, respectively.

Abstract: A method for producing a hydrorefining catalyst of the present invention has a step of preparing an aluminum solution containing phosphorus in a molar ratio of 0.001 to 0.05 with respect to aluminum; a step of neutralizing the prepared aluminum solution to produce a pseudo-boehmite powder; a step of forming the pseudo-boehmite powder followed by performing calcination at a temperature of not less than 650° C. to obtain a carrier; and a step of carrying a hydrogenation-active metal on the pseudo-boehmite powder or the carrier. The dispersion of the concentration distribution of phosphorus in the carrier of the obtained catalyst is within 10%. This method makes it possible to obtain the hydrorefining catalyst which has a practically sufficient mechanical strength and which has an excellent activity.

Abstract: A CO removal catalyst of inducing CO shift reaction for allowing water and carbon monoxide to react to produce hydrogen and carbon dioxide, comprising a catalyst carrier having a cerium-zirconium composite oxide and a zirconium oxide and a predetermined noble metal supported on the catalyst carrier, wherein the average particle diameter of the particulate cerium-zirconium composite oxide is greater than the average particle diameter of the particulate zirconium oxide, the average particle diameter of the particulate zirconium oxide is greater than the average particle diameter of the predetermined particulate noble metal and the predetermined noble metal is supported on the catalyst carrier more in the outer part thereof.

Abstract: A latent image developing system, a novelty kit, and an ink composition for printing latent images on a substrate. The latent image developing system includes a first substrate containing a colorless image deposited on a first surface thereof. A developer component is provided that is reactive with the colorless image to provide a visible image. The developer component is selected from a developer instrument, a developer finger paint, a developer coating on a first surface of a substantially transparent substrate for adhesive attachment to the first substrate, and a combination of one or more of the developer instrument, the developer finger paint, and the developer coating. The latent image developing system optionally includes, an image blocking instrument for concealing at least a portion of the visible image. The image blocking instrument includes a blocking composition applicator and an aqueous mixture of blocking composition and water.

Abstract: Disclosed are drilling fluids suitable for use in connection with oil well drilling. The drilling fluids of the invention include in one embodiment a liquid base, an alkyl glucoside, such as methyl glucoside, and a borehole stability promoter that includes a maltodextrin, a carboxyalkyl starch, a hemicellulose-containing material, or a mixture of the foregoing. In another embodiment, the drilling fluid includes a liquid base and molasses solids, preferably in combination with an alkyl glucoside and more preferably in further combination with one of the aforementioned borehole stability promoters. The drilling fluids of the invention surprisingly have a reduced tendency to swell shale as compared with known drilling fluids. Also disclosed are a drilling apparatus and process. The drilling apparatus includes a drill string, which may be conventional, that is fluidically coupled to a source of drilling fluid, the source of drilling fluid including the drilling fluid of the invention.

Abstract: A composition and method are given for self-destructive fluid loss additives and filter cakes in wellbores and subterranean formations. The fluid loss additives and filter cakes are formed from a mixture of particulate solid acid-precursors, such as a polylactic acid or a polyglycolic acid, and particulate solid acid-reactive materials, such as magnesium oxide or calcium carbonate. In the presence of water, the solid acid-precursors hydrolyze and dissolve, generating acids that then dissolve the solid acid-reactive materials. The composition is used in oilfield treatments such as drilling, completion and stimulation where it disappears when it is no longer needed without the use of mechanical means or injection of additional fluids.

Abstract: The rolling bearing of the invention to be incorporated in the compressor for fuel cell system comprises a fluorine-based grease containing a fluororesin and a fluorine-based oil, a urea grease containing a urea compound and a synthetic oil or a lithium complex grease containing a lithium complex and a synthetic oil encapsulated therein. In this arrangement, the grease deterioration of the rolling bearing incorporated in the compressor for force-feeding various fluids between machines can be prevented, making it possible to provide a fuel cell system which can maintain stable operation over an extended period of time.

Abstract: The present invention relates to a process of removing coloured stains from plastic by treating the substrate in an automatic dishwashing machine with an aqueous liquor comprising a hydrophobic component having a density in the range of 0.06 to 1 gram cm3.

Abstract: The invention relates to azeotropic and azeotrope-like mixtures of 1,1,1,3,3-pentachloropropane (HCC-240fa) and carbon tetrachloride and a process for separating the azeotrope-like mixtures. The compositions of the invention are useful as an intermediate in the production of HFC-245fa. The latter is useful as a nontoxic, zero ozone depleting fluorocarbon useful as a solvent, blowing agent, refrigerant, cleaning agent and aerosol propellant.