Patents Issued in September 11, 2007
  • Patent number: 7269012
    Abstract: A heat dissipation device includes a first heat sink (10), a second heat sink (20), a pair of heat pipes (30) connecting the first heat sink and the second heat sink and a fan assembly (40) located between the first heat sink and the second heat sink. The first heat sink comprises a base (12), a cover (14) and a plurality of heat dissipating fins (16) sandwiched between the base and the cover. The second heat sink comprises a plurality of cooling fins (22). Each heat pipe comprises three portions, respectively orderly sandwiched between the base and the heat dissipating fins, sandwiched between the cover and the heat dissipating fins and thermally extending in the cooling fins.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: September 11, 2007
    Assignees: Fu Zhun Precision Industry (Shenzhen) Co., Ltd., Foxconn Technology Co., Ltd.
    Inventors: Hsieh-Kun Lee, Wan-Lin Xia, Tao Li, Min-Qi Xiao
  • Patent number: 7269013
    Abstract: A heat dissipation device includes a heat dissipation body and a heat conducting body thermally combined with the heat dissipation device. The heat dissipation body includes a central portion defining a through hole therein and a plurality of fin extending from a periphery of the central portion. Each of the fins branches a plurality of portions at an end thereof. The heat conducting body includes a column thermally fitted in the through hole of the central portion of the heat dissipation body. A cavity is defined between the column and the central portion of the heat dissipation body. The cavity contains a phase-changeable medium therein, which becomes vapor once the column absorbs heat from a heat-generating electronic device.
    Type: Grant
    Filed: January 9, 2006
    Date of Patent: September 11, 2007
    Assignees: Fu Zhun Prexision Industry (Shan Zhen) Co., Ltd., Foxconn Technology Co., Ltd.
    Inventors: Chun-Chi Chen, Shi-Wen Zhou, Zhan Wu
  • Patent number: 7269014
    Abstract: A heat dissipation device for dissipating heat from an electronic element includes a heat spreader (12) for contacting with the electronic element, a conducting member (30) having a lower base plate (32) thermally contacting with the heat spreader and an upper base plate (34) with a plurality of first fins (36) extending downwardly from the upper base plate towards the lower base plate and a connecting portion (33) interconnecting the lower and upper base plate. A plurality of second fins (38) is mounted on the conducting member. A plurality of heat pipes (40) thermally connects the heat spreader and the conducting member and the second fins to transfer heat from the heat spreader to the conducting member and the second fins. A fan (20) is mounted adjacent to air passages of the first and second fins for generating a forced airflow through the air passages.
    Type: Grant
    Filed: March 15, 2006
    Date of Patent: September 11, 2007
    Assignees: Fu Zhun Precision Industry (Shen Zhen) Co., Ltd., Foxconn Technology Co., Ltd.
    Inventors: Liang-Hui Zhao, Yi-Qiang Wu
  • Patent number: 7269015
    Abstract: A heat sink assembly for cooling a heat generating integrated circuit (IC) component is provided. The assembly includes a heat sink base positioned adjacent the IC component and a thermal interface member positioned between the heat sink base and the IC component. The interface member has a first surface in abutting engagement with the heat sink base and an opposite second surface in abutting engagement with an outer surface of a lid on the IC component. The first and second surfaces each include a plurality of protrusions to increase a number of contact points between the interface member and the heat sink base and between the interface member and the outer surface of the lid to facilitate a transfer of heat from the IC component to the heat sink base.
    Type: Grant
    Filed: February 1, 2005
    Date of Patent: September 11, 2007
    Assignee: Tyco Electronics Corporation
    Inventors: Craig Warren Hornung, John Thomas Larkin, Jr., Ralph Edward Spayd, Jr.
  • Patent number: 7269016
    Abstract: A heat dissipating device includes a heat sink and a clip attached on the heat sink. The heat sink includes a solid trunk and a plurality of fins extending radially outwardly from a circumference of the trunk. A rectangular extension portion is formed at a bottom end of the trunk. A pressing portion extends from the extension portion and abuts against the clip toward the heat sink in an axial direction of the heat sink. The clip defines a rectangular opening fittingly receiving the extension portion to thereby form a positioning structure for preventing the clip from moving relative to the heat sink in a circumferential direction of the heat sink.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: September 11, 2007
    Assignees: Fu Zhun Precision Industry (Shenzhen) Co., Ltd., Foxconn Technology Co., Ltd.
    Inventors: Jin-Liang Wang, Gen-Cai Wang, Wei-Guo Zhou
  • Patent number: 7269017
    Abstract: A circuit board assembly with a substrate having a laminate construction of ceramic layers, such as an LTCC ceramic substrate. The substrate is configured for the purpose of improving the thermal management of power circuit devices mounted to the substrate. Thermally-conductive vias extend through the substrate from a first surface thereof to a second surface thereof. A circuit device is mounted to the first surface of the substrate and is electrically interconnected to conductor lines of the substrate. The device is also thermally coupled to the thermally-conductive vias with a first solder material. A heat sink located adjacent the second surface of the substrate is bonded to the thermally-conductive vias with a second solder material, such that the first solder material, the thermally-conductive vias, and the second solder material define a thermal path from the device to the heat sink.
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: September 11, 2007
    Assignee: Delphi Technologies, Inc.
    Inventors: Carl W. Berlin, Dwadasi Hara Rama Sarma, Bruce A. Myers
  • Patent number: 7269018
    Abstract: A plurality of heat sinks in one example is coupled to a support structure. The support structure has a plurality of independent spring force elements that respectively contact the plurality of heat sinks such that each heat sink of the plurality of heat sinks is moveable within the support structure relative to the other heat sinks of the plurality of heat sinks. The support structure is coupled to a substrate having a plurality of components, each of the components having an upper surface, at least two of the upper surfaces being non-coplanar. The non-coplanar upper surfaces of the components are respectively coupled to the plurality of heat sinks by respective thermal interfaces.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: September 11, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Bryan Bolich, Gwynn M. Masada
  • Patent number: 7269019
    Abstract: A driving device for a motor has a mounting substrate mounted to a base substrate. Highly heat-generating components such as a switching element for PWM control are mounted to the mounting substrate and only less heat-generating circuit components are mounted to the base substrate. The mounting substrate has a base plate part made of a metallic plate material surround by a molded insulating material but includes a heat dissipating part where the insulating material is removed and the internal metallic plate material is exposed.
    Type: Grant
    Filed: June 25, 2005
    Date of Patent: September 11, 2007
    Assignee: OMRON Corporation
    Inventors: Akihiko Hirata, Tokihiko Sugiura, Yasuhide Tanaka
  • Patent number: 7269020
    Abstract: A mounting device, for mounting a bezel (50) to cover an opening of a chassis (10) which is received in a cabinet (4), includes a pair of sliding units (20), a locking plate (30) attached to the chassis and the cabinet, and a pair of bent plates attached to opposite ends of the bezel. The sliding unit includes a horizontal member (22) attached to the chassis, a vertical member attached to the bezel, and a sliding member horizontally movably attached to the horizontal member and vertically movably attached to the vertical member. The bezel is movable from a first position in which the bent plates are engaged with the locking plates and the bezel covers the opening to a second position in which the bezel is moved away from the opening without detached from the chassis. Electronic components mounted in the chassis are therefore movable through the opening for maintenance.
    Type: Grant
    Filed: May 12, 2004
    Date of Patent: September 11, 2007
    Assignee: Hon Hai Precision Ind. Co., Ltd.
    Inventors: Yu-Jiun Wang, Ching-Mao Lin
  • Patent number: 7269021
    Abstract: A smart card contains a carrier body for receiving at least one system component, which has (in each case) a plurality of electrical components, and which unites the electrical functions for the operation of the smart card. The system component terminates approximately evenly with the top side of the card body of the smart card. At least one of the electrical components is accessible from the top side of the smart card.
    Type: Grant
    Filed: November 5, 2002
    Date of Patent: September 11, 2007
    Assignee: Infineon Techonologies AG
    Inventors: Harald Gundlach, Jochen Müller
  • Patent number: 7269022
    Abstract: A connecting device with a low height comprises a connector part, and a set of metal terminals. The connector part has a height compatible with the height of an inner space in a standard USB interface slot socket so as to be inserted into the standard USB interface slot socket. The set of metal terminals is arranged on the connector part and composed of a plurality of metal sheets and each metal sheet has an end disposed in the connector part and another end extending outward the connector part. The first end of the respective metal sheet in the set of metal terminals contacts with internal electronic signal of the standard USB interface slot socket and the second end of the respective metal sheet is soldered to a printed circuit board. Furthermore, the low height connecting device can be revised as an electronic connecting device capable of being inserted into the USB slot socket so that both of the connecting devices can be used in a dual interface memory storage apparatus or a memory storage apparatus.
    Type: Grant
    Filed: August 11, 2003
    Date of Patent: September 11, 2007
    Assignee: Power Quotient International Co., Ltd.
    Inventor: Sheng Shun Yen
  • Patent number: 7269023
    Abstract: Left and right heat radiating plates are mounted on the rear side of a liquid crystal display panel in respective left and right positions thereon. The left and right heat radiating plates are of a substantially L-shaped cross section including a plurality of fins and respective supports near the center of the rear side of the liquid crystal display panel. A central rear cover has a plurality of fins and has left and right ends fixedly mounted respectively on the supports of the left and right heat radiating plates in covering relation to a circuit assembly on the rear side of the liquid crystal display panel. Left and right rear covers are mounted respectively on rear sides of the left and right heat radiating plates and lie substantially flush with the central rear cover.
    Type: Grant
    Filed: July 11, 2005
    Date of Patent: September 11, 2007
    Assignee: Sony Corporation
    Inventor: Masahiro Nagano
  • Patent number: 7269024
    Abstract: A retainer secures one or more printed wiring assemblies in a processor unit. In one embodiment, the retainer has one or more protuberances that abut against a wiring assembly to secure it in place, or sit within a cutout section in the wiring assembly to secure the assembly in a serviceable position.
    Type: Grant
    Filed: April 15, 2005
    Date of Patent: September 11, 2007
    Assignee: Honeywell International Inc.
    Inventor: Mark V. Striano
  • Patent number: 7269025
    Abstract: In some embodiments, a multichip package includes mounting pads to mount devices, such as integrated circuits, to a substrate, such as a printed circuit board, so that devices mutually placed on opposite surfaces of the substrate do not have interfering connections or connection vias. Other embodiments are described.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: September 11, 2007
    Assignee: Intel Corporation
    Inventor: Howard David
  • Patent number: 7269026
    Abstract: A plasma display apparatus includes: a Plasma Display Panel (PDP) adapted to display images; a chassis base arranged on a rear portion of the PDP; printed circuit boards arranged on a rear portion of the chassis base and adapted to drive the PDP, the printed circuit boards including substrate connectors respectively arranged at front portions thereof; and connection cables adapted to electrically connect the PDP to the printed circuit boards and to electrically connect the printed circuit boards to each other, the connection cables including a wiring member and a cable connector having two sides. One side of the cable connector is affixed to the chassis base and the other side of the cable connector is coupled to one of the substrate connectors and to at least an end of the wiring member.
    Type: Grant
    Filed: December 7, 2005
    Date of Patent: September 11, 2007
    Assignee: Samsung SDI Co., Ltd.
    Inventor: Kwang-Jin Jeong
  • Patent number: 7269027
    Abstract: Optoelectronic components, specifically, ceramic optical sub-assemblies are described. In one aspect, the optoelectronic component includes a ceramic base substrate having a pair of angled (or substantially perpendicular) faces. The electrical traces are formed directly on the ceramic surfaces and extend between the pair of faces. A semiconductor chip assembly is mounted on the first face of the ceramic base substrate and a photonic device is mounted on the second face. Both the semiconductor chip assembly and the photonic device are electrically connected to traces on the ceramic base substrate. The semiconductor chip assembly is generally arranged to be electrically connected to external devices. The photonic devices are generally arranged to optically communicate with one or more optical fibers. The described structure may be used with a wide variety of photonic devices.
    Type: Grant
    Filed: January 31, 2006
    Date of Patent: September 11, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Jia Liu, Luu Thanh Nguyen, Ken Pham, William Paul Mazotti, Bruce Carlton Roberts, Stephen Andrew Gee, John P. Briant
  • Patent number: 7269028
    Abstract: A method of routing or laying out signal traces on printed wire or circuit board in order to improve signal transmission quality. The method includes routing a given signal trace such that it is electrically connected to a rectangular corner of a substantially wider component pin pad and forms an angle of approximately 135 degrees with the proximate sides of the pad, thereby minimizing the impedance discontinuity at the interface or junction of the signal trace and pad and hence minimizing the reflection of the digital signal at the interface or junction.
    Type: Grant
    Filed: December 19, 2000
    Date of Patent: September 11, 2007
    Assignee: Celestica, Inc.
    Inventors: Jacqueline V. Csonka, Ignatius T. Chong
  • Patent number: 7269029
    Abstract: A test board for testing a packaged integrated circuit has a set of contacts matching counterpart contacts on a socket. The contacts are each connected to a first voltage plane containing power, a second voltage plane carrying ground, and a set of terminals that will be connected to a tester system. The number of terminals necessary to operate the circuit is identified, both power terminal and signal-carrying terminals to the affected part of the circuit, and two of the three connections to the contacts are severed; e.g. the terminal carrying signals is disconnected from the power and ground. The disconnect from the voltage planes may be performed by an automated milling machine in a short time, providing much faster turnaround than a method that forms a custom-made board.
    Type: Grant
    Filed: November 9, 2004
    Date of Patent: September 11, 2007
    Assignee: International Business Machines Corporation
    Inventor: Richard W. Oldrey
  • Patent number: 7269030
    Abstract: Remote enclosure systems have now been designed that meet the following goals: a) consolidates electrical terminations in one system; b) pre-terminates AC and DC equipment loads before site installation; c) provides multiple access points for facilitating equipment repair and installation; d) is easily expanded through the use of additional systems or expansion cabinets and e) is aesthetically functional given the cable entry and routing structure. Remote enclosure systems generally comprise: a) a frame system further comprising at least two side panels; b) at least one door coupled to the frame system; c) at least one removable radiofrequency (RF) port plate coupled to at least one of the side panels and/or the frame system; d) a bottom panel coupled to the frame system; and e) a cable management top assembly coupled to the frame system.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: September 11, 2007
    Assignee: Purcell Systems, Inc.
    Inventors: William Miller, Kelly Johnson
  • Patent number: 7269031
    Abstract: A board-mounting device (20) which includes a base carrier (10) that can be snapped down on a board (14). The base carrier (10) includes at least one locking hook (22) which engages behind the board (14) in the mounted condition of the device (20). The device (20) further includes a device carrier (11), connected with the base carrier (10), which is adapted to be moved relative to the base carrier (10). The locking hook (22) is provided with at least one shoulder (43) on which the device carrier (11) is supported by at least one guide pin (31, 40, 50, 60) before the device (20) is in its mounted condition.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: September 11, 2007
    Inventor: Klaus Lorenzen
  • Patent number: 7269032
    Abstract: A shielding apparatus for EMI-sensitive electronic components, especially for radio transmitting devices and/or radio receiving devices of telecommunication terminals for contactless telecommunication, such as cordless telephones and mobile telephones and similar, which can be constructed without using expensive manufacturing and assembly steps without any extra space requirement. The EMI-sensitive electronic components and/or circuits are arranged on a separate, at least double-layered printed circuit board and are embodied as a printed circuit board module.
    Type: Grant
    Filed: July 2, 2004
    Date of Patent: September 11, 2007
    Assignee: Siemens Aktiengesellschaft
    Inventor: Matthias Lungwitz
  • Patent number: 7269033
    Abstract: A suppressor device for an electronic device comprising a plug-in device, comprising at least one plug element, which is arranged on a electrically conducting housing of the electronic device. A printed circuit board is arranged in the housing and bears an electronic circuit leading to the plug element. A capacitor is connected to the plug element and to the potential of the housing. The capacitor is arranged on the printed circuit board which protrudes from the inner part of the housing through an opening with a part thereof and which is also extends from the inner part of the housing to the outer side of the housing. The plug element is conductively connected to the capacitor and the circuit on the part of the printed circuit board located on the outer part of the housing.
    Type: Grant
    Filed: June 18, 2003
    Date of Patent: September 11, 2007
    Assignee: Siemens Aktiengesellschaft
    Inventor: Reinhold Berberich
  • Patent number: 7269034
    Abstract: A power converter nearly losslessly delivers energy and recovers energy from capacitors associated with controlled rectifiers in a secondary winding circuit, each controlled rectifier having a parallel uncontrolled rectifier. First and second primary switches in series with first and second primary windings, respectively, are turned on for a fixed duty cycle, each for approximately one half of the switching cycle. Switched transition times are short relative to the on-state and off-state times of the controlled rectifiers. The control inputs to the controlled rectifiers are cross-coupled from opposite secondary transformer windings.
    Type: Grant
    Filed: August 23, 2006
    Date of Patent: September 11, 2007
    Assignee: SynQor, Inc.
    Inventor: Martin F. Schlecht
  • Patent number: 7269035
    Abstract: A switching device and a method of operating a switching power element are disclosed for generating a train of drive pulses (D1 to D32) in a basic pattern for a repetition cycle time (T to TF) having leading time intervals (Th1 to Th3, Th1? to Th3?), associated with leading edges (a1 to a32) of the drive pulses, and trailing time intervals (Tl1 to Tl3, Tl1? to Tl3?), associated with trailing edges (b1 to b32) of the drive pulses, which are different from each other, whereby switching frequencies and associated harmonics, resulting from the leading edges and the trailing edges of the drive pulses, are diffused. A diffusion frequency, representing an inverse number of the repetition cycle time for the basic pattern is set to be higher than an audible frequency.
    Type: Grant
    Filed: April 3, 2006
    Date of Patent: September 11, 2007
    Assignees: Denso Corporation, Nippon Soken, Inc.
    Inventors: Koji Kawasaki, Keiji Shigeoka, Shinya Goto
  • Patent number: 7269036
    Abstract: An electrical power converter system adjusts a wakeup voltage periodically, to permit earlier connection and/or operation, to increase performance. The electrical power converter system selects between a mathematically adjusted wakeup voltage based on at least one previous period, and a table derived wakeup voltage that takes into account historical information. The electrical power converter system is particularly suited to applications with periodicity such as solar based photovoltaic power generation.
    Type: Grant
    Filed: May 12, 2004
    Date of Patent: September 11, 2007
    Assignee: Siemens VDO Automotive Corporation
    Inventors: Duo Deng, Anil Tuladhar, Kent M. Harmon
  • Patent number: 7269037
    Abstract: A power supply includes a direct converter provided in the form of a two-phase or three-phase bridge circuit. The bridge branche of the direct converter includes a serial connection of any number of identical two-terminal networks, each having the following characteristics: The two-terminal networks each have at least one switching state, in which their terminal voltage takes on positive values independent of the magnitude and polarity of the terminal current; the two-terminal networks each have at least one switching state, in which their terminal voltage takes on negative values independent of the magnitude and polarity of the terminal current; the two-terminal networks have at least one internal energy store.
    Type: Grant
    Filed: April 16, 2003
    Date of Patent: September 11, 2007
    Assignee: Siemens Aktiengesellschaft
    Inventor: Rainer Marquardt
  • Patent number: 7269038
    Abstract: A synchronous full bridge rectifier is controlled to provide a power factor near unity. The full bridge rectifiers are transistors each with a controlling input. The AC input signal and currents within the circuit are sensed and sent to a controller. In response, the controller output control signals to turn on/off the rectifying MOSFETS on a timely basis to form a power factor of near one with respect to the AC input signal. The full wave rectifier is made of N-channel MOSFET's, some with fast body diodes. The MOSFET's are rectifiers and PFC control elements. The result is a one stage synchronous rectifier with PFC. A solid state precision analog differential amplifier senses the AC line waveform and high frequency current transformers sense the currents. The controller accepts the inputs of the amplifier and the sensed currents and outputs control signals that turn on and off the four MOSFET's.
    Type: Grant
    Filed: September 12, 2005
    Date of Patent: September 11, 2007
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Sampat Shekhawat, Ronald H. Randall, Dong-Young Huh
  • Patent number: 7269039
    Abstract: A device includes an active rectifier (14) having control gates controllable to produce an output voltage on a DC bus (20), a gate control circuit (16) for producing gate control signals for controlling the active rectifier control gates, a first circuit (18) connected to the gate control circuit (16) for producing a command current magnitude signal and a power factor signal for use by the gate control circuit (16), a current line (30) providing a signal related to the DC load current to the first circuit (18), and a voltage line (32) providing a signal related to the DC bus voltage to the first circuit (18). The first circuit (18) includes a command current magnitude signal generator (34) producing the command current signal based on the DC load current and a power factor controller (44, 48) producing the power factor signal. The power factor controller (44, 48) includes a feed forward circuit (52, 56) for increasing the power factor signal in response to current fluctuations on the current line (30).
    Type: Grant
    Filed: August 19, 2005
    Date of Patent: September 11, 2007
    Assignee: Honeywell International Inc.
    Inventor: Louis Cheng
  • Patent number: 7269040
    Abstract: A static content addressable memory (CAM) cell. The CAM cell includes a latch having complementary data nodes capacitively coupled to ground, first and second access transistors, each coupled between a data node of the latch and a respective data line. The gates of each access transistor is coupled to a word line such that when activated, the respective data node and data line are coupled. The CAM cell further includes a match circuit coupled to one of the complementary data nodes of the latch. The match circuit discharges a match line in response to a data value stored at the data node to which the match circuit is coupled and compare data present on the respective data line mismatching. Two of the CAM cells can be used to implement a full ternary CAM cell.
    Type: Grant
    Filed: January 12, 2006
    Date of Patent: September 11, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Shane Ching-Feng Hu
  • Patent number: 7269041
    Abstract: A multi-port memory device that prevents degradation of efficiency of a global data drive by turning off the switches, which do not discharge a global data bus. The multi-port memory device includes a global data bus, a banks, each bank including a transmitter and a receiver; ports, each port including a transmitter and a receiver; switches that operate to selectively connect the receivers of the banks and ports to the global data bus; and a switch signal generator for generating a switch signal in response to data drive pulses inputted to the transmitters of the banks and the ports.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: September 11, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kyung-Whan Kim, Jae-Jin Lee
  • Patent number: 7269042
    Abstract: A method of forming a stacked memory module from a plurality of memory devices is provided. Each of the plurality of memory devices is modified to include a logic block for decoding a plurality of chip select signals. A first high density memory module is also provided that includes the modified memory devices and a serial presence detect device. The first high density memory module is included within an electronic system. Also, an additional method of forming a stacked memory module is provided, the method requiring modification of an address buffer to include a logic block for decoding a plurality of chip select signals. A second high density memory module is also provided that includes the modified address buffer and a serial presence detect device. The second high density memory module is included within an electronic system.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: September 11, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Thomas H. Kinsley, Kevin M. Kilbuck
  • Patent number: 7269043
    Abstract: Disclosed is a memory module and a method of calibrating an impedance of a semiconductor memory device of the memory module, where the memory module includes semiconductor memory devices each having a separate terminal for calibrating impedance characteristics, and a reference resistor commonly connected to the separate terminals, such that the number of reference resistors used in calibration of impedance characteristics of an off-chip driver or an on-die termination circuit of the semiconductor memory device is reduced.
    Type: Grant
    Filed: March 17, 2005
    Date of Patent: September 11, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jung-Bae Lee
  • Patent number: 7269044
    Abstract: A memory device including first and second memory elements is provided. The first and second memory elements each have first and second electrodes. The first electrode of the first and second memory elements is a common first electrode and is located below the second electrodes. A first line is connected to the second electrode of the first memory element and a second line connected to the second electrode of the second memory element. The first and second lines are switchably connected to a third line for applying a voltage to the second electrodes. Methods of operating a memory device are also provided.
    Type: Grant
    Filed: April 22, 2005
    Date of Patent: September 11, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Jon Daley
  • Patent number: 7269045
    Abstract: A magnetic random access memory includes memory cells which store information using an internal magnetization direction. A first write line includes a first extending portion, a second extending portion and a first connection portion. The first extends portion extends along a first direction and has a first end and a second end. The second extending portion extends along the first direction and has a third end facing the first end and a fourth end facing the second end. The first connection portion connects the first end and the third end. A second write line and the first write line sandwiches one of the memory cells. First peripheral circuits are connected to the first connection portion and to at least one of the second end and the fourth end.
    Type: Grant
    Filed: September 2, 2005
    Date of Patent: September 11, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuui Shimizu, Yoshihisa Iwata
  • Patent number: 7269046
    Abstract: A floating-gate transistor array and method for programming the same. The floating-gate transistor array includes a plurality of transistors having a source, drain, and floating-gate, whereby the plurality of transistors is arranged into multiple rows and columns. Each row of transistors includes a row programming switch having an output connected to each floating-gate within the row, while each column of transistors includes a column programming switch having an output connected to each drain within the column. The source of each transistor is coupled with a source line corresponding to the specific row of the transistor. The row and column programming switches are utilized to select and program a desired floating-gate transistor. In an indirect programming method, two transistors share a floating gate, such that programming a programmer transistor modifies the current of an agent transistor, which is attached to the circuit, thereby permitting run-time programming.
    Type: Grant
    Filed: May 10, 2006
    Date of Patent: September 11, 2007
    Assignee: Georgia Tech Research Corporation
    Inventors: David W. Graham, Ethan Farquhar, Jordan Gray, Christopher M. Twigg, Brian Degnan, Christal Gordon, David Abramson, Paul Hasler
  • Patent number: 7269047
    Abstract: Methods and apparatus for decreasing oxide stress and increasing reliability of memory transistors are disclosed. Duration and frequency of exposure of memory transistor gates to read signals are significantly reduced. In some embodiments, after a short read cycle, the content of the memory cell is latched and maintained as long as the subsequent read attempts are directed to the same memory cell. In these embodiments the read cycle need only be long enough to latch the memory content of the cell, and as long as the subsequent read attempts target the same memory cell the latched value will be used instead of repeating the read process.
    Type: Grant
    Filed: March 6, 2006
    Date of Patent: September 11, 2007
    Assignee: Kilopass Technology, Inc.
    Inventors: David Fong, Jianguo Wang, Jack Zezhong Peng, Harry Shengwen Luan
  • Patent number: 7269048
    Abstract: A semiconductor integrated circuit device includes a plurality of first memory cells each of which includes a cell transistor whose gate terminal is connected to a word line and a ferroelectric capacitor which is connected at one end to a source terminal of the cell transistor. The drain terminals of the cell transistors of are used as a first local bit line, the other end of each of the ferroelectric capacitors are used as a first plate line. A first reset transistor has a source terminal connected to the first plate line and a drain terminal connected to the first local bit line. A first block selection transistor has a source terminal connected to the first local bit line and a drain terminal connected to a first bit line.
    Type: Grant
    Filed: November 16, 2004
    Date of Patent: September 11, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Daisaburo Takashima
  • Patent number: 7269049
    Abstract: A plurality of ferroelectric memory cells is arrayed. One terminal of each memory cells arrayed in the same column is connected in common to a first bit line. A gate of a transistor of memory cells arrayed in the same row is connected in common to a word line. The other terminal of each of memory cells arrayed in the same column or the same row is connected in common to a cell plate line. A second bit line is connected with a reference voltage supply circuit. The first and second bit lines are connected with a data read circuit. The data read circuit includes a sense amplifier and a current mirror circuit having a pair of current input node connected to the first and second bit lines, and carrying the same current flowing through one of the first and second bit line to the other bit line.
    Type: Grant
    Filed: February 1, 2005
    Date of Patent: September 11, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidehiro Shiga, Shinichiro Shiratake, Daisaburo Takashima
  • Patent number: 7269050
    Abstract: The present invention is a method of programming a memory device, wherein different levels or magnitudes of current may be applied to and imposed on the memory device so that any one of a plurality of memory states may be realized. A read step indicates the so determined state of the memory device.
    Type: Grant
    Filed: June 7, 2005
    Date of Patent: September 11, 2007
    Assignee: Spansion LLC
    Inventors: Swaroop Kaza, David Gaun, Stuart Spitzer, Juri Krieger
  • Patent number: 7269051
    Abstract: The present invention provides an inspection method of an array board and an inspection equipment thereof, which can detect a disconnection failure of a gate line even if electric potentials are applied from both ends of the gate line.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: September 11, 2007
    Assignee: International Business Machines Corporation
    Inventor: Tomoyuki Taguchi
  • Patent number: 7269052
    Abstract: A memory system having electromechanical memory cells and decoders is disclosed. A decoder circuit selects at least one of the memory cells of an array of such cells. Each cell in the array is a crossbar junction at least one element of which is a nanotube or a nanotube ribbon. The decoder circuit is constructed of crossbar junctions at least one element of each junction being a nanotube or a nanotube ribbon.
    Type: Grant
    Filed: October 10, 2006
    Date of Patent: September 11, 2007
    Assignee: Nantero, Inc.
    Inventors: Brent M. Segal, Darren K. Brock, Thomas Rueckes
  • Patent number: 7269053
    Abstract: A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region.
    Type: Grant
    Filed: November 16, 2004
    Date of Patent: September 11, 2007
    Assignee: Fujitsu Limited
    Inventors: Toru Anezaki, Tomohiko Tsutsumi, Tatsuji Araya, Hideyuki Kojima, Taiji Ema
  • Patent number: 7269054
    Abstract: A nonvolatile semiconductor memory device is provided for a high-powered system without the need for an additional system setting process to set the system initialization state after power-on to the previous state. The nonvolatile semiconductor memory device comprises a pull-up driving unit configured to include a plurality of nonvolatile cells for storing inputted data and to pull up a storage node, a pull-down driving unit configured to pull down the storage node, and a plurality of data registers including a data input/output unit configured to selectively input/output data between a bit line and the storage node depending on a voltage applied to a word line.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: September 11, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hee Bok Kang, Jin Hong Ahn
  • Patent number: 7269055
    Abstract: The present invention discloses a memory device with a leakage current reduction feature. The memory device includes at least one memory cell for storing a value, and at least one switch module coupled to the memory cell for generating an operating voltage at various levels depending on various operation modes of the memory cell. The operating voltage is at a first level when the memory cell is being accessed, and is at a second level lower than the first level when the memory cell is not being accessed, thereby reducing a leakage current for the memory cell.
    Type: Grant
    Filed: February 13, 2006
    Date of Patent: September 11, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wesley Lin, Fang-Shi Jorcan Lai
  • Patent number: 7269056
    Abstract: Disclosed is an improved power grid design for split-word line style memory cell. An array of memory cells comprises a first metal layer for local interconnections; a second metal layer for a bit line, a complementary bit line, and a first voltage line located between the bit line and the complementary bit line; a third metal layer for a first plurality of second voltage lines, and a word line located between the first plurality of second voltage lines, each running substantially in a first direction; and a fourth metal layer for a second plurality of second voltage lines, each running in a second direction orthogonal to the first direction.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: September 11, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 7269057
    Abstract: A method for connecting circuit elements within an integrated circuit for reducing single-event upsets is disclosed. The integrated circuit includes a first and second circuit elements that are substantially identical to each other. In order to reduce the single-event upsets to the first and second circuit elements, each of the first and second circuit elements is divided into a first sub-element and a second sub-element. The first sub-element of the first circuit element is connected to the second sub-element of the second circuit element. The second sub-element of the first circuit element is connected to the first sub-element of the second circuit element. As a result, the nodal spacings between the sub-elements within the first and second circuit elements are effectively increased without demanding additional real estate.
    Type: Grant
    Filed: April 27, 2005
    Date of Patent: September 11, 2007
    Assignee: BAE Systems Information And Electronic Systems Integration Inc.
    Inventors: Nadim F. Haddad, Neil E. Wood, Adam Bumgarner, Wayne Neiderer, Shankarnarayana Ramaswamy, Scott Doyle, Tri-Minh Hoang
  • Patent number: 7269058
    Abstract: A system and method for preserving an error margin for a non-volatile memory that includes a memory cell, a reference cell coupled to a reference current mirror configured to mirror current through the reference cell. The system comprises a memory current mirror coupled to the memory cell and configured to mirror current through the memory cell. A sense amplifier has a first and a second input. The first input is coupled to the reference current mirror and the second input is coupled to the memory current mirror. The sense amplifier is configured to compare a voltage across the memory cell with a voltage across the reference cell.
    Type: Grant
    Filed: May 9, 2005
    Date of Patent: September 11, 2007
    Assignee: Atmel Corporation
    Inventors: Massimiliano Frulio, Fabio Tassan Caser, Lorenzo Bedarida, Mirella Marsella
  • Patent number: 7269059
    Abstract: A magnetic recording element, in which a spin-polarized electron is injected, has a layer whose magnetization direction is changed by the spin-polarized electron in accordance with a flow direction of the spin-polarized electron and records data in accordance with the magnetization direction. The magnetic recording element includes a free layer whose magnetization direction is changed by an action of a spin-polarized electron and has a spin polarization Pf. A pinned layer whose magnetization direction is fixed has a spin polarization Pp larger than the spin polarization Pf. An intermediate layer is interposed between the pinned layer and the free layer and consisting essentially of a nonmagnetic material.
    Type: Grant
    Filed: June 8, 2005
    Date of Patent: September 11, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirofumi Morise, Shiho Nakamura, Shigeru Haneda
  • Patent number: 7269060
    Abstract: A magnetic random access memory includes first write lines separated from one another and extending along a first direction. Second write lines extend in a direction different from the first direction. The MTJ elements are provided between the first write lines and the second write lines. Connection lines connect the first write lines. Sinkers are connected to ends of the first write lines and to the first write lines at between the connection lines and extract currents from the first write lines. Drivers are connected to ends of the first write lines and supply currents to the first write lines.
    Type: Grant
    Filed: December 12, 2005
    Date of Patent: September 11, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryousuke Takizawa, Kenji Tsuchida, Tsuneo Inaba
  • Patent number: 7269061
    Abstract: A magnetic memory has a first, a second and a third magnetic transistor. The first magnetic transistor has a first magnetic section and a second magnetic section, wherein the first magnetic section couples to a high voltage end. The second magnetic transistor has a third magnetic section and a fourth magnetic section, wherein the third magnetic section couples to a low voltage end, and the fourth magnetic section couples to the second magnetic section of the first magnetic transistor. The third magnetic transistor has a fifth magnetic section and a sixth magnetic section, wherein the fifth magnetic section couples with the second magnetic section and the fourth magnetic section together, and the sixth magnetic section couples to an input/output end.
    Type: Grant
    Filed: October 13, 2006
    Date of Patent: September 11, 2007
    Assignee: Northern Lights Semiconductor Corp.
    Inventors: Tom Allen Agan, James Chyi Lai