Abstract: A phantom for evaluating a magnetic resonance spectroscopy (MRS) performance is provided. Specifically, a phantom for evaluating an MRS performance capable of quantitatively evaluating a resolution of a spectrum obtained when a chemical shift imaging MRS measurement process is performed is provided. The phantom evaluates MRS performance using a magnetic resonance imaging (MRI) apparatus, and includes: an external container having an opened upper end; internal containers which are disposed in the external container and constructed so as to include metabolites; and an external container cover for covering the upper end of the external container.

Abstract: The invention relates to a magnetic resonance unit, with a magnet generating a static magnetic field, in the hollow space of which an essentially tubular inner lining is disposed, into which a patient support device can be introduced, and with control elements disposed on a front lining to control the magnetic resonance unit. It is possible to introduce the patient support device and the inner lining, which surrounds the patient support device and can be moved in relation to the patient support device, into the hollow space of the magnet and to remove them therefrom together.

Abstract: A compact and integrated portable device is provided for the analysis of dispersions by low-field pulsed NMR including: an NMR probe module, a means for generating radio frequency and magnetic field gradient pulses, a signal processor, and a master controller. Also provided are methods for using the device to measure one or more characteristics of phases or particles comprising a dispersion such as surface area, solid/liquid ratio, particle size, and elemental analysis.

Abstract: A multicomponent induction logging tool is used on a MWD bottomhole assembly. Multifrequency focusing that accounts for the finite, nonzero, conductivity of the mandrel is applied. Using separation of modes, the principal components and relative dip angles in an earth formation are determined. The results are used for reservoir navigation in an earth formation. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A remote-controlled battery charging/testing system includes an execution unit capable of performing at least one battery-related function and a control panel remotely connected to and in operable communication with the execution unit. Communication may be wired or wireless. The control panel is installed in an ergonomically-suitable position such that the user does not need to bend or stoop to provide input to the battery charging/testing system. Both the execution unit and the control panel may be cart-mounted for portability and mobility. In cart-mounted configurations, the control panel is adjustable to maintain an ergonomically-suitable position. In free-standing configurations, the execution unit may be installed so as to be conveniently located yet unobtrusive, with the control panel installed in an ergonomically-suitable, accessible position.

Abstract: A battery testing/charging system includes an execution unit, such as a battery tester/charger, a receptacle configured to receive an external booster pack, and an outlet configured to power the booster pack when the booster pack is connected to the outlet. The receptacle removably receives the booster pack, such that the booster pack can be removed and separately carried when the execution unit is not required. The receptacle may be integrated with the execution unit. Alternatively, the execution unit may be mounted on a cart, and the receptacle integrated with the cart. The cart may also include an accessory storage tray and an output device bracket. The execution unit may receive partial or total power from the booster pack.

Abstract: There is provided an electronic device having an operation circuit for outputting an output signal to be tested or evaluated and a demodulator that receives the output signal from the operation circuit to output a demodulation signal in which a phase-modulated or frequency-modulated component of the output signal is demodulated.

Abstract: A circuit arrangement is disclosed herein comprising a first and a second supply terminal for application of a supply voltage and an output terminal for providing an output signal. The circuit arrangement additionally comprises at least one programmable switch arrangement comprising a normally off MOS transistor, which has a load path between a first and second load terminal and a control electrode, and comprising a capacitive component, having a first and a second terminal, the first terminal of which is connected to the control electrode of the MOS transistor and the second terminal of which is connected to a control and programming terminal. In this case, the load path of the MOS transistor is connected between the output terminal and one of the supply terminals.

Abstract: A load abnormality detecting system and method for detecting the burnout and short circuit of a load are provided. A voltage generator (10) generates a specified voltage Vs in accordance with a load current IL. A judging device (4) compares a signal corresponding to this voltage (Vs) with a specified reference value (T1, T2) to judge whether a load (2) has any abnormality. A selector (6) causes the burnout reference value (T1) to be inputted to the judging device (4) and controls the voltage generator (10) to use a first resistance value when checking the burnout of the load (2) while causing the short-circuit reference value (T2) to be inputted to the judging device (4) and controlling the voltage generator (10) to use a second resistance value when checking the short circuit of the load (2).

Abstract: An alternating signal from a signal generator is applied to a direct current source via a detecting resistor and a coupling capacitor. A detecting member detects a voltage amplitude change appeared at a contact between the detecting resistor and the coupling capacitor. Based on the voltage amplitude change, a correction member corrects a first measuring voltage when a capacitor is connected to a contact between an anode of the direct current source and a ground, and a second measuring voltage when the capacitor is connected to a contact between a cathode of the direct current source and the ground. Based on the corrected first and second measuring values and a voltage across the direct current source when the capacitor is connected to the anode and the cathode of the direct current source by a voltage measuring member, a calculation member calculates a resistance between the direct current source and the ground.

Abstract: The present invention provides a fuel cell electric power sensing methodology and the applications thereof.

Abstract: A capacitive humidity sensor includes a detecting portion and a reference portion. The detecting portion includes a first sensor element, and a capacitance of the first sensor element varies in accordance with humidity. The reference portion includes a second sensor element and a capacitor. The second sensor element is connected to the first sensor element in series, and a capacitance of the second sensor element varies in accordance with the humidity. The capacitor has a constant capacitance relative to a humidity variation. The first sensor element has a gradient of a capacitance variation to the humidity variation, which is different from a gradient of the second sensor element.

Abstract: A real-time multi-point ground resistance monitoring device is provided herein to simultaneously monitor ground resistances of different work stations. The present invention mainly contains a number of monitoring ports connected to multiple test ground points in parallel via conductive wires respectively. Each monitoring port is configured with a safety range of acceptable ground resistances and a presentation manner of the alarm when the measured ground resistance of a monitoring port exceeds the safe range. The monitoring device has a self-correction function to automatically offset the resistance of conductive wire from the measurement result when the conductive wire is too long. The monitoring device can further contain a network interface allowing remote operation and monitoring.

Abstract: A method and apparatus for detecting a fault in a joint connecting sections of an electrical transmission line together are disclosed. Previously known methods for detecting joint faults require a visual inspection of the joint or testing the transmission line using sophisticated, expensive equipment. This manual testing is expensive and inefficient. In the proposed method, a fault in a joint (301) connecting sections of an electrical transmission line (107) together is detected by measuring the resistance to current flowing through the joint (301) in one and the other directions along said electrical transmission line (107) and detecting a fault in the joint (301) if the measured resistance differs substantially in said one and the other directions. The method has particular utility in relation to low power transmission lines such as telephone lines.

Abstract: A voltage/current (V/I) source includes circuitry having first, second, third and fourth nodes, a first current source electrically connected to the first node, a second current source electrically connected to the second node, where the third and fourth nodes are between the first and second nodes, and an operational amplifier (op-amp) having an output, an inverting input, and a non-inverting input. The output is electrically connected to the third node, and the non-inverting input is electrically connected to a voltage source. A feedback line is between the fourth node and the inverting input.

Abstract: An apparatus for testing semiconductor devices includes a table having receptacles for trays holding semiconductor devices to be tested. An interface is positioned between the receptacles and at least one test device. The interface is customized to electrically connect the semiconductor devices to the at least one test device. The apparatus also includes a press that moves toward the table and applies force to each of the semiconductor devices, thereby securing the semiconductor devices in place for testing and securing the electrical connection to the interface.

Abstract: A probe array may be fabricated by forming probes arranged on a sacrificial substrate, forming a probe substrate above the probes, and removing the sacrificial substrate. In one embodiment, first probes may be two-dimensionally formed in row and column directions on a sacrificial substrate. Second probes may be formed between the first probes arranged in the row direction such that a distance between the first and second probes is smaller than the resolution limit in a lithography process. A probe substrate may be formed on the sacrificial substrate having the first and second probes, and the sacrificial substrate may be removed.

Abstract: A probe for electrical test comprises a probe body having a base end attached to a support base plate through a solder and a front end continuous with said base end and a surface layer showing a conductivity higher than that of the probe body and a solder wettability higher than that of the probe body and extending on the surface of the probe body from the base end to the front end. In the vicinity of the base end of the surface layer, a shield region having a smaller solder wettability than that of the surface layer is formed across the surface layer.

Abstract: A probe for measuring the hardness of concrete includes a body adapted to receive a retainer such that the combined body and retainer can be held in an aperture extending through a wall of a mould for the hardenable material, with the body extending from the inside of the wall. A sensor circuit includes detector elements supported by the body and disposed when in use in the concrete, and circuit terminals which face the exterior of the mould wall when in use, and are accessible through the retainer for connection to terminals of an external instrument. Preferably, the detector elements are conductive portions of a printed circuit board forming a resonator. The instrument can operate a switch in the probe which interconnects the terminals to indicate a good connection and measures resonator impedance at multiple frequencies.

Abstract: A blade probe card includes a plurality of blades that each includes a first end connected to a printed circuit board and a second end. A probe member is attached to the second end of each blade and extends outward to make contact with a device under test. A ground member is attached to the second end of each blade. The blade probe card also includes a common ground member that is separate from the printed circuit board and coupled to the ground member of each blade. Each blade may also include a first conductive signal trace and two or more conductive ground traces formed on a surface of each blade. The first conductive signal trace electrically connects the probe member to a contact on the printed circuit board. The two or more conductive ground traces are adjacent to the conductive signal trace and reduce crosstalk between the blades.

Abstract: Described are methods of using probes, for making electrical contact to high-density chips or similar electronic devices. Two groups of probes are covered. The first group includes probes that are moved laterally, parallel to the surface of the contact pads of the device under test, after the initial contact has been made. This is to create the desired wipe or scrub. The second group includes probes that operate on the principle of suction cups. When the probe is pushed against the device under test, the probe working tips stretch outwardly and create the desirable wipe or scrub. Described also are the probes themselves that are used for the above methods. In this divisional application, the emphasis is on the first group.

Abstract: A partitioned multi-die wafer-sort probe card includes an arcuate unit pattern. The arcuate unit pattern is repeated, either in complete or truncated form across the footprint of the multi-die wafer-sort probe card. Wafer testing is carried out by first testing at a first touchdown (TD), stepping the multi-die wafer-sort probe card footprint at least one die-site dimension, and second testing at a second TD.

Abstract: Apparatus and methods for monitoring temperature which employ certain characteristics of diodes in an effective way to monitor the temperature of a heat generating device and enable use of a signal derived from the monitored temperature to control the heat generating device or accessories if so desired.

Abstract: Improved methods, systems, and apparatuses are disclosed for testing LGA devices. One example embodiment include vertical routing of test nest assembly cooling lines in order to minimize the test nest footprint and increase available test sites on a single test card. Another example embodiment includes isolating and adjusting external loads and moments into the heatsink/cold plate, wherein these loads and moments involve controlling the centroid to restore more ideal thermal performance of the heatsink/chip interface. Still another example embodiment includes a nest architecture facilitating easy and low-cost replacement of LGA sockets. Finally, another example embodiment includes efficient condensation control of test nest assembly parts by using dry-air exhaust.

Abstract: An apparatus (100) is provided for dispersing heat from an integrated circuit (202) to a heat sink (404). The apparatus (100) is formed on a nonconductive body (102) having at least two conductive surfaces (110, 112) disposed thereon. One of the conductive surfaces (110) is reflowed to a heat generating lead of the integrated circuit (202), and the other conductive surface (112) provides a surface for contacting a heat sink (404). The apparatus (100) and integrated circuit provide a package (200) which can be tape and reeled (300) for easy mounting to a printed circuit board (402) of a communication device (400).

Abstract: A display filter and a display apparatus including the display filter, which can increase a contrast ratio, increase brightness, and have a great electromagnetic (EM) radiation-shielding effect, are provided. The display filter includes: a filter base; and an external light-shielding layer formed on a surface of the filter base, wherein the external light-shielding layer includes a base substrate including a transparent resin and light-shielding patterns spaced apart on a surface of the base substrate at predetermined intervals, and including a conductive material.

Abstract: One or more testers wirelessly communicate with one or more test stations. The wireless communication may include transmission of test commands and/or test vectors to a test station, resulting in testing of one or more electronic devices at the test station. The wireless communication may also include transmission of test results to a tester. Messages may also be wirelessly exchanged.

Abstract: A measurement apparatus is provided for measuring at least one of the switching times of the output signals output from a device under test.

Abstract: A method of inspecting a quiescent power supply current in a semiconductor integrated circuit, includes an ID information acquisition process for acquiring ID information of the semiconductor integrated circuit, a quiescent power supply current measuring process for measuring the value of the quiescent power supply current in the semiconductor integrated circuit, a measurement information storing process for storing the quiescent power supply current value and the ID information in a corresponding manner, a reference value determining process for determining a reference value for the quiescent power supply current on the basis of the stored quiescent power supply current value, and a defect determining process for comparing the stored quiescent power supply current value with the reference value for the quiescent power supply current to determine whether the semiconductor integrated circuit is defective or not.

Abstract: Nanotube-based logic circuitry is disclosed. Tri-stating elements add an enable/disable function to the circuitry. The tri-stating elements may be provided by nanotube-based switching devices. In the disabled state, the outputs present a high impedance, i.e., are tri-stated, which state allows interconnection to a common bus or other shared communication lines. In embodiments wherein the components are non-volatile, the inverter state and the control state are maintained in the absence of power. Such an inverter may be used in conjunction with and in the absence of diodes, resistors and transistors or as part of or as a replacement to CMOS, biCMOS, bipolar and other transistor level technologies.

Abstract: Time-multiplexed interconnect structures, timing optimization techniques and software tools for said structures, for programmable semiconductor ICs is disclosed. A first aspect is a programmable logic device, wherein a plurality of outputs from logic blocks is coupled to a plurality of inputs to logic blocks by a single wire segment comprising a programmable time multiplexing method. A second aspect is a software placement and route tool, wherein a plurality of routs is assigned to a single route, wherein the plurality of routs is routed in the single route by a time multiplexed method. A third aspect is a critical signal propagation path in a programmable logic device comprising global non-overlapping control signals and time multiplexed wires, wherein each control signal assigns a programmable time slot for multiple signals within one of said wires, further comprising one or more critical signals assigned to the last multiplexed time slot.

Abstract: Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.

Abstract: An input device for an electronic device is provided that includes a base, a frame pivotally connected to the base, a roller member rotatably supported by the frame, and at least one button pivotally connected at a side of the base. An electronic device is also provided that includes a first body, a second body pivotally attached to the first body, and an input device located in the first body.

Abstract: An FPGA architecture has top, middle and low levels. The top level is an array of B16×16 tiles enclosed by I/O blocks. The routing resources in the middle level are expressway routing channels including interconnect conductors. At the lowest level, there are block connect routing channels, local mesh routing channels, and direct connect interconnect conductors to connect the logic elements to further routing resources. Each B1 block includes four clusters of devices. Each of the clusters includes first and second LUT3s, a LUT2, and a DFF. Each of the LUT3s have three inputs and one output. Each of the LUT2s have two inputs and one output. Each DFF has a data input and a data output. In each of the clusters the outputs of the LUT3s are multiplexed to the input of DFF, and symmetrized with the output of the DFF to form two outputs of each of the clusters.

Abstract: In a first aspect, a three-dimensional semiconductor device, wherein: a configurable memory element coupled to a programmable logic circuit to program the logic circuit is positioned substantially above the logic circuit. In a second aspect, a three-dimensional semiconductor device, comprising: a first module layer having a circuit block; and a second module layer positioned substantially above the first module layer, comprising a configuration circuit coupled to the circuit block to program the circuit block.

Abstract: A circuit for balancing delays through true and complement phases of complementary drivers includes: a first driver; a second driver; a first delay device coupled to an input of the first driver and having an input coupled to an input signal node; a second delay device coupled to an input of the second driver and having an input coupled to the input signal node through a first inverter, wherein the first and second delay devices are clocked such that an input signal reaches the first driver simultaneously with an inverted input signal reaching the second driver.

Abstract: Methods and apparatus are provided for controlling at least one of a rise time and a fall time of a signal. A plurality of time shifted clock signals are generated; and a received data signal is sampled using a plurality of parallel data paths, where each of the data paths are controlled by a corresponding one of the plurality of time shifted clock signals. The plurality of time shifted clock signals can be generated, for example, by at least one delay element. The plurality of parallel data paths can be substantially identical and comprise, for example, at least one latch or at least one flip flop. Compensation can optionally be provided for variations in, for example, process corner, supply voltage, aging and operating temperature.

Abstract: A multi-enabled clock gating circuit reduces clock enable setup time. In one example, the multi-enabled clock gating circuit comprises an OAI logic gate and a clock enable control circuit. The OAI logic gate is configured to generate a gated clock signal by inverting an input clock signal responsive to one of a timing-sensitive clock enable signal and a timing-insensitive clock enable signal being active. The clock enable control circuit is configured to prevent the OAI logic gate from receiving the timing-insensitive clock enable signal responsive to the timing-sensitive clock enable signal being active. In one or more embodiments, a multi-enabled clock gating circuit having reduced clock enable setup time may be included in an integrated circuit for implementing clock gating during different operating modes of the integrated circuit.

Abstract: A reset detection circuit for a logic circuit and a RAM includes a first determining circuit, a second determining circuit and a reset signal generating circuit. The first determining circuit operates with a first voltage and determines whether a second voltage is equal to or higher than a reset voltage for the logic circuit. The second determining circuit operates with the first voltage and determines whether the first voltage is equal to or higher than a minimum operating voltage as a guarantee voltage for an operation of the first determining circuit. The reset signal generating circuit outputs a reset signal for resetting the logic circuit and the RAM, when the first voltage is lower than the minimum operating voltage and the second voltage is lower than the reset voltage.

Abstract: A sample and hold circuit architecture samples using two capacitors that are cyclically switched between charge and discharge modes. The sample and hold circuit includes a buffer to receive an input signal to be sampled, a first sampling capacitor, a second sampling capacitor, and an amplifier. The first sampling capacitor is connected to the output of the buffer during the positive phase of a clock and across the feedback path of the amplifier during the zero phase of the clock. The second sampling capacitor is connected to the output of the buffer during the zero phase of the clock and across the feedback path of the amplifier during the positive phase of the clock. Neither the first sampling capacitor nor the second sampling capacitor is simultaneously connected to the buffer, the amplifier, or to each other.

Abstract: A differential level shifter employs a variable current mirror to maintain a reference voltage at one output while the other output follows a differential input. Resistor networks allow postproduction trimming of load resistors and the current mirror, resulting in a precise and accurate output of the differential signal. An active cascode circuit enhances current mirror balance and high frequency operation.

Abstract: A pulse power source comprises a first circuit, a second circuit, a transformer for coupling the first circuit and the second circuit, and a switching controller. The second circuit comprises a third semiconductor switch connected in series with a secondary winding of the transformer. The third semiconductor switch is connected in such a direction that a voltage generated in the second circuit is reverse-biased during a period in which the second semiconductor switch is turned on. A gate amplifier for forming a control signal from the switching controller into a pulse and outputting the pulse as a pulse signal is connected between a gate terminal and a cathode terminal of the third semiconductor switch.

Abstract: A high voltage tolerant input buffer capable of operating across wide range of power supply, including low power supply voltages, dynamically controls the gate voltage of an NMOS pass transistor by sensing the incoming high voltage signal at the pad and dynamically controlling the gate bias voltage of NMOS pass transistor.

Abstract: An output buffer for providing a buffered current to a circuit load includes a plurality of operative stages, each one for generating a component of the buffered current and an enabling circuit for selectively enabling each operative stage. The output buffer further comprises at least one auxiliary stage and control means for measuring a control current that can be delivered by the at least one auxiliary stage and for activating the enabling means according to the measured control current.

Abstract: A system and method for power-on reset and under-voltage lockout schemes. The system includes a first transistor, which includes a first gate, a first terminal, and a second terminal, the second terminal being biased to a predetermined voltage. The system includes a second transistor, which include a second gate, a third terminal, and a fourth terminal, the third terminal being configured to receive an input voltage. The system includes a first resistor that is associated with a first resistance. The first resistor includes a fifth terminal and a sixth terminal, the fifth terminal being configured to receive the input voltage. The system includes a second resistor that is associated with a second resistance. The second resistor includes a seventh terminal and an eighth terminal, the seventh terminal being coupled to the sixth terminal. The system includes a first Zener diode that is associated with a first Zener voltage.

Abstract: A DLL circuit of a semiconductor memory apparatus includes a frequency sensing unit that generates and outputs a high frequency signal and a low frequency signal on the basis of a CAS latency signal. A clock dividing unit divides the frequency of an internal clock by a predetermined value and generates a divided clock in response with whether the high frequency signal is enabled or the low frequency signal is enabled. A phase sensing unit that switches a reference clock and a comparison clock, compares the phases thereof in accordance with whether the high frequency signal is enabled or the low frequency signal is enabled, selectively switches first and second phase control signals generated on the basis of the comparison result, and outputs the switched signals.

Abstract: A technology capable of avoiding malfunction of a delay locked loop without generating a constant phase error in a delay locked loop circuit is provided. In a delay locked loop circuit, a control circuit is disposed in the outside of a delay locked loop, and in phase comparison of the delay locked loop, the control circuit outputs a control signal to the delay locked loop so that the relation in the phase comparison between a reference signal and an output signal is shifted by a set cycle.

Abstract: A DLL circuit comprising: delay circuits which output first and second delayed clock signals obtained by delaying the reference clock signal by a delay times selected according to control signals; an interpolation circuit which interpolates a phase difference between the delayed clock signals to output an internal clock signal; an output circuit which generates a predetermined signal; a dummy output circuit which has the same transmission characteristics as the output circuit and outputs a feedback clock signal having the same phase as the predetermined signal; a phase comparison circuit which compares phases of the reference clock signal and the feedback clock signal; delay control circuits which controls the control signals in a direction where both phases are equal; wherein the delay time of the second delayed clock signal is larger than the first delayed clock signal by an amount equivalent to one cycle of the reference clock signal.

Abstract: A pulse frequency modulation oscillating circuit includes a reference voltage generator for generating a first reference voltage and a second reference voltage, a first comparison circuit for comparing a state signal with the first reference voltage, a second comparison circuit for comparing the state signal with the second reference voltage, an output circuit for outputting a pulse frequency modulation signal according to an under-voltage signal, and signals outputted from the first comparison circuit and from the second comparison circuit, a mode generation circuit for generating the state signal, and a mode decision circuit for outputting inverse signals of the signals outputted from the first comparison circuit or signals outputted from the output circuit to the mode generation circuit according to the pulse frequency modulation signal, the under-voltage signal, and the signals outputted from the first comparison circuit and from the second comparison circuit.

Abstract: Data storage circuits and components of such circuits constructed using nanotube switching elements. The storage circuits may be stand-alone devices or cells incorporated into other devices or circuits. The data storage circuits include or can be used in latches, master-slave flip-flops, digital logic circuits, memory devices and other circuits. In one aspect of the invention, a master-slave flip-flop is constructed using one or more nanotube switching element-based storage devices. The master storage element or the slave storage element or both may be constructed using nanotube switching elements, for example, using two nanotube switching element-based inverters. The storage elements may be volatile or non-volatile. An equilibration device is provided for protecting the stored data from fluctuations on the inputs. Input buffers and output buffers for data storage circuits of the invention may also be constructed using nanotube switching elements.