Abstract: A method for measuring the holding properties of a TFT array of an active matrix display panel comprising multiple pixel circuits with holding capacitors, this measuring method being characterized in that the multiple pixel circuits comprise at least a first pixel circuit and a second pixel circuit, and the method comprises a step for charging to the holding capacitor of the first pixel circuit, a step for then charging to the holding capacitor of the second pixel circuit, a step for performing an effect-eliminating procedure due to floating capacity, and a step for measuring the charge of the holding capacitor of the first and second pixel circuits wherein a predetermined holding time after charging has elapsed.

Abstract: An integrated circuit includes at least a first and second compensation circuit that compensate for process, temperature, and other variable conditions that affect circuit performance. A compensation select circuit is coupled to selectively enable each of the first and second compensation circuits at respective first and second time periods to control a voltage on the input/output terminal to substantially equal a reference voltage and thereby determine appropriate compensation setting.

Abstract: A buffer circuit is configured to generate an output signal which is a function of an input signal received by the buffer circuit, the buffer circuit being selectively operative in one of at least two modes in response to a control signal. In a first mode, the buffer circuit is configured to provide a low output impedance, characteristic of a digital buffer. In a second mode, the buffer circuit is configured to limit an output current of the buffer circuit. The control signal is indicative of a level of the output signal of the buffer circuit.

Abstract: In one embodiment, NMOS transistors have their source coupled to a common source node such that the NMOS transistors conduct a leakage current if the common source node is grounded. To reduce this leakage current, the common source node is raised in potential. Similarly, PMOS transistors have their source coupled to a common source node such that the PMOS transistors conduct a leakage current if the common source node is charged to a power supply voltage VDD. To reduce this leakage current, the common source node is lowered in potential.

Abstract: An improved digital circuit for reducing readback time in field programmable gate arrays (FPGAs) includes a shift register having a plurality of latches and a clock and a reset signal provided to the latches. An interconnect circuit is provided between each pair of latches of the shift register for providing a selective data frame from the desired latch or latches. Connecting a control signal generator to a control input of said interconnect circuit enables quick readback of selected data frames, thereby reducing the time consumed for debugging of an FPGA.

Abstract: An electronic circuit has a programmable logic cell with a plurality of programmable logic units that are capable of being configured to operate in a multi-bit operand mode and a multiplexing mode. The programmable logic units are coupled in parallel between an input circuit and an output circuit. In a multi-bit operand processing mode the input circuit is configured to supply logic input signals from different ones of the logic inputs to the programmable logic units. The programmable logic units are coupled to successive positions along a carry chain at least in the multi-bit operand mode, so as to process carry signals from the carry chain. An output circuit passes outputs from the programmable logic units in parallel in the multi-bit operand mode. The programmable logic units have look-up tables which share the same configuration bits. The programmable logic units can also have multiplexers for passing one of the received input signals when configured to operate in a multiplexing mode of operation.

Abstract: A multiple-time programming apparatus and method using one-time programming (OTP) elements are provided. The apparatus comprises a first adjusting OTP element, a second adjusting OTP element and a logic device. An adjusting data is written into the first adjusting OTP element. When a modification in an IC is desired, the value of a desired data and the prior adjusting data is performed exclusive-OR (XOR, hereinafter) together and written into the second adjusting OTP element. The logic device performs XOR on the first OTP signal outputted from the first adjusting OTP element and the second OTP signal outputted from second adjusting OTP element, and outputs the resulting OTP signal with desired value. Thus, the apparatus and the method according to an embodiment of the present invention allow modification of data using the OTP elements that prevents from using expensive multiple-time programming elements.

Abstract: Operation noise and charge error of a charge pump circuit are reduced, thereby the jitter characteristics and the spectrum characteristics of a PLL circuit are improved, and further a time period elapsed until the PLL circuit is locked is shortened. The charge pump circuit 36 receives a control signal depending on an output of a phase comparison circuit 34 from a control circuit 35, and comprises a first P-channel MOS transistor P1, a second P-channel MOS transistor P2 and a third P-channel MOS transistor P3, and a first N-channel MOS transistor N1, a second N-channel MOS transistor N2 and a third N-channel MOS transistor N3, and a first current source 61, a second current source 62, a third current source 63 and a fourth current source 64.

Abstract: An output buffer for a semiconductor memory device and other semiconductor devices includes a feedback circuit to dynamically control the output impedance of the output buffer in response to a variety of load conditions, thus reducing output ringing. The output buffer may also include circuitry to support selectively converting the device for operation at a variety of supply voltage ranges without the need for additional mask or process steps.

Abstract: Methods and apparatus are provided for trimming a phase detector in a delay-locked-loop. A latch that evaluates a phase offset between two signals is trimmed by applying two signals to the latch that are substantially phase aligned; obtaining a phase offset between the two signals measured by the latch; and adjusting a trim setting of one or more buffers associated with the two signals until the phase offset satisfies one or more predefined criteria. The two signals can be a clock signal and an inverted version of the clock signal. The two signals can be a source of phase aligned data generated from a single clock source.

Abstract: In wireless application there is made use of a quadrature oscillators that generate signals that are capable of oscillating at quadrature of each other. The quadrature oscillator is comprised of two differential modified Colpitts oscillators. A capacitor bank allows for the selection of a desired frequency from a plurality of discrete possible frequencies. The quadrature oscillator is further coupled with a phase-error detector connected at the point-of-use of the generated ‘I’ and ‘Q’ channels and through the control of current sources provides corrections means to ensure that the phase shift at the point-of-use remains at the desired ninety degrees.

Abstract: A receiver includes clocked, differential equalization circuitry to compensate for signal attenuation that varies with the frequency of the input signal received over a respective communication channel. The incoming signal is split into filtered and unfiltered signal components. Separate current-steering transistors coupled in parallel amplify the filtered and unfiltered components and sum the results. The filter or filters used to separate the signal components may be tunable, e.g. using voltage-controlled filter components. The ratio of device sizes for the current-steering transistors sets the magnitude of the boost applied to high-frequency components. The embodiments include adjustable or programmable current-steering networks to facilitate adjustments that accommodate the unique characteristics of individual communication channels.

Abstract: An input power supply voltage level detection circuit and method are presented. The circuit includes a main detector core and a two-inverter buffer block that can include a first inverter and a second inverter. The circuit receives a voltage input signal and outputs a voltage output signal that is substantially equal to either the voltage input signal or ground, depending on whether the voltage input signal has reached a threshold voltage. The threshold voltage is defined by component characteristics of the main detector core and the two-inverter buffer block. The circuit can receive a hysteresis input signal, tied to the voltage input signal or the ground, that allows the threshold voltage to have a first threshold value when the voltage input signal increases and a second threshold value when the voltage input signal decreases. A power down input signal can also be received that allows the circuit to be powered down.

Abstract: A sample-and-hold device including first and second capacitors, first and second switches, amplifier and feedback network is provided. The amplifier includes first and second input stages, output stage and switchable bias current source. The first switch and the first capacitor are coupled in series between input signal and first voltage, and a common node is coupled to a first positive input terminal of the amplifier. The first switch is on during first period and off during second period. The second switch and the second capacitor are coupled in series between the input signal and second voltage, and a common node is coupled to a second positive input terminal of the amplifier. The second switch is on during second period and off during first period. The switchable bias current source biases the second input stage during first period, and switches to bias the first input stage during second period.

Abstract: A multi-stage transistor circuit is provided in which the multiple transistor stages are coupled in parallel and switched individually in sequence by a series arrangement of buffers. Each buffer drives the gate of a corresponding stage of the multi-stage transistor circuit with a gating signal that is delayed by each buffer. Optionally, the voltage of the gating signal can be varied. Each transistor stage may comprise one or more transistors in parallel. A switched capacitor DC/DC converter incorporating the multi-stage transistor circuit is provided in which parasitic ringing at the output is substantially reduced or eliminated. Additionally, the multi-stage transistor circuit is well suited for implementing an adaptive non-overlapping gating signal generator for complementarily driving a series arrangement of multi-stage transistors.

Abstract: An input buffer includes a signal passing module for generating a first output signal in response to the input signal based on a comparison between the input signal and a first supply voltage thereof; a regulating module having a first input terminal receiving the input signal and a second input terminal receiving the first output signal for generating a second output signal within a first predetermined voltage range; and a level down module for generating a third output signal within a second predetermined voltage range for the core circuitry in response to the second output signal. The input signal passes through the signal passing module with a substantial voltage drop when a voltage level of the input signal is substantially greater than the first supply voltage, and without a substantial voltage drop when the voltage level of the same is less than or equal to the first supply voltage.

Abstract: There is provided a reduced current input buffer circuit. More specifically, in one embodiment, there is provided an input buffer circuit comprising an input buffer that is adapted to draw an operating current, means for providing a first portion of the operating current to the input buffer, and means for providing a second portion of the operating current to the input buffer if the input buffer is expecting data.

Abstract: The buffer circuit includes pull up and pull down circuits configured to selectively pull up and pull down, respectively, a voltage of an put/output pad. The pull up and pull down circuits are connected to separate power supply lines such that a current path from the input/output pad to the pull down circuit through the pull up circuit does not exist when electrostatic discharge is received at the input/output pad.

Abstract: A push-pull buffer amplifier and a source driver are provided. In the buffer amplifier, the N-type and the P-type comparators compare an input signal and an output signal. The input terminals of the first and the second inverters are coupled to the first output terminals of the N-type and the P-type comparators, respectively. The first and the fourth transistors are controlled by the second output terminal of the N-type comparator and the output terminal of the second inverter, respectively, so that the first voltage line charges/discharges an output load. The second and the third transistors are controlled by the second output terminal of the P-type comparator and the output terminal of the first inverter, respectively, so that the second voltage line charges/discharges the output load.

Abstract: A clock multiplication circuit simple in configuration, easy to adjust the characteristics thereof, and capable of shortening lockup time. The circuit delivers an output clock signal at a frequency that is a multiple of the frequency of a reference clock signal as inputted. A counter counts the number of rising edges of the output clock signal existing during a High level period of the reference clock signal, delivering a count value CN. A subtracter subtracts the count value from a reference value BN, delivering a difference value DN. An adder adds the difference value to a preceding integrated value, calculating a new integrated value. A DA converter delivers the analog control voltage corresponding to the integrated value. A VCO delivers the output clock signal at a frequency corresponding to the analog control voltage. The frequency of the output clock signal is controlled such that DN=BN?CN=0.

Abstract: A ramp generator is provided that includes an amplifier, first and second transistors, a variable resistive load having a control electrode, and a capacitor. The amplifier has an inverting input that receives a first reference voltage, and an output connected to the gate of the first transistor. The first transistor has a source connected to a second reference voltage, and a drain connected to the non-inverting input of the amplifier and also to the variable resistive load. The second transistor mirrors the current of the first transistor so as to charge the capacitor, which is periodically discharged by a discharging circuit. In one embodiment, the generator further comprises a comparator, a filter, and an integrator that control the variable resistive load so as to generate a slope having characteristics that are noticeably independent from dispersion, from manufacturing methods, and temperature.

Abstract: A charge pump and loop filter circuit of a phase locked loop includes a resistor, first and second capacitors, first and second input current sources for supplying first and second currents to the circuit, a first output current source for outputting the first current from the circuit, and a second output current source for receiving the second current from the circuit. The charge pump also contains a plurality of up pulse switches and down pulse switches for controlling current flow through the circuit such that only a fraction of the current that flows through the resistor flows into and out of the first capacitor for charging and discharging the first capacitor. The size of the first capacitor can be reduced accordingly based on the amount of current used to charge and discharge the first capacitor.

Abstract: A delay-locked loop (DLL) has a counter that is incremented or decremented by the loop in the process of achieving lock. The counter value is converted using an digital to analog converter (DAC) to an analog voltage that controls the delay through the delay line. During faster lock modes, the loop increments/decrements intermediate bits of the counter (with the bits less significant being held at a constant value, e.g., 0) to provide a coarse lock, rather than incrementing/decrementing the least significant bit of the counter. After coarse lock is achieved, a better lock is then achieved by incrementing/decrementing the counter using a smaller increment, i.e., a less significant bit is updated, until finally, the LSB is utilized to achieve fine lock. Utilizing the coarse lock first, and then one or more finer locks, allows the lock to be achieved more quickly.

Abstract: A method and apparatus for reducing the duty cycle distortion of a periodic signal in high speed devices. More specifically, there is provided a device having a switching point modulation circuit coupled to input logic and configured to modulate the periodic output signal from the input logic such that the periodic output signal is centered about a known voltage signal, such as a switching point voltage signal.

Abstract: In some examples, a hysteresis comparator includes a series resistor portion including a plurality of resistors for dividing a power supply voltage, the series resistor portion generating a first midpoint voltage and a second midpoint voltage higher than the first midpoint voltage, a first comparator configured to compare the first midpoint voltage and a reference voltage, a second comparator configured to compare the second midpoint voltage and the reference voltage, and a flip-flop having a clock terminal to which an output signal of the first comparator is applied and a reset terminal to which an output signal of the second comparator is applied. In some examples, a hysteresis comparator further includes an OR gate to which output signals of the first comparator and the second comparator are applied, and an AND gate to which output signals of the first comparator and the second comparator are applied.

Abstract: A delay control circuit capable of controlling a delay time is disclosed. The delay control circuit includes a delay detecting circuit, a first pulse generator, a counter control circuit and a counter. The delay detecting circuit delays an input signal by a first time in response to an output signal and compares the input signal and the delayed input signal to generate a first signal. The first pulse generator generates a second signal in response to the input signal. The counter control circuit generates a count-up signal and a count-down signal in response to the first signal and the second signal. The counter generates the output signal in response to the count-up signal and the count-down signal to divide the first time by 2n intervals, wherein n is a positive integer.

Abstract: A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay units of the first delay line circuit, the transfer circuits controlling the transfer of the outputs of the delay units of the first delay line circuit to associated stages of the delay units of the second delay line circuit. The delay units of respective stages of the first delay line circuit inverting input signals. Each stage delay unit of the second delay line circuit includes a logic circuit receiving an output signal of the transfer circuit associated with the delay unit in question and an output signal of a preceding stage to send an output signal to a following stage. The duty ratio is rendered variable by independently selecting the rising edge of the input signal and a propagation path of the falling edge.

Abstract: Differential signals are supplied to gates of first and second transistors. One end and a gate of a third transistor are connected to a signal output node. One end and a gate of a fourth transistor are connected to the other end of the second transistor. A fifth transistor is connected between a power source and the other end of the third transistor. A sixth transistor is connected between a power source and the other end of the fourth transistor. A seventh transistor is inserted between the power source and the signal output node. An eighth transistor is inserted between the power source and the common connection node of the second and fourth transistor, and a gate of the eighth transistor is connected to the gate of the sixth transistor.

Abstract: A mixer circuit configured to operate in a bypass or mixing mode, and which comprises a mixer core, and a mode select circuit. The mixer core includes first and second switches, each of which has an input, and first and second outputs. The mode select circuit is coupled to the mixer core and includes third and fourth switches, which are collectively configured to operate in either a first state corresponding to the bypass mode, or a second state corresponding to the mixing mode. The input of the first switch is configured to receive a signal at a first frequency, wherein the first and second switches are configured to switch between their respective first and second outputs at a second frequency, and wherein, responsive to the state of the third and fourth switches, the first output of the first switch, and the second output of the second switch are each configured to output a signal which is either (i) at the first frequency, or (ii) a mixing product of the first and second frequencies.

Abstract: A self-repairable semiconductor comprises a first device and a replacement device. A switching device selectively swaps the replacement device for the first device when the first device is non-operable. The switching device includes an analog switching circuit that selects one of a first pair of differential outputs of the first device having a first common mode voltage and a second pair of differential outputs of the replacement device having a second common mode voltage. The analog switching circuit includes first and second switches having one of a source and drain that communicate with the first pair of differential outputs. Third and fourth switches have one of a source and drain that communicate with the second pair of differential outputs. An amplifier has a first input that communicates with the other of the source and drain of the first and third switches and a second input that communicates with the other of the source and drain of the second and fourth switches.

Abstract: Through operated alternately between a charging phase and a discharging phase, a charge pump converts an input voltage source into a drive voltage for being supplied to a light emitting diode. A current setting unit determines a reference current. A current regulating unit has a current regulating terminal and a feedback detecting terminal. The current regulating terminal is coupled to the light emitting diode so as to control a current flowing through the light emitting diode to be proportional to the reference current. The feedback detecting terminal provides a feedback signal representative of a current regulation characteristic voltage. Based on a difference between the feedback signal and a reference voltage source, an error amplifier generates an error signal. A variable resistance unit is coupled between the input voltage source and the charge pump for adjusting a variable resistance in response to the error signal.

Abstract: An electrically blowable fuse circuit having a fuse which may be placed in a condition to be blown. The circuit includes a first transistor having a body, a source, a drain, and a gate. The source is connected to one end of the fuse and the drain is connected to ground. The first transistor further includes a controllable parasitic device in its body. A second transistor is connected to the parasitic device such that when the second transistor is turned on, the parasitic device turns on the first transistor, allowing the fuse to be blown when the fuse is placed in a condition to be blown.

Abstract: An integrated circuit for programming an electrical fuse includes a first programming device coupled to the electrical fuse for selectively providing the same with a first programming current, and a second programming device coupled to the electrical fuse for selectively providing the same with a second programming current. A detection module is coupled to the electrical fuse for generating an output indicating a resistance level of the electrical fuse, wherein the resistance level has three or more predetermined states, which are provided by selectively programming the electrical fuse with the first or second programming current.

Abstract: The smart charge-pump circuits basically include a high-performance charge-pump circuit as well as a smart lock-in circuit. After the smart charge-pump circuit sensors an initial condition and responds accordingly, it will begin to operate fully as a high performance charge-pump.

Abstract: A loop powered process instrument comprises a control circuit measuring a process variable and developing a control signal representing the process variable. An output circuit for connection to a two-wire process loop controls current on the loop in accordance with the control signal. A power supply circuit is connected to the output circuit and the control circuit for receiving power from the two-wire process loop and supplying power to the control circuit. The power supply comprises cascaded charge pump circuits.

Abstract: The present invention provides methods and apparatuses for a polyphase filter, comprising: a first and second cascoded differential amplifiers configured to receive a first and second differential signals, the first cascoded differential amplifier having a first resistor coupled between current legs of the first cascoded differential amplifier and the second cascoded differential amplifier having a first capacitor coupled between current legs of the second cascoded differential amplifier; and a third and fourth cascoded differential amplifiers configured to receive said first and said second differential signals, the third cascoded differential amplifier having a second resistor coupled between current legs of the third cascoded differential amplifier and the fourth cascoded differential amplifier having a second capacitor coupled between current legs of the fourth cascoded differential amplifier; wherein the first and second cascoded differential amplifiers are configured to provide a first differential outp

Abstract: A ladder filter includes multiple inductor sections, each including voltage-controlled current sources and capacitors. A second signal input terminal is provided for the filter separately from an ordinary signal input terminal and a signal, which has been input through the second terminal, is supplied to one of the voltage-controlled current sources by way of a gain calculator. By adjusting the gain obtained by the gain calculator to an appropriate value, the ladder filter can make the numerator of its transfer function freely definable.

Abstract: A DC offset calibration device for calibrating a DC offset of an output signal of a gain stage, the DC offset calibration device includes: a digital-to-analog converter (DAC) electrically connected to the gain stage for generating an offset current according to the DC offset of the output signal of the gain stage; and a current-to-current converter electrically connected to the DAC and the gain stage for reducing the signal scale of the offset current to generate a compensation signal so as to reduce the DC offset at the output of the gain stage.

Abstract: An improved PWM amplifier is disclosed that uses multiple integrators in the loop filter to provide high loop gain across the frequency band-of-interest. The frequency characteristics of the loop filter are optimized to distribute large loop gains across the entire band to provide large suppression of noise and distortions generated in the modulation and output stages.

Abstract: A circuit is described which uses a thick gate oxide device in the input stage and a thin gate oxide device in a second stage that is connected to the input stage. The input stage thick gate oxide device provides a low input gate leakage current. The thin gate oxide device in the second stage has high performance characteristics due to the use of the thin gate oxide device. The circuit thereby has high performance characteristics and low input gate leakage current. In various applications, the circuit may be, for example, an amplifier, a differential amplifier, a variable gain differential amplifier, or an operational amplifier in a sample and hold circuit. A guideline is provided where the thick gate oxide layer is about 1.5× the thickness of the thin gate oxide layer. Also, a design to control the circuit's common mode voltage using common mode voltage feedback is described.

Abstract: In a differential amplifier and an operational amplifier each for amplifying a signal, a differential signal composed of first and second signals is inputted to a couple of input terminals (1, 2). When the voltage of the first signal is, e.g., less than the voltage value of a reference voltage source (15), a comparator (13) senses it and a switch circuit (12) switches to a first current source (6) and a current from a third current source (11) flows into the first current source (6) so that a current is inhibited from flowing in the first differential couple (4). As a result, the inputted differential signal is amplified and outputted only through a second differential couple (5). In a situation in which the voltage of the first signal exceeds the voltage of the reference voltage source (15), on the other hand, the switch circuit (12) switches to a current source (7) so that the inputted differential signal is amplified and outputted only through the first differential couple (4).

Abstract: An amplifier capable of controlling the magnitudes of quiescent and output current, using externally supplied voltages. The amplifier includes: an input circuit converting a voltage difference between input signals into a current; an output circuit outputting an output current to the outside of the (class AB) amplifier (in response to a change in voltages at the first and second output nodes of the input circuit); a first control circuit generating a first bias current (when a first control voltage is applied), and a first control current; and a second control circuit generating a second bias current (whose magnitude is less than that of the first bias current) when a second control voltage is applied, and a second control current. In a first operating mode the first bias current controls the magnitude of quiescent flowing through the output circuit. The first control circuit and the output circuit form a current mirror.

Abstract: A low voltage CMOS differential amplifier is provided. More specifically, in one embodiment, there is provided a method of manufacturing a device comprising coupling a fixed biased transistor in parallel to a self-biased transistor and configuring the fixed biased transistor and the self-biased transistor to provide a current to a differential amplifier, wherein the fixed biased transistor is configured to provide current to the differential amplifier when the self-biased transistor is operating in a triode or cut-off region.

Abstract: In a push-pull power amplifier having an end stage (10) in which two power transistors (ML, MH) are connected in series, a dead time is normally used to ensure that the power transistors do not conduct simultaneously. The invention provides an end stage in which the dead time can be omitted. This is achieved by dimensioning the driver circuits (11, 12) in such a way that during switching the control voltages (Vgh, Vgl) of the power transistors cross their threshold level (VT) substantially simultaneously.

Abstract: A sliding bias circuit for dynamically controlling quiescent current flowing through an output transistor of a linear power amplifier operating in an output frequency band, the linear power amplifier comprising a circuit device for generating a bias signal producing a quiescent current flowing through the output transistor of the RF power amplifier, the sliding bias circuit comprising a detector circuit for detecting RF input to the amplifier and generating an output signal tracking the detected RF input, the output signal directly coupled to the circuit device for automatically modifying the bias signal and the quiescent current through the output transistor. In this manner, the quiescent current at the output stage is reduced and optimized for minimum dissipation and optimal linearity at all power output levels.

Abstract: A traveling wave amplifier comprises a first normally off MOS transistor having a drain, source and gate terminal. The drain terminal is connected to a node of a drain line, which is connected to a first supply voltage potential via a connecting resistor. The gate terminal is connected to a node of a gate line, onto which an input signal is coupled. The source terminal is coupled to a second supply voltage potential via a first resistor. The traveling wave amplifier also comprises at least one second normally off MOS transistor. In addition, the traveling wave amplifier further comprises a normally off bias MOS transistor. The normally off bias MOS transistor forms a current mirror with at least one of the second normally off MOS transistors. An output signal of the traveling wave amplifier is tapped off on the drain line.

Abstract: An RF power module in which operating voltage is controlled by a control signal based on amplitude information includes a temperature detecting device which is provided over a semiconductor chip formed with an amplifying transistor or a semiconductor chip formed with a power source circuit; and a detector having a hysteresis characteristic which is provided over the semiconductor chip formed with the device or a different semiconductor chip, applies a bias to the temperature detecting device to compare the state of the device at two reference levels, outputs a signal indicating abnormality when judging that the temperature of the semiconductor chip formed with the temperature detecting device is above a predetermined temperature, and outputs a signal indicating normality when judging that the temperature of the semiconductor chip is below a second predetermined temperature lower than the predetermined temperature.

Abstract: An amplifier circuit for receiving an input signal and providing an output signal, comprises a main chain of logic stages with a plurality of nodes therebetween, and at least one auxiliary chain nested between one node in the main chain and another node, which is not the next node, to form a series of feed back or feed forward nested equalisation loops; whereby the input signal is fed serially down the main chain and is also fed through the said at least one auxiliary chain and summed to provide the output signal. The invention overcomes gain-bandwidth limits of the drive stages and bandwidth reductions that occur when analogue stages operating in a linear mode are concatenated.

Abstract: A frequency compensation device for providing added compensation to an operational amplifier, such as a bipolar or MOS rail-to-rail output operational amplifier, when the output device of the operational amplifier is in saturation. The device comprises a detector circuit for detecting those conditions which can cause the output device to go into saturation. When saturation is detected, an auxiliary frequency compensation device provides added frequency. Thereby, in a normal mode of operation, the op-amp is not overcompensated. Yet, when an output device becomes saturated, the auxiliary compensation is added to improve stability and prevent the op-amp from becoming oscillatory.

Abstract: An operational amplifier circuit includes an analog driving circuitry and a digital driving circuitry. The analog driving circuitry is coupled to a load and drives the load according to an input signal. The digital driving circuitry includes a code comparator, a sourcing unit, and a sinking unit. The code comparator compares a reference code with codes corresponding to the input signal and generates a first control signal and a second control signal accordingly. The sourcing unit is coupled to the code comparator and the load, and sources a first current to the load according to the first control signal. The sinking unit is coupled to the code comparator and the load, and sinks a second current from the load according to the second control signal.