Abstract: A solid-state image sensing device that is free of kTC noise, can eliminate black smear and dark current, has a larger numerical aperture, and can eliminate the problem of insufficient area of the light-receiving portion. Photodiode PD is formed as the light-receiving portion in the formation region of first semiconductor region 15. Light is received by semiconductor layer 14 in this region, and the generated signal charge is accumulated. Semiconductor layer 12, 14, gate electrode for pixel selection 13a, first semiconductor region 15, second semiconductor region 16, third semiconductor region 17, etc., form transistor Tr1 for pixel selection. The threshold of junction transistor JT1, composed of semiconductor substrate 10, semiconductor layer 14, and second semiconductor region 16, etc., is modulated by means of the signal charge accumulated in semiconductor layer 14 in the light-receiving portion. When transistor Tr1 for pixel selection is ON, a voltage modulated according to the signal charge is output.

Abstract: A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a liner layer preferably is deposited into the trench. An anisotropic plasma process is then performed on the trench. A silicon layer may be deposited on the base of the trench during the plasma process, or the plasma can treat the liner layer. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator, and oxidizing the silicon rich layer on the base of the trench. The resulting trench has a consistent etch rate from top to bottom of the trench.

Abstract: A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a silicon nitride barrier is deposited into the trench. The silicon nitride layer has a high nitrogen content near the trench walls to protect the walls. The silicon nitride layer further from the trench walls has a low nitrogen content and a high silicon content, to allow improved adhesion. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator. The resulting trench has a well-adhered insulator which helps the insulating properties of the trench.

Abstract: Techniques for “strapping” a primary conductor with a secondary conductor in an integrated circuit (IC). The IC includes a number of circuit elements interconnected by a secondary conductor through a number of vias disposed at a number of locations for coupling the circuit elements as an alternative to a primary conductor. The primary conductor is typically formed with a low loss metal (e.g., copper or copper alloy), and the secondary conductor is typically formed with a lossy metal (e.g., aluminum or aluminum alloy) relative to the low loss metal. The secondary conductor is strapped to the primary conductor by the vias, which may be disposed only at both ends or along the entire length of the secondary conductor. The secondary conductor is formed using design guidelines such that it provides the required electrical connectivity when the primary conductor is not present but minimally interferes with the RF performance of the primary conductor.

Abstract: Cost is reduced and reliability is improved with a BGA (Ball Grid Array) type semiconductor device which has ball-shaped conductive terminals. A first wiring is formed on an insulation film which is formed on a surface of a semiconductor die. A glass substrate is bonded over the surface of the semiconductor die, and a side surface and a back surface of the semiconductor die are covered with an insulation film. A second wiring is connected to a side surface or a back surface of the first wiring and extending over the back surface of the semiconductor die. A conductive terminal such as a bump is formed on the second wiring.

Abstract: Structures are provided for multiple oxide thicknesses on a single silicon wafer. In particular, structures are provided for multiple gate oxide thicknesses on a single chip. The chip can include circuitry including but not limited to the memory and logic technologies. These structures for multiple oxide thickness on a single silicon wafer can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity. One structure includes a top layer of SiO2 on a top surface of a silicon wafer and a trench layer of SiO2 on a trench wall of the silicon wafer. The trench wall of the silicon wafer has a different order plane-orientation than the top surface. The thickness of the top layer is different from a thickness of the trench layer.

Abstract: A charge coupled device for detecting electromagnetic and particle radiation is described. The device includes a high-resistivity semiconductor substrate, buried channel regions, gate electrode circuitry, and amplifier circuitry. For good spatial resolution and high performance, especially when operated at high voltages with full or nearly full depletion of the substrate, the device can also include a guard ring positioned near channel regions, a biased channel stop, and a biased polysilicon electrode over the channel stop.

Abstract: A semiconductor device is provided that includes a leadframe, a die, and a clip. The leadframe has a flag and a power pad. The die is coupled to the flag. The clip comprises a die retaining section and a pad section. The die is coupled to the die retaining section, and the pad section extends from the die retaining section. The pad section is coupled to the power pad. Methods for forming the semiconductor device are provided as well.

Abstract: An electronic component includes at least two vertical semiconductor power devices and an electrically conductive contact clip. Each vertical semiconductor device has a first side with at least one first lead electrode and a second side opposing the first side with at least one second load electrode. The contact clip comprises a flat web portion and at least one peripheral rim portion extending from an edge region of the flat web portion. Each of the at least two vertical semiconductor power devices is attached, and electrically connected to, the lower surface of the flat web portion of the contact clip.

Abstract: A metal substrate apparatus comprises a plurality of metal substrates forming an IC card module used in manufacturing transfer mold-type non-contact IC cards. The metal substrate apparatus comprises a thin metal strip of processing material, and each metal substrate has connecting parts. Each metal substrate has a die pad for loading an IC chip. Antenna terminals to connect antenna coils are located outside the die pad and a resin-sealed region. The antenna terminals of one metal substrate and those of a longitudinally adjacent metal substrate overlap a shared region of the processing material in a width direction. The metal substrates can be separated by sealing and then making longitudinal cuts on the processing material on the outer parts of the metal substrates along two connecting lines.

Abstract: A circuit board comprises a dielectric layer, a net of first power supply lines for providing a first reference voltage plane and a net of second power supply lines for providing a second reference voltage plane. The nets of first and second power supply lines are arranged such that first power supply lines and second power supply lines are alternately arranged in the direction of a first surface of the dielectric layer.

Abstract: A semiconductor power circuit in which multiple field effect transistor dies are solder connected between opposed contact surfaces of overlying flat conductors and are clamped by means of spring clips which are arranged in symmetrically opposed relationship. A circuit board also disposed between the clamped surfaces is protected from the clamping forces by means of a soft paper layer with holes registering with similar holes in the circuit board to permit solder pads to pass there through.

Abstract: The present invention provides a modular packing integrated circuit card and its manufacturing method. The above modular packing integrated circuit card comprises a shell, a composite chip unit, and a switch card with a specific interface format. The switch card has a predetermined space for locating the composite chip unit, and enabling the predetermined pins of the composite chip unit to be connected with the predetermined lines of the switch card. The switch card further includes an interface device for a specific interface format so as to connect with the predetermined lines. Finally, the switch card is fastened in the shell. Consequently, the composite chip unit can be manufactured as different interface formats by using different switch cards, such that different interface formats are easier to be exchanged with each other.

Abstract: On an adapter mounting portion 3a having a projecting cross section which is formed on a cap 3 of a small-sized memory card 1, a recessed portion of an adapter 2 side is fitted so that both parts are formed as an integral unit in a replaceable manner. Accordingly, the small-sized memory card 1 can maintain the dimensional compatibility with respect to existing memory cards whereby the small-sized memory card 1 can be used also in equipment which is designed to cope with the existing memory cards.

Abstract: There is disclosed a wiring board comprising a core substrate 110, a build-up layer 130a formed on at least one side of main surfaces the core substrate, wherein a cavity 120 for accommodating a chip-type decoupling capacitor 121 is formed in the build-up layer 130a. The capacitor 121 includes electrode terminals on an upper surface thereof that are directly connected to a semiconductor component, and electrode terminals on a back surface of the capacitor 121 is connected to a wiring conductor layer 132a on a bottom surface of the cavity 120. This structure enables decoupling capacitor and the semiconductor component 260 to be connected with low resistance and low inductance.

Abstract: A power semiconductor device package according to one aspect of the present invention comprises: a plurality of power semiconductor chips which are arranged in a laminated structure so that the plurality of power semiconductor chips are opposing to each other at the surfaces with the same electrical structures, and which are connected in parallel to one another, and are sealed in a sealing resin as one body.

Abstract: A printed circuit board is provided with first lands, second lands, and third lands. The first lands are arranged so as to correspond to first bumps arranged along a first side of an integrated circuit device when the integrated circuit device is mounted on the printed circuit board. The first lands are used to output electrical signals individually. The second lands are less in number than the first lands, and arranged so as to correspond to second bumps arranged along a second side of the integrated circuit device opposite to the first side. The second lands have an area the same as that of the first lands, and are used to input electrical signals individually. The third lands are arranged so as to correspond to third bumps arranged in a row formed by the second bumps, have an area larger than that of the first lands, and are not used to input or output electrical signals.

Abstract: A flip chip package generally includes a substrate, a flip chip die, and a heat spreader. The flip chip die is coupled to the substrate. The heat spreader is coupled to the flip chip die. The heat spreader can include one or more walls. Generally, the one or more walls at least partially laterally surround the flip chip die and/or the substrate. The walls can completely laterally surround the flip chip die to define a cavity in the heat spreader. The flip chip package can further include an encapsulate. For example, the encapsulate can be injected between the one or more walls of the heat spreader and the flip chip die and/or other components of the flip chip package. The encapsulate and/or the one or more walls of the heat spreader can protect one or more components of the flip chip package against moisture, corrosives, heat, or radiation, to provide some examples.

Abstract: A constraint stiffener for reinforcing an integrated circuit package is provided. In one embodiment, the constraint stiffener comprises a rigid, planar base element for bonding to an integrated circuit substrate. The base element has a plurality of elongated support members, and the base element has an opening therein for surrounding an integrated circuit. The base element and support members reduce warpage due to thermal expansion mismatches between at least the integrated circuit and the substrate. In one embodiment, the elongated support members are detachable from the corners of the base element. In another embodiment, the elongated support members have means for attaching and detaching to the corners of the base element. In yet another embodiment, the elongated support members are detachable from about the midsections of the base element. In another embodiment, the elongated support members have means for attaching and detaching to the midsections of the base element.

Abstract: A microelectronic component comprising a dielectric layer having an opening and leads extending across the opening is disclosed. The leads have an offset portion. A method of making a microelectronic assembly comprises connecting each of the leads to a contact on a microelectronic element. A semiconductor chip assembly has a microelectronic component with an opening and leads extending across the opening. The leads are connected to contacts on a semiconductor chip and have at least one twisted portion.

Abstract: Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces having such interconnects are disclosed herein. One aspect of the invention is directed toward a method for manufacturing a microelectronic workpiece having a plurality of microelectronic dies. The individual dies include an integrated circuit and a terminal electrically coupled to the integrated circuit. In one embodiment, the method includes forming an opening in the workpiece in alignment with the terminal. The opening can be a through-hole extending through the workpiece or a blind hole that extends only partially through the substrate. The method continues by constructing an electrically conductive interconnect in the workpiece by depositing a solder material into at least a portion of the opening and in electrical contact with the terminal. In embodiments that include forming a blind hole, the workpiece can be thinned either before or after forming the hole.

Abstract: A bump structure of a semiconductor package and a method for fabricating the same are provided. The bump structure is used to connect a semiconductor element to a carrier of the semiconductor package. The fabrication method primarily employs an electroplating process to form the bump structure including an under bump metallurgy (UBM) layer, at least one I-shaped conductive pillar, and a solder material. This allows fine-pitch electrical connection pads to be arranged in the semiconductor package, and also provides an enhanced support structure and a sufficient height between the semiconductor element and the carrier.

Abstract: A solderable device includes a substrate and a soldering pad overlying the substrate. A solder mask overlies the substrate and portions of the soldering pad. The solder mask has an opening that exposes a portion of the soldering pad. The opening has at least two edges that symmetrically overlie portions of the soldering pad.

Abstract: Various systems and methods for implementing multi-mode semiconductor devices are discussed herein. For example, a multi-mode semiconductor device is disclosed that includes a device package with a number of package pins. In addition, the device includes a semiconductor die with at least two IO buffers. One of the IO buffers is located a distance from a particular package pin and another of the IO buffers is located a greater distance from the particular package pin. The IO buffer located closest to the package pin includes first bond pad electrically coupled to a circuit implementing a first interface type and a first floating bond pad, and the other IO buffer includes a second bond pad electrically coupled to a circuit implementing a second interface type and a second floating bond pad.

Abstract: A method for providing a low resistance non-agglomerated Ni monosilicide contact that is useful in semiconductor devices. Where the inventive method of fabricating a substantially non-agglomerated Ni alloy monosilicide comprises the steps of: forming a metal alloy layer over a portion of a Si-containing substrate, wherein said metal alloy layer comprises of Ni and one or multiple alloying additive(s), where said alloying additive is Ti, V, Ge, Cr, Zr, Nb, Mo, Hf, Ta, W, Re, Rh, Pd or Pt or mixtures thereof; annealing the metal alloy layer at a temperature to convert a portion of said metal alloy layer into a Ni alloy monosilicide layer; and removing remaining metal alloy layer not converted into Ni alloy monosilicide. The alloying additives are selected for phase stability and to retard agglomeration. The alloying additives most efficient in retarding agglomeration are most efficient in producing silicides with low sheet resistance.

Abstract: The present invention is to improve yield and reliability in a wiring step of a semiconductor device. When an Al wiring on an upper layer is connected through an connection pillar onto an Al wiring on a lower layer embedded in a groove formed on an interlayer insulation film, a growth suppression film having an opening whose width is wider than that of the Al wiring is formed on the interlayer insulation film and the Al wiring. In this condition, Al and the like are grown by a selective CVD method and the like. Accordingly, the connection pillar is formed on the Al wiring within the opening, in a self-matching manner with respect to the Al wiring.

Abstract: A semiconductor integrated circuit having a plurality of interconnect layers and at least one via connecting interconnects of two adjacent interconnect layers, wherein each interconnect layer has a plurality of first interconnect groups and second interconnect groups arranged respectively in a row and a column in a matrix. The first and the second interconnect groups are alternately arranged in each row and in each column of the matrix arranged facing each other between two adjacent interconnect layers. The first and second interconnect groups facing each other between the layers have crossing parts where they can be connected through vias.

Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric and a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide post-passivation interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick passivation interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Abstract: A semiconductor device has first wiring layers 30 and a plurality of dummy wiring layers 32 that are provided on the same level as the first wiring layers 30. The semiconductor device defines a row direction, and first virtual linear lines L1 extending in a direction traversing the row direction. The row direction and the first virtual linear lines L1 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the first virtual linear lines L1. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines L2 extending in a direction traversing the column direction. The column direction and the second virtual linear lines L2 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the second virtual linear lines L2.

Abstract: A carrier for use in a chip-scale package, including a semiconductor substrate, such as a semiconductor wafer, with a plurality of apertures formed therethrough. The present invention also includes a chip-scale package including the carrier. When the carrier is employed in such a package, a semiconductor device or a wafer including a plurality of semiconductor devices thereon is invertedly aligned with and disposed over the carrier so that bond pads of the semiconductor device or semiconductor devices substantially align with apertures through the semiconductor substrate. The chip-scale package also includes conductive material disposed in each of the apertures of the semiconductor substrate to form vias through the semiconductor substrate. Conductive traces may extend substantially laterally from selected vias. The chip-scale package may also include a contact or conductive bump disposed in communication with each via.

Abstract: A photo mask set for forming multi-layered interconnection lines and a semiconductor device fabricated using the same includes a first photo mask for forming lower interconnection lines and a second photo mask for forming upper interconnection lines. The first and second photo masks have lower opaque patterns parallel with each other and upper opaque patterns that overlap the lower opaque patterns. In this case, ends of the lower opaque patterns are located on a straight line that crosses the lower opaque patterns. As a result, when upper interconnection lines are formed using the second photo mask, poor photo resist patterns can be prevented from being formed despite the focusing of reflected light.

Abstract: A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

Abstract: A plasma conditioning method of improving the adhesion between an integrated circuit chip, having active and passive surfaces, the active surface polymer-coated and having a plurality of electrical coupling members, and an insulating underfill material. The method comprises the steps of positioning a wafer having a plurality of integrated circuits, including the coupling members, in a vacuum chamber of a plasma apparatus so that the polymer-coated surface faces the plasma source. Next, a plasma is initiated; the ion mean free path is controlled so that the ions reach the wafer surface with predetermined energy. The wafer surface is then exposed to the plasma for a length of time sufficient to roughen the polymer surface, clean the polymer surface from organic contamination and improve the surface affinity to adhesion. The adhesion ability of this surface to organic underfill material is thus enhanced.

Abstract: A chip carrier for flip chip applications, according to the present invention, provides peripheral bumps and inner bumps. The inputs and outputs related to the inner bumps are routed out on an additional wiring layer by means of vias. The proposed bond layout provides a high I/O count for a predefined chip size and a predefined carrier technology.

Abstract: A package-in-package system is provided including forming a top substrate having a first integrated circuit electrically connected thereto and mounting a second integrated circuit over the first integrated circuit. The system includes forming first electrical connectors on the second integrated circuit and encapsulating the second integrated circuit in a first encapsulant with the first electrical connectors exposed. The system includes mounting the second integrated circuit over a bottom substrate with the first electrical connectors electrically connected thereto and encapsulating the top substrate and the first encapsulant in a second encapsulant.

Abstract: A method for forming a stud bumped semiconductor die is disclosed. The method includes forming a ball at the tip of a coated wire passing through a hole in a capillary, where the coated wire has a core and an oxidation-resistant coating. The formed ball is pressed to the conductive region on the semiconductor die. The coated wire is cut, thereby leaving a conductive stud bump on the conductive region, where the conductive stud bump includes an inner conductive portion and an outer oxidation-resistant layer.

Abstract: The present invention provides a wafer structure having a plurality of bonding pad, an adhesion layer, a barrier layer, a wetting layer, a plurality of bump, a first passivation layer and a second passivation layer. The bonding pads are disposed on the active surface of the wafer and exposed by the first passivation layer. The second passivation layer is disposed on the first passivation layer and exposing the bonding pads. An adhesion layer is disposed on the bonding pad and covers a portion of the first passivation layer. The second passivation layer covers the first passivation layer and a portion of the adhesion layer. The barrier layer and the wetting layer are sequentially disposed on the adhesion layer and the bumps are disposed on the wetting layer.

Abstract: A semiconductor device comprising: a semiconductor element having a plurality of electrodes; a passivation film formed on the semiconductor element in a region avoiding at least a part of each of the electrodes; a conductive foil provided at a given spacing from the surface on which the passivation film is formed; an external electrodes formed on the conductive foil; intermediate layer formed between the passivation film and the conductive foil to support the conductive foil; and wires electrically connecting the electrodes to the conductive foil; wherein a depression tapered in a direction from the conductive foil to the passivation film if formed under a part of the conductive foil that includes the connection with the external electrodes.

Abstract: Because of the necessity of resolver for detecting a rotating position, which is very expensive, and noise suppression of the rotating position signal line on a doubly-fed machine, cost increase of the generator and reduced reliability due to possible failures are inevitable. In order to solve such problem, a generation system in the present invention is equipped with an exciter that estimates the slip frequency of the doubly-fed machine from each primary current I1 and voltage V1 and secondary current I2 and voltage V2 of the doubly-fed machine and excites the secondary of the doubly-fed machine at the estimated slip frequency.

Abstract: A system for transmitting data and/or energy between a chassis and a seat movably arranged on the chassis, the seat being able to glide in guide rails, attached to the chassis, with the aid of slides; one iron-core half of a transformer—the iron-core half bearing at least one primary winding—is disposed on the slide gliding in the guide rail, the primary winding being a cable lying in the guide rail; and the other iron-core half of the transformer having a secondary winding is arranged on the seat, the two iron-core halves of the transformer being positioned relative to each other for the data and/or energy transmission when the seat is mounted.

Abstract: The disclosed device is directed towards a combined network switch and power strip including a housing defining an interior and an exterior. A power cord is coupled to the housing. A power surge protector coupled to the power cord is disposed in the housing. An electrical power switch is coupled to the surge protector and is disposed in the housing. An array of electrical outlets is coupled to the electrical power switch and is disposed in the housing in operative communication between the interior and the exterior. A power transformer is coupled to the power surge protector in the housing interior. A network switch is coupled to the power transformer and is disposed in the housing interior. The network switch includes a network port array in operative communication between the interior and the exterior. A network connection is in operative communication with the network switch and a network outlet.

Abstract: A power supply circuit is constructed by a step-up circuit for receiving an input DC voltage to generate a plurality of output DC voltages, and a plurality of voltage regulators, each powered by two voltages selected from a combination of the output DC voltages and the ground voltage. The difference between the two voltages of each of the voltage regulators are substantially the same, to stably operate the voltage regulators.

Abstract: A semiconductor integrated circuit includes a first logic circuit to which a first power supply voltage is applied and which outputs a first signal, a first level conversion circuit to which the first power supply voltage and a second power supply voltage having an amplitude of second voltage level different from the first power supply voltage are supplied and which outputs a second signal, a second logic circuit to which the second power supply voltage is applied and which outputs a third signal, and a second level conversion circuit which 15 connected between the first and second logic circuits, to which the first and second power supply voltages are applied, and which level-converts the third signal of the second voltage level output from the second logic circuit to the first voltage level and outputs a fourth signal.

Abstract: A balancing circuit for voltages of a series connection of capacitors, particularly for intermediate circuit capacitors (3) of an inverter, there being at least two intermediate circuit capacitors connected in series over intermediate circuit voltage. The balancing circuit comprises capacitor-specific freely oscillating inverters (4), the input poles of which are connected in parallel with the capacitor corresponding to the inverter and the output poles of which are connected in parallel to provide a voltage source (Va).

Abstract: Power distribution apparatus include a rack mountable housing, an electrical power input assembly and an electrical power output assembly including a plurality of external circuits adapted for hardwired to remote equipment and a plurality of internal circuits each adapted to receive a plug of electrical equipment and to provide power thereto. The plurality of internal circuits may include differently configured receptacles adapted to receive differently configured plugs.

Abstract: The process for controlling an electronic power component for piloting an opening and/or closure of this component. The piloting process includes a plurality of steps for controlling the application of a succession of different commutation voltages on a control electrode of the electronic power component between an instant when the piloting process begins and an instant when either the opening or the closure of the electronic power component is to stop. Passage from one commutation voltage to a successive commutation voltage in this piloting process is automatically effected as soon as a corresponding condition of passage is satisfied. The process further includes a step of interrupting the piloting process and immediately triggering off a process for safeguarding the integrity of the electronic power component if the component does not react to a commutation voltage within a predetermined time for the commutation voltage.

Abstract: The invention concerns a method for deicing energized electrical transmission lines by means of an apparatus capable of producing an angular offset between its terminals. The method consists in: selecting segments (4, 6) of electrical transmission lines to de deiced, connecting the segments (4, 6) so as to form a loop, connecting the apparatus in series with the segments (4, 6) of the loop to be deiced. In the case of an apparatus with adjustable angular offset, it consists in switching on the apparatus and adjusting the angular offset to impose an increase of current flowing in at least one of the segments (4, 6) as the case may be. In the case of a apparatus with fixed angular offset, it consists in using a switch (54) or a circuit breaker (28) so as to connect the apparatus in the loop, the apparatus and the line segments being previously selected such that the angular offset imposes the required current increase to the deicing of at least one of the segments (4, 6) of the loop.

Abstract: A linear motor includes a primary having lamination stacks, which are arranged to realize a polygonal configuration of the primary, and winding coils having windings wrapped about the lamination stacks in parallel relationship to an outer periphery of the primary. Each lamination stack is made of elongate sheets extending in parallel relationship to a center axis of the motor. The lamination stacks are modules that can be combined in any number or arrangement to form a primary best suited for linear motors of desired power output.

Abstract: A linear motor has a multi-phase coil to be energized. The linear motor includes a movable element, a stator, and a control system for controlling the position of the movable element. The control system is arranged to acquire drive information related to the linear motor going to be driven, and to position the stator on the basis of the drive information prior to the driving.

Abstract: An autofocus actuator includes a cover which is provided with elastic tabs in addition to protrusions to which a stopper attached to a holder with a lens unit abuts when the holder is excessively displaced by, for example, a fall of an electronic equipment provided with the autofocus actuator. The protrusions are provided on the peripheral edge of an opening formed in the cover, and the elastic tabs are also provided on the peripheral edge of the opening. Each of the elastic tab has one end which is supported on the cover and the other end which protrudes from the peripheral edge of the opening in a cantilever manner so that the other end makes abutment with the stopper attached to the holder before the stopper makes contact with the protrusions to thereby absorb a shock applied to the holder.