Abstract: The series TFT comprises a semiconductor layer including a first body, a second body and a connecting portion serially connecting the first body to the second body. The first body has a first channel region and first source/drain regions positioned at both sides of the first channel region. The second body has a second channel region and second source/drain regions positioned at both sides of the second channel region. And the connecting portion is interposed between the first source/drain region and the second source/drain region to serially connect the first body to the second body and having a conductive type different from that of at least one of the first source/drain region and the second source/drain region. A first gate is positioned to correspond to the first channel region, and a second gate is positioned to correspond to the second channel region. An active matrix OLED can be manufactured using such series TFTs.

Abstract: The invention includes semiconductor constructions containing vertically-extending pillars, and methods for forming such constructions. The vertically-extending pillars can be incorporated into transistor devices, and can contain vertically-extending channel regions of the transistor devices. The transistor devices can be incorporated into integrated circuitry, and in some aspects are incorporated into memory constructions, such as, for example, dynamic random access memory (DRAM) constructions.

Abstract: A semiconductor device includes a transistor of a first conductivity type and a transistor of a second conductivity type. The transistor of the first conductivity type includes a first gate portion formed on a first region of a semiconductor substrate, a first sidewall formed on each side face of the first gate portion, a first protecting film formed between the first sidewall and the first gate portion, and an extension diffusion layer of the first conductivity type. The transistor of the second conductivity type includes a second gate portion formed on a second region of the semiconductor substrate, a second sidewall formed on each side face of the second gate portion, a second protecting film having an L-shaped cross-section and formed between the second sidewall and the second gate portion and between the second sidewall and the semiconductor substrate, and an extension diffusion layer of the second conductivity type.

Abstract: A flexible electronic device excellent in heat liberation characteristics and toughness and a production method for actualizing thereof in low cost and with satisfactory reproducibility are provided. A protection film is adhered onto the surface of a substrate on which surface a thin film device is formed. Successively, the substrate is soaked in an etching solution to be etched from the back surface thereof so as for the residual thickness of the substrate to fall within the range larger than 0 ?m and not larger than 200 ?m. Then, a flexible film is adhered onto the etched surface of the substrate, and thereafter the protection film is peeled to produce a flexible electronic device.

Abstract: Semiconductor structure and method of fabricating a semiconductor structure are provided that include a substrate having a first in-plane unstrained lattice constant, a first layer comprising a first semiconductor material on the substrate and having a second in-plane unstrained lattice constant that is different from the first in-plane unstrained lattice constant and a variable mismatch layer comprising a second semiconductor material disposed between the substrate and the first layer. The variable mismatch layer is configured to reduce stress in the first layer to below a level of stress resulting from growth of the first layer directly on the substrate. The variable mismatch layer may be a layer having a strained in-plane lattice constant that substantially matches the unstrained lattice constant of the first layer.

Abstract: The invention relates to a light-emitting element with porous light-emitting layers. The light-emitting element comprises: a substrate, a first conductive cladding layer, a second conductive cladding layer and at least one porous light-emitting layer. The porous light-emitting layer is formed between the first conductive cladding layer and the second conductive cladding layer, and has an upper barrier layer, a lower barrier layer and a carrier trap layer. The carrier trap layer positioned between the upper barrier layer and the lower barrier layer has a plurality of chevron structures for defining a plurality of valley shaped structures, and is an indium-containing nitride structure, the energy band gap of which is less than those of the upper barrier layer and the lower barrier layer.

Abstract: The present invention is a semiconductor apparatus for white light generation and amplification, where, under different current bias, white light can be generated steadily and evenly by folding up multi-wavelength quantum wells and by side-injecting a current. And, the white light can be excited out electronically without mingling with a fluorescent powder so that the cost for sealing is reduced. Because the light is directly excited out by electricity to prevent from energy loss during fluorescence transformation, the light generation efficiency of the present invention is far greater than that of the traditional phosphorus mingled with light-emitting diode of white light. Besides, concerning the characteristics of the white light, the spectrum of the white light can be achieved by adjusting the structure and/or the number of the quantum wells while preventing from being limited by the atomic emission lines of the fluorescent powder.

Abstract: A laser device having a semiconductor body (1), which has a plurality of active layers (5, 9) arranged vertically one above the other and serving for generating laser radiation. The active layers are subdivided in the transverse direction into a plurality of emission zones (15) and are electrically connected in series in the vertical direction. The semiconductor body (1) is formed in monolithic integrated fashion, and a cooling element (2) is provided on which the semiconductor body (1) is arranged.

Abstract: A light emitting diode chip with red, green and blue light emission regions on a single substrate. The light emission regions may be powered selectively to only emit one color light at a time. Or all three regions may be powered simultaneously so that the LED chip emits white light.

Abstract: A light-emitting diode array comprising a conductive layer formed on a substrate, pluralities of separate light-emitting portions formed on the conductive layer, a first groove formed in the conductive layer to divide the light-emitting portions to blocks, a first electrodes formed on at least part of an upper surface of each light-emitting portion, a second electrode formed directly on the conductive layer in each block, switching common wirings separately connecting the first electrodes and first bonding pads each connected to each common wiring, first bonding pads each connected to each common wiring, and second bonding pads each connected to each second electrode, the first bonding pads and the second bonding pads being arranged longitudinally in a row, and a ratio of the number of the first bonding pads to the number of the second bonding pads being 1:n (n?3).

Abstract: In a semiconductor optical device, a first conductive type semiconductor region includes first and second semiconductor portions. The first and second semiconductor portions are made of nitride mixed semiconductor crystal. This first semiconductor portion has a first region and a second region. The second semiconductor portion is provided on the first region of the first semiconductor portion. A second conductive type semiconductor region is made of nitride mixed semiconductor crystal. The second conductive type semiconductor region includes a first region and a second region. This second region of the first semiconductor portion of the first conductive type semiconductor region and the second region of the second conductive type semiconductor region constitute a pn junction. The sides of the second semiconductor portion of the first conductive type semiconductor region and the second region of the second conductive type semiconductor region constitute a pn junction.

Abstract: A semiconductor light-emitting device has a semiconductor light-emitting element for emitting light with emission wavelengths of 390 to 420 nm, wherein the wavelengths of light from the semiconductor light-emitting element are converted by a fluorescent substance having a monochromatic emission peak. The emission wavelengths of 390 to 420 nm, which have almost no adverse effect on human bodies and components of the semiconductor light-emitting device, are in a low human visibility range. Since light whose wavelengths are converted by the fluorescent substance are hardly affected by direct light from the semiconductor light-emitting element, light from the fluorescent substance has a favorable color tone. Also, the semiconductor light-emitting device allows desired luminous colors to be obtained only by changing fluorescent substance materials without changing the structure of the semiconductor light-emitting device or the semiconductor light-emitting element.

Abstract: A light-emitting diode has a sub-mount, a first conductivity type substrate deposed on the sub-mount, a reflector layer deposed between the sub-mount and the first conductivity type substrate, a first conductivity type buffer layer deposed on the first conductivity type substrate, a first conductivity type distributed Bragg reflector (DBR) layer deposed on the first conductivity type buffer layer, an illuminant epitaxial structure deposed on the first conductivity type distributed Bragg reflector layer, and a second conductivity type window layer deposed on the illuminant epitaxial structure.

Abstract: The invention relates to an optoelectronic component containing an optoelectronic chip (1) and containing a chip carrier (2) that has a central region (3) on which the chip is fixed and that comprises terminals (41, 42, 43, 44) extending outwardly from the central region of the chip carrier (2) to the outside, wherein the chip and portions of the chip carrier are enveloped by a body (5) and wherein the projection of the body and that of each of the longitudinal axes of the terminals onto the contact plane between the chip and the chip carrier are substantially point-symmetrical with respect to the central point of the chip. The invention further relates to an arrangement comprising said component. The advantage of the symmetrical configuration of the component is that the risk of thermomechanically induced failures of the component is reduced.

Abstract: A semiconductor LED device includes: a transparent substrate stacked on which are an n-type nitride semiconductor layer, a nitride semiconductor light emission layer and a p-type nitride semiconductor layer; recess regions cutting the p-type layer and light emission layer and exposing the n-type layer, defining a plurality of mesa active regions and mesa electrode pull-up regions; an n-side electrode formed on the n-type layer in the recess surrounding the mesa active regions and extending onto the mesa electrode pull-up regions; a p-side electrode formed on the p-type layer of each of the mesa active regions; and a support substrate including n-side connection members connected to and facing the n-type electrodes and p-side connection members connected to and facing the p-side electrodes.

Abstract: A liquid crystal display device with a liquid crystal display panel and a backlight, the backlight is formed by stacking a lower electrode, a light emitting layer and an upper layer on one surface of a substrate, one of the lower electrode and the upper electrode have planer pattern, another of the lower electrode and the upper electrode have plurality of large regions and plurality of small regions which connect neighboring two of the plurality of large regions, and width of the small regions is narrower than that of the large regions.

Abstract: The invention provides a heterojunction bipolar transistor comprising a substrate having a collector therein, an intrinsic base region, a first extrinsic base region, a second extrinsic base region, an emitter on the intrinsic base layer and a spacer adjacent the emitter and on the first extrinsic base region. The first extrinsic base region is adjacent the intrinsic base region and the second extrinsic base region is adjacent the first extrinsic base region on the substrate, wherein a dopant concentration of the second extrinsic base region is higher than a dopant concentration of the first extrinsic base region.

Abstract: In a nitride semiconductor device according to one embodiment of the invention, a p-type gallium nitride (GaN) layer electrically connected to a source electrode and extending and projecting to a drain electrode side with respect to a gate electrode is formed on an undoped or n-type aluminum gallium nitride (AlGaN) layer serving as a barrier layer.

Abstract: An image sensor includes a semiconductor substrate of a first conductivity type, a photodiode of a second conductivity type located in the substrate, a hole accumulated device (HAD) region of the first conductivity type located over the photodiode, a thin surface diffusion region formed on the surface of the HAD region, and a transfer gate located over the surface of the substrate adjacent the HAD region. The image sensor further includes a first channel region of the first conductivity type located in the substrate and aligned below the transfer gate, a second channel region of the second conductivity type located in the substrate between said transfer gate and the first channel region, and an floating diffusion region which is located in the substrate and which electrically contacts the second channel region.

Abstract: According to the present invention, the integrated circuit includes isolation field regions on a semiconductor substrate. Gate dielectrics are formed on a surface of a substrate. Gate electrodes are formed on the gate dielectrics. A photo resist is formed covering the active regions. Dummy patterns are selectively etched. A dummy substrate is selectively etched. The photo resist is then removed. A pair of spacers is formed along opposite sidewalls of the gate electrode and the gate dielectric. The source and drain are formed on the surface of said substrate and on opposite sides of the gate. Silicide is formed on the gate electrode, source, and drain. A layer of inter-level dielectric is then formed. A contact opening and metal wiring are then formed.

Abstract: In a solid-state image-sensing device, when image sensing is performed, in each pixel, MOS transistors T1 and T5 are turned on and a MOS transistor T6 is turned off so that a MOS transistor T2 operates in a subthreshold region. When resetting is preformed, in each pixel, the MOS transistors T1 and T5 are turned off and the MOS transistor T6 is turned on so that the gate voltage of the MOS transistor T2 is kept constant. In this state, the MOS transistor T2 is brought first into a conducting state and then, by turning a signal ?VPS to a high level, into a cut-off state. This permits a signal proportional to the threshold value of the MOS transistor T2 to be output as compensation data.

Abstract: A memory cell which is formed on a substrate of a first conductivity type. A pillar of the first conductivity type extends vertically upward from the substrate. A source region of a second conductivity type is formed in the substrate extending adjacent to and away from a base of the pillar. A drain region of the second conductivity type is formed in an upper region of the pillar. A gate dielectric and conductor are arranged along a first side of the pillar. A capacitor dielectric and body capacitor plate are arranged along an opposite, second side of the pillar. A depletion region around the source region defines a floating body region within the pillar which forms both a body of an access transistor structure and a plate of a capacitor structure. The cell also provides gain with respect to charge stored within the floating body.

Abstract: The present invention discloses a method including providing a substrate; forming a lower conductor over the substrate; forming a conducting nanostructure over the lower conductor; forming a thin dielectric over the conducting nanostructure; and forming an upper conductor over the thin dielectric. The present invention further discloses a device including a substrate; a lower conductor located over the substrate; a conducting nanostructure located over the lower conductor; a thin dielectric located over the conducting nanostructure; and an upper conductor located over the thin dielectric.

Abstract: Methods and devices are disclosed utilizing a phosphorous-doped oxide layer that is added prior to re-oxidation. This allows greater control of the re-oxidation process and greater control of the performance characteristics of semiconductor devices such as flash memory. For flash memory, greater control is gained over programming rates, erase rates, data retention and self-aligned source resistance.

Abstract: Flash memory integrated circuit devices include an integrated circuit substrate. A cell array on the integrated circuit substrate includes a plurality of cell transistors. A bit line is coupled to ones of the plurality of cell transistors and a first pass transistor is coupled to the bit line. The first pass transistor has a first diffusion structure configured to provide a breakdown voltage higher than that of a second diffusion structure. One or more second pass transistor(s) are coupled to the first pass transistor. The second pass transistor(s) have the second diffusion structure. The second diffusion structure may have a resistance smaller than a resistance of the first diffusion structure.

Abstract: A non-volatile memory is described having memory cells with a gate dielectric. The gate dielectric is a multilayer charge trapping dielectric between a control gate and a channel region of a transistor to trap positively charged holes. The multilayer charge trapping dielectric comprises two layers of dielectric having different band gaps such that holes are trapped at a barrier between the two layers.

Abstract: An embodiment of a floating-gate memory cell has a tunnel dielectric layer formed overlying a semiconductor substrate; a drain region formed in a semiconductor substrate adjacent a first side of the tunnel dielectric layer, a source region formed in a semiconductor substrate adjacent a second side of the tunnel dielectric layer, a floating-gate layer formed overlying the tunnel dielectric layer, a control-gate layer formed overlying the floating-gate layer, and an intergate dielectric layer formed interposed between the floating-gate layer and the control gate layer. The control-gate layer includes a silicide layer in contact with an underlying polysilicon layer. There is no interposing dielectric layer between the control-gate layer and an overlying bulk insulator layer, and a width of the silicide layer is substantially equal to a width of the polysilicon layer.

Abstract: The present invention discloses a semiconductor device having a pad structure for preventing a stress of a silicon nitride film. The semiconductor device includes a semiconductor substrate, a lower structure formed on the semiconductor substrate, a first insulation film formed on the lower structure, a first metal layer coupled to the lower structure through a first metal contact in the first insulation film, a second metal layer formed on the first metal layer, and a plurality of dummy gates having a concentric square structure formed at the lower portion of the pad region on the second metal layer.

Abstract: A method and an apparatus for manufacturing a memory cell having a non-volatile resistive memory element with a limited size active area. The method comprises a first step of providing a dielectric volume and forming a plug opening within the dielectric volume. A recessed plug of a conductive material is then formed within a lower portion of the opening and a dielectric spacer is formed along the sidewalls of an upper portion of the opening. The spacer is cylindrical and has a central hole. A contact plug is subsequently formed within the central hole, the contact plug electrically coupled to the recessed plug. The contact plug can include a memory element or an additional memory element can be applied over the contact plug.

Abstract: The semiconductor device includes a first semiconductor region of a first conductivity type partially extending to a top face of a semiconductor substrate; a second semiconductor region of a second conductivity type formed on the first semiconductor region; a third semiconductor region of the first conductivity type formed on the second semiconductor region; a fourth semiconductor region of the second conductivity type formed on the second semiconductor region and adjacent to the third semiconductor region; a trench penetrating through the second semiconductor region and the third semiconductor region; a gate insulating film formed on an inner wall of the trench; and a gate electrode formed on the gate insulating film within the trench.

Abstract: An integrated circuit and method of fabrication are provided in which the integrated circuit includes a field effect transistor (FET) having a channel region and source and drain regions adjacent to the channel region. A first stressed region having a first type of stress is provided to underlie the channel region, in which the first type of stress is either compressive type or tensile type. Second stressed regions having a second type of stress are provided to underlie the source and drain regions, in which the second type of stress is an opposite one of the compressive type or tensile type stress of the first stressed region.

Abstract: A semiconductor device includes a first diffusion region including germanium atoms and first impurity atoms, provided on a surface layer of a semiconductor substrate, the first impurity atoms contributing to electric conductivity, and a second diffusion region including second impurity atoms, provided shallower than the first diffusion region from a surface of the first diffusion region, the second impurity atoms not contributing to the electric conductivity.

Abstract: A field effect transistor is formed having wrap-around, vertically-aligned, dual gate electrodes. Starting with an silicon-on-insulator (SOI) structure having a buried silicon island, a vertical reference edge is defined, by creating a cavity within the SOI structure, and used during two etch-back steps that can be reliably performed. The first etch-back removes a portion of an oxide layer for a first distance over which a gate conductor material is then applied. The second etch-back removes a portion of the gate conductor material for a second distance. The difference between the first and second distances defines the gate length of the eventual device. After stripping away the oxide layers, a vertical gate electrode is revealed that surrounds the buried silicon island on all four side surfaces.

Abstract: A method for forming a semiconductor on insulator structure includes providing a glass substrate, providing a semiconductor wafer, and performing a bonding cut process on the semiconductor wafer and the glass substrate to provide a thin semiconductor layer bonded to the glass substrate. The thin semiconductor layer is formed to a thickness such that it does not yield due to temperature-induced strain at device processing temperatures. An ultra-thin silicon layer bonded to a glass substrate, selected from a group consisting of a fused silica substrate, a fused quartz substrate, and a borosilicate glass substrate, provides a silicon on insulator wafer in which circuitry for electronic devices is fabricated.

Abstract: The inventive method for forming thin channel MOSFETS comprises: providing a structure including at least a substrate having a layer of semiconducting material atop an insulating layer and a gate region formed atop the layer of semiconducting material; forming a conformal oxide film atop the structure; implanting the conformal oxide film; forming a set of spacers atop the conformal oxide film, said set of sidewall spacers are adjacent to the gate region; removing portions of the oxide film, not protected by the set of spacers to expose a region of the semiconducting material; forming raised source/drain regions on the exposed region of the semiconducting material; implanting the raised source/drain regions with a second dopant impurity to form a second dopant impurity region; and annealing a final structure to provide a thin channel MOSFET.

Abstract: A semiconductor substrate includes a first semiconductor layer that is formed on a semiconductor base substrate, a second semiconductor layer that is formed on the first semiconductor layer and that has an etching selection ratio smaller than that of the first semiconductor layer, a cavity portion that is formed below the second semiconductor layer by removing a portion of the first semiconductor layer, a thermal oxidation film that is formed on the surface of the second semiconductor layer in the cavity portion, and a buried insulating film that is buried in the cavity portion.

Abstract: A multiple gate region FET device for forming up to 6 FET devices and method for forming the same, the device including a multiple fin shaped structure comprising a semiconductor material disposed on a substrate; said multiple fin shaped structure comprising substantially parallel spaced apart sidewall portions, each of said sidewall portions comprising major inner and outer surfaces and an upper surface; wherein, each of said surfaces comprises a surface for forming an overlying field effect transistor (FET).

Abstract: A semiconductor device has a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type which is formed to extend from the surface of the semiconductor substrate toward the inside thereof, a pair of second well regions of a second conductivity which are formed to extend from the surface of the semiconductor substrate toward the inside thereof in such as manner as to sandwich the first well region therebetween, and a third well region of the second conductivity type which is formed under each of the first well region and the pair of second well regions in the semiconductor substrate. The third well region electrically connects the pair of second well regions to each other. The first well region has at least a portion thereof connected to the region of the semiconductor substrate in which the third well region is not formed.

Abstract: A method of fabricating a dual-gate on a substrate and an integrated circuit having a dual-gate structure are provided. A first high-K dielectric layer is formed in a first area defined for a first gate structure and in a second area defined for a second gate structure. A second high-K dielectric layer is formed in the first and second areas. The first high-K dielectric layer has a lower etch rate to an etchant relative to the second high-K dielectric layer. The second high-K dielectric layer is etched from the second area to said first high-K dielectric layer with the etchant, and a gate conductive layer is formed in the first and second areas over the second high-K dielectric layer and first high-K dielectric layer, respectively.

Abstract: A memory structure that reduces soft-errors for us in CMOS devices is provided. The memory cell layout utilizes transistors oriented such that the source-to-drain axis is parallel a shorted side of the memory cell. The dimensions of the memory cell are such that it has a longer side and a shorter side, wherein the longer side is preferably about twice as long as the shorter side. Such an arrangement uses a shorter well path to reduce the resistance between transistors and the well strap. The shorter well strap reduces the voltage during operation and soft errors.

Abstract: An analog switch has a first circuit and a second circuit. The first circuit has an NMOS and PMOS connected in series, and the second circuit has a PMOS and NMOS connected in series. The first and second circuits are provided in parallel between an input terminal and output terminal of the analog switch. The gate of each NMOS is connected to a terminal to which a first clock signal is supplied, and the gate of each PMOS is connected to another terminal to which a second clock signal is supplied. The second clock signal is a reversal of the first clock signal. When the analog switch is set to the OFF state and a voltage that is above the supply potential is applied to the input terminal, the NMOSs become reverse-biased diodes. Therefore, an off leak current is not produced.

Abstract: A structure of a semiconductor device and method for fabricating the same is disclosed. The semiconductor structure comprises first and second source/drain regions; a channel region disposed between the first and second source/drain regions; a buried well region in physical contact with the channel region; and a buried barrier region being disposed between the buried well region and the first source/drain region and being disposed between the buried well region and the second source/drain region, wherein the buried barrier region is adapted for preventing current leakage and dopant diffusion between the buried well region and the first source/drain region and between the buried well region and the second source/drain region.

Abstract: A contact connected to a word line is formed on a gate electrode of an access transistor of an SRAM cell. The contact passes through an element isolation insulating film to reach an SOI layer. A body region of a driver transistor and that of the access transistor are electrically connected with each other through the SOI layer located under the element isolation insulating film. Therefore, the access transistor is in a DTMOS structure having the gate electrode connected with the body region through the contact, which in turn is also electrically connected to the body region of the driver transistor. Thus, operations can be stabilized while suppressing increase of an area for forming the SRAM cell.

Abstract: An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of forming the advanced gate structure is also provided in which the silicided source and drain regions are formed prior to formation of the silicided metal gate region.

Abstract: A semiconductor device may include a substrate and a fin shaped semiconductor region on the substrate. The fin shaped semiconductor region may include a channel region and first and second junction regions on opposite sides of the channel region. A gate electrode may be provided on the channel region of the fin shaped semiconductor region, and a stress inducing layer on the fin shaped semiconductor region.

Abstract: A Fermi threshold voltage FET has Germanium implanted to form a shallow abrupt transition between the semiconductor substrate dopant type, or well dopant type, and a counter doping layer of opposite type closely adjacent the surface of the semiconductor substrate. Germanium is a charge neutral impurity in silicon that significantly reduces the diffusion motion of other impurity dopants, such as As, P, In, and B in the regions of silicon where Ge resides in significant quantities (i.e. greater than 1E19 cm sup3).

Abstract: Excellent capacitor-voltage characteristics with near-ideal hysteresis are realized in a capacitive-like structure that uses an electrode substrate-type material with a high-k dielectric layer having a thickness of a few-to-several Angstroms capacitance-based SiO2 equivalent (“TOx, Eq”). According to one particular example embodiment, a semiconductor device structure has an electrode substrate-type material having a Germanium-rich surface material. The electrode substrate-type material is processed to provide this particular electrode surface material in a form that is thermodynamically stable with a high-k dielectric material. A dielectric layer is then formed over the electrode surface material with the high-k dielectric material at a surface that faces, lies against and is thermodynamically stable with the electrode surface material.

Abstract: A physical quantity sensor includes: a semiconductor substrate; a cavity disposed in the substrate and extending in a horizontal direction of the substrate; a groove disposed on the substrate and reaching the cavity; a movable portion separated by the cavity and the groove so that the movable portion is movably supported on the substrate; and an insulation layer disposed on a bottom of the movable portion so that the insulation layer provides a roof of the cavity.

Abstract: A solid-state image sensing device is provided which saves the effort of removing adhesives from a cover glass and is capable of reading an image without being affected by adhesive residuals. In a solid-state image sensing device, defacement of a cover glass upon the transport, etc. is prevented by having a protective film adhere to the surface of the cover glass. The adhesion section between the cover glass and the protective film is provided so as to keep clear of the front face of a light-receiving section. Therefore, after the protective film is detached, even without conventional surface processing like cleaning the cover glass, the light received by the light-receiving section entering through the cover glass is not adversely affected by residual adhesives.

Abstract: An optoelectronics chip-to-chip interconnects system is provided, including packaged chips to be connected on printed-circuit-board (PCB), multiple-packaged chip, optical-electrical(O-E) conversion means, waveguide-board, and PCB. Single to multiple chips interconnects can be possible using this technique. The packaged-chip includes semiconductor-die and its package based on the ball-grid array or chip-scale-package. The O-E board includes the optoelectronics components and multiple electrical contacts. The waveguide board includes electrical conductors transferring signal from O-E board to PCB and the flex optical waveguide easily stackable onto the PCB, to guide optical signal from one chip-to-other chip. The chip-to-chip interconnects system is pin-free and compatible with the PCB. The main advantages are that standard packaged-chip and conventional PCB technology can be used for low speed electrical signal connection.