Abstract: A nitride read only memory cell comprising a silicon-germanium layer with a pair of source/drain regions. A strained silicon layer is formed overlying the silicon-germanium layer such that the pair of source/drain regions is linked by a channel that is generated in the strained silicon layer during operation of the cell. A nitride layer is formed overlying the substrate. The nitride layer has at least one charge storage region. The nitride layer may be a planar layer, a planar split gate nitride layer, or a vertical split nitride layer. A control gate is formed overlying the nitride layer. Ballistic direct injection is used to program the memory cell. A first charge storage region of the nitride layer establishes a virtual source/drain region in the channel. The virtual source/drain region has a lower threshold voltage than the remaining portion of the channel.

Abstract: In a memory cell, in a trench, a layer sequence comprising a first oxide layer, a nitride layer provided on the first oxide layer, and a second oxide layer, facing the gate electrode, and provided at the lateral trench walls, while the nitride layer is absent in a curved region of the trench bottom. In an alternative configuration, in each case at least one step is formed at the lateral walls of the trench, preferably below the source region or the drain region, respectively.

Abstract: To provide a highly reliable complementary thin film transistor circuit in which deviations in characteristics of a first-conductivity-type thin film transistor and a second-conductivity-type thin film transistor can be reduced or prevented and operated stably. A first-conductivity-type thin film transistor and a second-conductivity-type thin film transistor are formed using single crystal grains, the single crystal grains being formed substantially centered on each of a plurality of starting-point portions provided on an insulating surface of a substrate, wherein the first-conductivity-type thin film transistor and the second-conductivity-type thin film transistor are formed by equalizing their drain current directions, and are formed in the single crystal grains in which at least channel regions of the first-conductivity-type thin film transistor and the second-conductivity-type thin film transistor have the same plane orientation.

Abstract: This invention provides an electrostatic damage protection device which can protects a device to be protected enough from an electrostatic damage and prevents damages of protection transistors themselves. A N-channel type first MOS transistor and a N-channel type second MOS transistor serving as protection transistors are connected in series between an output terminal and a ground potential. On the other hand, a P-channel type third MOS transistor and a P-channel type fourth MOS transistor serving as protection transistors are connected in series between a high power supply potential and the output terminal. These first, second, third, and fourth MOS transistors are formed of low withstand voltage MOS transistors.

Abstract: The present invention provides a 6T-SRAM semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk-Si region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has an silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of the SRAM cell built from the combination of the SOI and bulk-Si region FETs.

Abstract: An integrated circuit having devices fabricated in both SOI regions and bulk regions, wherein the regions are connected by a trench filled with epitaxially deposited material. The filled trench provides a continuous semiconductor surface joining the SOI and bulk regions. The SOI and bulk regions may have the same or different crystal orientations. The present integrated circuit is made by forming a substrate with SOI and bulk regions separated by an embedded sidewall spacer (made of dielectric). The sidewall spacer is etched, forming a trench that is subsequently filled with epitaxial material. After planarizing, the substrate has SOI and bulk regions with a continuous semiconductor surface. A butted P-N junction and silicide layer can provide electrical connection between the SOI and bulk regions.

Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Abstract: A non-volatile semiconductor memory device is disclosed, which comprises a memory cell unit including at least one memory cell transistor formed on a semiconductor substrate and having a laminated structure of a charge accumulation layer and a control gate layer, and a selection gate transistor one of the source/drain diffusion layer regions of which is connected to a bit line or a source line and the other of the source/drain diffusion layer regions of which is connected to the memory cell unit. The shape of the source diffusion layer region of the selection gate transistor is asymmetical to the shape of the drain diffusion layer region thereof below the selection gate transistor.

Abstract: A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor includes a substrate with spaced-apart source and drain regions formed in the substrate and a channel region defined between the source and drain regions. A layer of gate oxide is formed over at least a part of the channel region with a gate formed over the gate oxide. The gate further includes at least one implant aperture formed therein with the channel region of the substrate further including an implanted region within the channel between the source and drain regions. Methods for forming the threshold voltage adjusted transistor are also disclosed.

Abstract: A trench transistor has a cell array, in which at least one cell array trench (2) is provided, and an edge structure framing the cell array. An edge trench (15) spaced apart from the cell array trenches (2) is provided in the edge structure.

Abstract: Electro-mechanical switches and memory cells using vertically-disposed nanofabric articles and methods of making the same are described. An electro-mechanical device, includes a structure having a major horizontal surface and a channel formed therein. A conductive trace is in the channel; and a nanotube article vertically suspended in the channel, in spaced relation to a vertical wall of the channel. The article is electro-mechanically deflectable in a horizontal direction toward the conductive trace. Under certain embodiments, the vertically suspended extent of the nanotube article is defined by a thin film process. Under certain embodiments, the vertically suspended extent of the nanotube article is about 50 nanometers or less. Under certain embodiments, the nanotube article is clamped with a conducting material disposed in porous spaces between some nanotubes of the nanotube article. Under certain embodiments, the nanotube article is formed from a porous nanofabric.

Abstract: An accelerometer (305) for measuring seismic data. The accelerometer (305) includes an integrated vent hole for use during a vacuum sealing process and a balanced metal pattern for reducing cap wafer bowing. The accelerometer (305) also includes a top cap press frame recess (405) and a bottom cap press frame recess (420) for isolating bonding pressures to specified regions of the accelerometer (305). The accelerometer (305) is vacuum-sealed and includes a balanced metal pattern (730) to prevent degradation of the performance of the accelerometer (305). A dicing process is performed on the accelerometer (305) to isolate the electrical leads of the accelerometer (305). The accelerometer (305) further includes overshock protection bumpers (720) and patterned metal electrodes to reduce stiction during the operation of the accelerometer (305).

Abstract: A MgO tunnel barrier is sandwiched between semiconductor material on one side and a ferri- and/or ferromagnetic material on the other side to form a spintronic element. The semiconductor material may include GaAs, for example. The spintronic element may be used as a spin injection device by injecting charge carriers from the magnetic material into the MgO tunnel barrier and then into the semiconductor. Similarly, the spintronic element may be used as a detector or analyzer of spin-polarized charge carriers by flowing charge carriers from the surface of the semiconducting layer through the MgO tunnel barrier and into the (ferri- or ferro-) magnetic material, which then acts as a detector. The MgO tunnel barrier is preferably formed by forming a Mg layer on an underlayer (e.g., a ferromagnetic layer), and then directing additional Mg, in the presence of oxygen, towards the underlayer.

Abstract: A front-illuminated-type photodiode array comprises (a) a first-electroconductive-type semiconductor substrate, (b) a first-electroconductive-type electrode placed at the rear-face side of the semi-conductor substrate, (c) a first-electroconductive-type absorption layer formed at the front-face side of the semiconductor substrate, (d) a plurality of second-electroconductive-type regions formed from the surface of the absorption layer to a certain distance into the absorption layer such that the regions are arranged one- or two-dimensionally, (e) a second-electroconductive-type electrode provided at part of each of the second-electroconductive-type regions, (f) an antireflective coating that covers the top surface other than the individual second-electroconductive-type electrodes and that is for preventing reflection of an incoming lightwave, and (g) at least one leakage-lightwave-absorbing layer that is provided between the first-electroconductive-type electrode and the absorption layer and that has an absorp

Abstract: Electron-hole production at a Schottky barrier has recently been observed experimentally as a result of chemical processes. This conversion of chemical energy to electronic energy may serve as a basic link between chemistry and electronics and offers the potential for generation of unique electronic signatures for chemical reactions and the creation of a new class of solid state chemical sensors. Detention of the following chemical species was established: hydrogen, deuterium, carbon monoxide, and molecular oxygen. The detector (1b) consists of a Schottky diode between an Si layer and an ultrathin metal layer with zero force electrical contacts.

Abstract: A wide bandgap semiconductor device with surge current protection and a method of making the device are described. The device comprises a low doped n-type region formed by plasma etching through the first epitaxial layer grown on a heavily doped n-type substrate and a plurality of heavily doped p-type regions formed by plasma etching through the second epitaxial layer grown on the first epitaxial layer. Ohmic contacts are formed on p-type regions and on the backside of the n-type substrate. Schottky contacts are formed on the top surface of the n-type region. At normal operating conditions, the current in the device flows through the Schottky contacts. The device, however, is capable of withstanding extremely high current densities due to conductivity modulation caused by minority carrier injection from p-type regions.

Abstract: A semiconductor device structure includes a gate structure disposed on a portion of substrate, source and drain regions disposed adjacent to the portion so as to form a channel region in the portion, and trench isolation regions located immediately adjacent to the source and drain regions. At least portions of the trench isolation regions include stress materials such that the materials generate shear stresses in the channel region.

Abstract: A capacitor structure has a plurality of stacked conductive patterns, and each conductive pattern has a closed conductive ring, a plurality of major conductive bars arranged in parallel and electrically to the closed conductive ring, and a plurality of minor conductive bars arranged alternately with the major conductive bars and not electrically connected to the closed conductive ring. The major conductive bars and the minor conductive bars of an odd layer conductive pattern are respectively corresponding to the minor conductive bars and the major conductive bars of an even layer conductive pattern.

Abstract: Memory assemblies include memory chips having chip bond pads on both sides of the memory chip shorted to each other by a single lead of a leadframe. The memory chips contain memory devices arranged to be mounted in a memory package with the major axis of the memory chip aligned substantially parallel with the major axis of its memory package. Memory chips include a first power input chip bond pad in each of at least three quadrants of the memory chip. Memory chips include a second power input chip bond pad in each of at least three quadrants of the memory chip. The chip bond pads are interposed between memory banks of the memory device and the sides of the memory chip containing the memory device. Memory chips of various embodiments contain memory devices having banks of non-volatile flash memory cells whose access commands are synchronized to a system clock.

Abstract: A flip-ship semiconductor package with a lead frame as a chip carrier is provided, wherein a plurality of leads of the lead frame are each formed with at least a dam member thereon. When a chip is mounted on the lead frame by means of solder bumps, each of the solder bumps is attached to the corresponding one of the leads at a position between the dam member and an inner end of the lead. During a reflow-soldering process for wetting the solder bumps to the leads, the dam members would help control collapse height of the solder bumps, so as to enhance resistance of the solder bumps to thermal stress generated by CTE (coefficient of thermal expansion) mismatch between the chip and the leads, thereby preventing incomplete electrical connection between the chip and the leads.

Abstract: An integrated circuit package system including an integrated circuit die and a lead frame with a trenched die pad. The integrated circuit die is mounted to the trenched die pad.

Abstract: A package for an electronic component according to one embodiment of the invention has a chip mounting area mounting a semiconductor chip in a hollow part of a metal plate and a plurality of connection electrodes to be connected to a substrate. The plurality of connection electrodes are formed in opposite sides of the rectangular metal plate and arranged asymmetrically with respect to a perpendicular bisector of the opposite sides.

Abstract: There is provided a semiconductor device including, a bed, a brazing filler metal formed on a first surface of the bed, a barrier metal film formed on a first surface of the brazing filler metal, a alloy film formed on a first surface of the barrier metal film, a semiconductor chip disposed on a first surface of the alloy film, a bonding wire electrically connecting between a terminal formed on a first surface of the semiconductor chip and a lead terminal, and a mold resin molding the bed, the brazing filler metal, the barrier metal film, the alloy film, the semiconductor chip and the bonding wire.

Abstract: A semiconductor component includes at least one semiconductor power switch, wherein a gate electrode and at least two source regions are disposed on the upper side of the semiconductor power switch. The component further includes a leadframe including a die pad and a number of leads disposed on one side of the die pad. A number of connectors extends between the source regions and the source leads such that each source lead is electrically connected to each source region.

Abstract: A semiconductor device carrier comprising; a carrier housing having a housing portion for accommodating a semiconductor device; an electrode sheet disposed in the carrier housing, having a front surface wiring conductively arranged on a front surface of an insulation substrate, a rear surface wiring conductively arranged on a rear surface of the insulation substrate, a rear surface bump contact placement wiring, and a bump contact disposed in a contact placement portion and an elastic sheet disposed in the carrier housing to be in contact with the bottom of the electrode sheet; wherein a width of the rear surface bump contact placement wiring in correspondence to a bump contact to be in contact with an extreme electrode section of the semiconductor device is smaller than a width of the front surface bump contact placement wiring on which a bump contact to be in contact with the extreme electrode section is arranged.

Abstract: A leadless image sensor package and methods for its assembly. In a first embodiment, an image sensor chip is mounted within a bottom-side cavity of a package shell in a flip-chip manner such that sensing circuitry on the image sensor chip is exposed through an aperture in the top side of the package shell. A transparent encapsulant material is deposited within the aperture to encase interconnect bonds between the package shell and the image sensor chip. A transparent lid is held in place over the aperture by the encapsulant material. The back surface of the image sensor chip is left exposed. In a second embodiment particularly suitable for high-end image sensors, an encapsulant material is not required. Instead, a backing cap is hermetically sealed to a ledge surface in the package shell to cover the bottom-side cavity. A compression member formed on the backing cap contacts the image sensor chip and maintains interconnect bond integrity.

Abstract: A semiconductor device package interposer including a receptacle extending substantially therethrough. Methods for assembling the interposer with one or more semiconductor devices are also disclosed. A film may be secured to a bottom surface of the interposer so as to at least partially cover a bottom end of the receptacle. One or more semiconductor devices are positioned within the receptacle, on the film. Each semiconductor device within the receptacle may then be electrically connected to the interposer. An encapsulant material, which is introduced into the receptacle, extends at least between portions of the outer periphery of each semiconductor device within the receptacle and a peripheral edge of the receptacle. Upon curing, setting, or hardening, the encapsulant material retains each semiconductor device within the receptacle and maintains a lateral position of each semiconductor device with respect to the interposer. Semiconductor device packages and multi-chip modules are also disclosed.

Abstract: A light transmissive cover for a device comprising: a cover member of light transmissive material; and a junction member joined to the cover member, the junction member being a member used to be joined to the body of the device and having a light interrupting film on the inner surface thereof. A device provided with a light transmissive cover, the device being provided with a cover member of light transmissive material joined to the body of device via a junction member so as to cover at least a part of the device, and having a light interrupting film on the inner surface of the junction member is also disclosed. In addition, methods for manufacturing them disclosed.

Abstract: A semiconductor device package includes a substrate, first and second chip pads spaced apart over a surface of the substrate, and an insulating layer located over the surface of the substrate. The insulating layer includes a stepped upper surface defined by at least a lower reference potential line support surface portion, and an upper signal line support surface portion, where a thickness of the insulating layer at the lower reference potential line support surface portion is less than a thickness of the insulating layer at the upper signal line support surface portion.

Abstract: A chip packaging structure without leadframe includes a bare chip having one surface provided with a plurality of contacts, and an adhesive and a fixing layer sequentially attached to the surface of the bare chip with the contacts, and a plurality of lead wires sandwiched between the adhesive and the fixing layer. Each of the lead wires has an inner end electrically connected to one of the contacts on the bare chip via an inner connecting window area provided on the adhesive layer corresponding to the contacts on the bare chip, and an outer end extended to one of multiple outer connecting window areas provided on the fixing layer to electrically connect to one of many external conducting bodies implanted in and exposed from the outer connecting window areas, such that no leadframe is needed to enable further reduced volume and decreased packaging cost of the whole chip packaging structure.

Abstract: A method of embedding a semiconductor chip in a support plate and an embedded structure thereof are proposed. A first dielectric layer having a reinforced filling material is provided, and a semiconductor chip is mounted on the first dielectric layer. A support plate having an opening and a second dielectric layer having a reinforced filling material are provided. The first dielectric layer mounted with the semiconductor chip, the support plate, and the second dielectric layer are pressed together, such that the semiconductor chip is received in the opening of the support plate, and the dielectric layers fill in a gap between the semiconductor chip and the opening of the support plate. The reinforced filling material of the dielectric layers can maintain flatness and consistency of the semiconductor chip embedded in the support plate, and fine circuits can be fabricated on the support plate by build-up and electroplating processes.

Abstract: An integrated circuit which includes a circuit board having passive elements embedded in its body.

Abstract: A semiconductor package includes: a first substrate including: a semiconductor base material having a first side and a second side; a functional element that is provided at the first side of the semiconductor base material; a first wiring; a pad that is electrically connected to the functional element via the first wiring; a through-hole interconnection that is electrically connected to the pad and is provided in a hole that is defined penetrating the semiconductor base material from the first side thereof to the second side thereof, the through-hole interconnection including a first insulating film and a first conductive material formed on the first insulating film; and a sealing material provided surrounding the functional element; a second substrate that is bonded to a first side of the first substrate via the sealing material.

Abstract: A contacting device comprises a carrier device with a first surface, a plurality of first terminal regions on the first surface, at least one elastic elevation on the first surface, and a plurality of interconnects, each running from a respective of the first terminal regions to an upper side of the elastic elevation. The plurality of first terminal regions is configured so that signals of a tester device can be fed to the plurality of first terminal regions, the interconnects have first contact regions located at the upper side of the elastic elevation configured to be contacted electrically with corresponding second contact regions of an integrated circuit, and the first contact regions comprise first particles for roughening the surface of the first contact regions.

Abstract: In a semiconductor module connecting a semiconductor element and a passive element to a printed board, each of connection portions between the semiconductor element and the printed board and between the passive element and the printed board includes a metal with a melting point of 260° C. or higher and an intermetallic compound with a melting point of 260° C. or higher. Specifically, by connecting them using Pb-free solder with a melting point of 260° C. or lower, the printed board capable of lowering in cost, lightening, and reducing back height can be applied to a module board.

Abstract: The present invention provides a semiconductor device capable of suppressing an increase in electrical resistance of a narrow interconnect, while keeping reliability of a wide interconnect from being degraded. A semiconductor device comprises a plurality of interconnect layers, and an interconnect in at least one interconnect layer among the plurality of interconnect layers contains an impurity, and the wider the interconnect in the at least one interconnect layer is, the higher concentration of the impurity the interconnect contains.

Abstract: An electronics assembly is provided including a circuit board substrate having a top surface and a bottom surface and a plurality of thermal conductive vias extending from the top surface to the bottom surface. At least one electronics package is mounted to the top surface of the substrate. A heat sink device is in thermal communication with the bottom surface of the substrate. Thermal conductive vias are in thermal communication to pass thermal energy from the at least one electronics package to the heat sink. At least some of the thermal conductive vias are formed extending from the top surface to the bottom surface of the substrate at an angle.

Abstract: An integrated electroosmotic pump may be incorporated in the same integrated circuit package with a re-combiner, and an integrated circuit chip to be cooled by fluid pumped by the electroosmotic pump.

Abstract: The present invention relates to semiconductor devices. According to the present invention a semiconductor device is described, comprising: a substrate for carrying a semiconductor chip on a first surface of said substrate; said semiconductor chip being punctually attached to said substrate on said first surface of said substrate via a single attachment point; and means for protecting said semiconductor chip on said first surface of said substrate at least protecting said semiconductor chip laterally.

Abstract: A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure, a metal-metal capacitor formed by at least a pair of metal electrodes on the same plane underneath the bonding pad structure, at least an interconnection metal layer, at least a via plug between the interconnection metal layer and the bonding pad structure, and an active circuit situated underneath the bonding pad structure on a semiconductor bottom.

Abstract: A semiconductor die includes a plurality of drivers and a plurality of bonding pads. Each driver is formed by a plurality of interconnected modules and has an associated bonding pad to which at least one of the modules of the driver is electrically connected. The modules of some of the drivers are positioned outside of the associated bonding pad toward a periphery of the die. The bonding pads may be arranged, for example, in a double- or triple-staggered pattern around the periphery of the die.

Abstract: The invention relates to a semiconductor component for mounting on a printed circuit board. The semiconductor component includes a housing that at least partially surrounds at least one flat semiconductor chip. Electrical contacts are assigned to the semiconductor chip and serve to establish an electrical connection to electrodes provided on a printed circuit board. The flat semiconductor chip has a mounting lateral surface that includes contact surfaces configured to make contact with the electrical contacts. A buffer layer is located between the housing and the chip, and surrounds the chip up to a supporting surface located on the mounting lateral surface.

Abstract: A method and apparatus for operating a combined-cycle power system is provided. The system is coupled to an electric power grid. The system includes at least one electric power generator, at least one steam turbine coupled to the generator, at least one combustion turbine coupled to the generator, and at least one steam source that is in flow communication with the steam turbine. The method includes operating the system at a first power output level with the steam turbine and the combustion turbine being synchronized to an operating frequency of the grid, so that the steam turbine, the combustion turbine, and the grid are operating at a frequency substantially similar to a standardized grid frequency value. The method also includes sensing a grid frequency deviation away from the standardized grid frequency value.

Abstract: Methods and apparatus for providing uninterruptible power are provided by aspects of the invention. One aspect is more particularly directed to an uninterruptible power supply for providing power to a load.

Abstract: A power supply circuit, wherein a power supply in a backup system is operational effectively even when a normal power supply to be used at a normal operation is turned off, including an A power supply system for supplying a first voltage to a circuit unit at a normal operation and a backup B power supply system, which starts to operate instantly when the A power supply system becomes abnormal to supply the first voltage to the circuit unit; wherein the B power supply system includes a regulator for outputting a second voltage equivalent to the first voltage, and a feedback circuit for detecting a voltage to be applied to the circuit unit and feeding back the detected voltage to the regulator; and the regulator adjusts an output voltage thereof, so that the voltage to be applied to the circuit unit becomes the first voltage when the voltage detected by the feedback circuit is lower than the first voltage.

Abstract: A tracking and control method and circuit for use in a power management unit integrated circuit (PMUIC) that enables multiple voltage regulator outputs to maintain a same voltage or a ratiometric relation to a reference voltage source. When the reference voltage source is powered down or falls below a prescribed level, the tracking power supplies are automatically switched to their internal bandgap reference voltage. Accordingly, outputs of the tracking power supplies are prevented from introducing large transient excursions that might result in malfunctions in the circuitry of the load such as latch-ups. Ratiometric tracking further provides coordinated preservation of logic interface levels, and reduces leakage current.

Abstract: A method and apparatus for powering an electronic circuit use comparators of supply voltages and voltage regulators to facilitate powering the electronic circuit utilizing more than one supply voltage. In one embodiment, power supplies of step-up power units are controlled using comparators of step-down power units and the step-up power units temporarily provide power to accidentally disabled of step-down power units.

Abstract: A bypass control section (6) maintains a bypass switch (5) in the ON state during the period when a battery voltage (Vi) is higher than the output voltage (Vo) to an external load (L). Upon falling of the output voltage (Vo) at a desired voltage (ET), a converter control section (4) starts switching control at once, and a step-up chopper (3) promptly starts boost operation. The bypass control section (6) maintains the bypass switch (5) in the ON state from the start of the boost operation of the step-up chopper (3) until the match between the battery voltage (Vi) and the output voltage (Vo).

Abstract: A radio wall switch that uses radio signals to control a load through a load circuit is disclosed. The radio wall switch is also configured group or bind electronic devices to operate collectively by responding to the same radio control signals. Preferably, the radio wall switch and electronic devices are grouped or bound to reflect their location in a floor plan architecture. The radio wall switch includes a radio control board is configured to be removable and located outside of a wall receptacle while electrically coupled to the load circuit. The radio control board includes contact switches that are selectively depressed by a switch plate for manually controlling the load. The switch plate is flexible and can be deformed to simultaneously actuate multiple contact switches to place the radio wall switch in a program mode for grouping or binding the other electronic devices.

Abstract: A system includes a thin-film battery and an activity-activated switch. In some embodiments, the system is placed on a substrate with an adhesive backing. In some embodiments, the substrate is flexible. Also formed on the substrate is an electrical circuit that includes electronics. The activity-activated switch places the thin-film battery in electrical communication with the circuit and electronics. The battery and the circuit are formed on the substrate and may be comprised of one or a plurality of deposited layers.