Abstract: A device (100) has a charging system (102) for coupling to a charger (103) operating in a vehicle, and a processor coupled to the charging system. The processor is programmed to detect (202) a charging state while a user of the device is operating the vehicle, and detect (204-208) an act by the user to exit the vehicle.

Abstract: A battery pack control module for balancing a plurality of cells or groups of cells connected in series includes a controller assembly, a disconnect circuit, a pack sensing circuit, a balancing circuit, and computer instructions for instructing the controller assembly to control the disconnect circuit and the balancing circuit. The disconnect circuit engages the controller assembly and a plurality of cells or groups of cells connected in series. The pack sensing circuit connects to the controller assembly and the plurality of cells or groups of cells connected in series. The balancing circuit connects between the plurality of cells or groups of cells connected in series, and engages the controller assembly. The plurality of cells or groups of cells connected in series is balanced when the battery pack control module operates in a charging phase, a discharging phase, a quiescent phase, or a storage phase.

Abstract: A charging circuit for a secondary battery includes a constant-voltage circuit part outputting one of a plurality of predetermined constant voltages and charges the secondary battery by applying the constant voltage thereto, a detection circuit part detecting a battery voltage of the secondary battery, and a control circuit part controlling the selection of the constant-voltage in response to the detected battery voltage.

Abstract: A drive state detection circuit is disclosed that detects a drive state of plural parts driven by alternating currents.

Abstract: A DC voltage source, a switch, and an inductor are connected together in series. The inductor is also connected together with a switch, a piezoelectric element in series. Moreover, the switches are connected in parallel with capacitors. By the control circuit, a state in which either of the switches is turned on is repeated through a state in which both of the switches are turned off. Furthermore, in a state in which both switches are turned off, after turning the switch off to enter the state concerned, when the voltage across both terminals of the switch that will be turned on is reduced by the resonance of a resonance circuit composed of the capacitors and the inductor, the switch concerned is turned on.

Abstract: In a voltage regulator including an inductor current flowing through a sense element with a first temperature coefficient, and a current sense circuit for generating a current sense signal related to the first temperature coefficient by sensing the inductor current from the sense element, a temperature compensation device and method determines a second temperature coefficient according to the first temperature coefficient and temperature variation, and produces a compensation signal with the second temperature coefficient to compensate variations in the current sense signal caused by the first temperature coefficient.

Abstract: A two stage multiple output power supply device is capable of outputting programmable DC voltages onto multiple outputs. The first stage receives an AC supply voltage and outputs a DC supply voltage. The second stage includes a DC-ID controller and multiple DC-to-DC converters, each DC-to-DC converter receiving the DC supply voltage and capable of outputting a programmable DC voltage onto a conductor of a power cord to power an electrical device. For each DC-to-DC converter, the DC-ID controller receives information in an AC signal on the conductor, the information indicating the voltage and current requirements and the polarity of an electrical device connected to the power cord for that DC-to-DC converter. In response to the information, the DC-ID controller controls the DC-to-DC converter to set a magnitude, a polarity and a current limit for the programmable DC voltage that will be output by the DC-to-DC converter.

Abstract: A voltage regulator includes first and second transistors arranged in parallel and configured to regulate current flow to an output node, and a sensing circuit configured to sense a voltage level at the output node and provide a signal proportional thereto. the regulator also includes a control circuit configured to receive the signal from the sensing circuit and provide control signals at control terminals of the first and second transistors such that voltage at the output node is maintained substantially at a selected level. The control circuit further configured to hold the second transistor in an off state while a demand for current at the output node remains below an output threshold. The second transistor is configured to control a large portion of load current above the output threshold. The regulator may also include a current bypass circuit configured to shunt leakage current of the second transistor to ground, away from the sensing circuit.

Abstract: An overshoot suppression circuit comprises a switch for coupling to an output of a voltage regulation module and a voltage detector for detecting an output voltage at the output. When the load to the voltage regulation module changes from heavy to light to result in the output voltage higher than a threshold, the voltage detector turns on the switch to release energy from the output, and thereby the output voltage is suppressed to produce overshoot to damage the load coupled to the output.

Abstract: An active current regulator circuit. In one embodiment, the active current regulator circuit includes a first input node for receiving a first reference electrical signal, a second input node for receiving a second reference electrical signal, a ground node, and an output node for outputting an output electrical signal with respect to the ground node. The active current regulator circuit further includes a PI controller having a first input node, a second input node, and an output node, and a linear regulator having a first input node electrically coupled to the output of the PI controller for receiving a voltage signal V0 generated the PI controller, a first output node and a second output node. In operation the voltage signal V0 is responsive to at least one input voltage signal applied to the first input of the second input of the amplifier, and drives the linear regulator to have a controlled electrical signal at its first output node accordingly.

Abstract: There is provided an inrush current preventing circuit. The circuit comprises an voltage-controlled type switching device that has an input terminal, an output terminal and a control terminal that limits current between the input terminal and the output terminal by an applied voltage. A first resistor is connected in parallel between the input terminal and the control terminal. A voltage control means is connected in series to the control terminal and varies a voltage applied to the control terminal.

Abstract: A constant voltage outputting apparatus includes an input terminal, an output terminal, a control unit, a plurality of output control transistors, and a switching unit. The input terminal receives an input voltage, and the output terminal outputs an output voltage. The control unit detects the output voltage and outputs a control signal equalizing the detected output voltage with a predetermined constant voltage. Each of the plurality of output control transistors receives the control signal and controls, according to the control signal, currents flowing from the input terminal to the output terminal. The switching unit switches the plurality of output control transistors to input the control signal thereto according to a predetermined setting. A constant voltage outputting method is also described.

Abstract: Droop-control circuitry of a multiphase power converter determines when multiphase switching signals are concurrently at either a high or low state and temporarily clamps the output of the power converter to either a high or low voltage level in response thereto.

Abstract: A spring modulation is proposed to regulate the output voltage of a voltage regulator. The spring modulation comprises a differential amplifier to generate a pair of voltage signal and current signal varied with the difference between a reference signal and a feedback signal related to the output voltage, and a PWM generator to generate a PWM signal in response to the pair of voltage signal and current signal to regulate the output voltage, in such a manner that, in load transient, the greater the difference between the feedback signal and reference signal is, the greater the on-time duty-cycle of the PWM signal is.

Abstract: The present invention provides a versatile system for providing a current-mode switching controller—in low voltage commercial semiconductor technologies—that is compatible with applications having very high input voltage ranges. The system provides an output transistor and a sense element coupled to the output transistor. A waveform representative of current charging across the sense element is recognized. First and second charging elements are provided, and the second charging element is adapted to charge at a rate twice as fast as the first charging element. First and second switching elements, coupled to the first and second charging elements, respectively, are adapted to activate the first and second charging elements responsive to a rising edge of the waveform.

Abstract: Systems and methods presented herein are generally directed to the location and/or identification of a circuit within a circuit. In one embodiment, a transmitter is configured for inducing a signal upon a circuit (e.g., power lines, communication lines, lighting circuits, etc.) to identify it from other circuit lines. The signal may be induced upon an individual element of the circuit through direct contact. A receiver may receive a radiated component of the signal from a distal point on the circuit to acquire the signal induced thereon and determine a strength of the signal received. Based on the received signal component, the receiver may determine location, configuration, and/or identification of the circuit from which the radiated signal is being received.

Abstract: Pursuant to certain embodiments of the present invention, methods of generating an internal clock signal in a semiconductor memory device are provided in which the frequency of an external clock signal is measured. A CAS latency value of the semiconductor memory device is automatically set based at least in part on the measured frequency of the external clock signal. The automatically set CAS latency value is then used to generate the internal clock signal from the external clock signal. In these methods, the delay of a delay lock loop of the semiconductor memory device may be based at least in part on the automatically set CAS latency value. The internal clock signal may be generated from the external clock signal using the delay lock loop. Circuits and methods for measuring the frequency of the external clock signal are also provided.

Abstract: A method is described to provide temperature compensation and reduction of drift due to aging for a current sensor based on a plurality of magnetic field sensors positioned around a current carrying conductor. The offset voltage signal generated by each magnetic field sensor is used to correct variations in the output signal due to temperature variations and aging.

Abstract: A presently-preferred embodiment of an electrical-energy meter comprises a base adapted to be mounted on a supporting surface, a current sensor assembly comprising a plurality of contact blades extending through the base and adapted to electrically contact a conductor of electrical energy, and a current transformer mechanically coupled to the base and electrically coupled to the contact blades. The electrical-energy meter further comprises a circuit board assembly comprising a main circuit board electrically coupled to the current transformer and the contact blades. The electrical-energy meter also comprises a circuit-board support member comprising a rim portion fixedly coupled to the base, and a first bracket adjoining the rim portion. The first bracket has a first and a second leg each extending away from the rim portion and the base and each being adapted to securely engage the main circuit board.

Abstract: In a motorcycle, to prevent an increase in the diameter of a hub in association with the mounting of a pulser ring and for increasing the flexibility when arranging a wheel speed sensor. An annular groove is formed on a side surface of an annular rear brake disk in an annular shape. A stepped annular pulser ring is mounted to the side surface of the rear brake disk so that a pulser section is located in the groove. Thus, a space for accommodating the pulser ring on an inner periphery of the rear brake disk is eliminated. In addition, the size of a hub-engagement hole on the rear brake disk may be reduced. Since the pulser section of the pulser ring is located in the groove of the rear brake disk, it does not take much space in the direction of an axle.

Abstract: An apparatus includes a first circuit, a second circuit, and a capacitor. The first circuit includes a sense element. The capacitor couples the first circuit to the second circuit. The first feedback path couples the second circuit to the first circuit. And the second feedback path couples the second circuit to the first circuit. A method includes generating, for an oscillator signal having an amplitude and a gain, a substantially direct current signal related to an amplitude, and controlling the gain with the substantially direct current signal.

Abstract: The invention enables to monitor a magnetic field drift of a magnetic resonance imaging apparatus on the basis of the magnetic resonance signals, which are acquired during magnetic resonance image data acquisition, such as by single shot EPI or by a gradient echo sequence. The phases of at least two magnetic resonance signals are acquired an echo time after the corresponding RF excitations. This corresponds to the central k-space line, which has frequency encoding but no phase encoding. The difference of two consecutive phase measurements, which are acquired at a certain time interval provides the shift of the resonance frequency. This enables monitoring of the shift of the resonance frequency and compensation of the magnetic field drift.

Abstract: An embodiment if the invention relates to an integrated on-chip NMR or ESR device for performing chemical analysis and medical diagnostics. Specifically, the device contains, on a single substrate, a sample holding space, a magnet for generating a static magnetic field across the sample holding space and a microcoil for generating an excitation magnetic field across sample holding space. The magnetic fields are able to create NMR or ESR within a sample in the sample holding space and collect and/or process the signals from the NMR or ESR. The substrate may comprise an array of microcoils and sample holding spaces for performing multiple NMR or ESR analysis, such as multiple DNA analysis. Other embodiments of the invention relate methods for fabricating such devices and methods for performing NMR or ESR analysis using such devices.

Abstract: A magnetic resonance imaging (MRI) magnet having a first section and a second section is disclosed. The first section has a first housing, and a first set of magnet coils arranged about a common axis that include coils proximate the common axis. The second section has a second housing, and a second set of magnet coils arranged about the common axis where the coils are radially displaced from the common axis. The second section is connected to but axially displaced a distance “d” from the first section.

Abstract: A potential sensor (101) including first and second detection electrodes (121 a, b) opposed to an object of which a potential is to be measured, and a movable shutter (125) so positioned between the detection electrodes and the potential-measured object with gaps thereto; wherein the movable shutter can assume a first state and a second state, the first detection electrode is exposed to the potential-measured object wider when the movable shutter assumes the first state than when the movable shutter assumes the second state, and the second detection electrode is exposed to the potential-measured object narrower when the movable shutter assumes the first state than when the movable shutter assumes the second state.

Abstract: Methods and apparatuses to repair defects in a circuit, such as during or subsequent to the manufacture of the circuit. Defects may be detected through, for example, optical processing of an acquired image of the circuit or by measuring the strength of a signal emitted across a pair of conductor plates. If defects are detected, conductive particles may be applied to the circuit to correct the detected defects.

Abstract: A semiconductor device test probe having a tip portion for being urged against an electrode pad of an integrated semiconductor device to establish an electrical contact against the electrode pad for testing functions of the semiconductor device. The spherical tip portion has a radius of curvature r expressed by 9t?r?35t, where r is the radius of curvature of the spherical surface and t is the thickness of the electrode pad. The tip portion may have a first curved surface substantially positioned in the direction of slippage of the probe when the probe is urged against the electrode pad and slipped relative to the electrode pad and a second curved surface opposite to the first curved surface. The first curved surface has a radius of curvature of from 7 ?m to 30 ?m and larger than that of the second curved surface.

Abstract: An apparatus for testing electrical characteristics of a semiconductor workpiece includes a probe card having probes and signal pads electrically connected to the probes, wherein the probes are in contact with a workpiece during a test process; a test head electrically connected with a performance board having signal pads; and a pogo module having pogo pins for electrically connecting the signal pads of the probe card with the signal pads of the performance board during a test process, wherein at least two the pogo pins are electrically connected in parallel to one of the signal pads of the probe card, and wherein at least two pogo pins are electrically connected in parallel to one of the signal pads of the performance board. A resistance caused by the pogo pins is lowered to test the electrical characteristics of a semiconductor workpiece more precisely and a test process is performed even when one of the pogo pins is in poor contact with a pad.

Abstract: Disclosed herein are exemplary embodiments of a contact system (referred to as a “Z-block”) for interfacing a semiconductor wafer to an electrical tester, and methods for making the same. In a preferred embodiment, the Z-block comprises three stacked pieces or layers: an upper and lower piece which are similar in structure, and a unique middle piece. The pieces each contain corresponding locking holes and probe pin holes. The locking holes are strategically arranged on each of the pieces to allow the stacked piece structure to be locked together at various points during its manufacture. After alignment of the probe pin holes in the various pieces, probe pins are injected into these holes. The probe pins are then aligned and locked into place by moving the middle piece relative to the upper and lower pieces. Such locking of the probe pins is accomplished through interaction of the middle piece with the shape of the probe pins, which prevents the probe pins from slipping out of the probe pin holes.

Abstract: The invention relates to a method and an arrangement of testing a device, such as a peripheral device, in a mobile station. The arrangement comprises a signal generator for generating a test signal for the device under test, a measurement unit integrated into the mobile station for measuring en electric quantity from a feeding line of the device under test, and an analyser for determining an electric response of the device to the test signal by using the electric quantity. According to the invention, at least a portion of the testing procedure composed of generating the test signal and determining the electric response of the device is performed using a functional unit, such as the signal generator or the analyser, integrated into the mobile station.

Abstract: A semiconductor circuit is disclosed, including a DLL circuit for supplying a desired signal-delay amount. The DLL circuit includes detecting means for detecting variations of a signal-delay amount, and delay-amount control means for generating a delay-amount control signal for controlling, depending on the variations of the signal-delay amount detected by the detecting means, the signal-delay amount of the DLL circuit. The semiconductor circuit further includes a part for monitoring circuit performance of the semiconductor circuit based on the delay-amount control signal.

Abstract: A method and system for testing a plurality of semiconductor dice on a semiconductor wafer during burn-in includes forming a plurality of semiconductor dice with each die including an integrated circuit and built-in self stress circuitry coupled thereto. The built-in self stress circuitry includes contacts coupled thereto that are configured for probing by a probe card on a burn-in tester. The built-in self stress circuitry, through an interface with the integrated circuit, generates signals for exercising the operation of the integrated circuit during burn-in testing. Each of the plurality of semiconductor dice on the semiconductor wafer are individually controllable by the burn-in tester.

Abstract: A rotatable or translatable carousel configured to facilitate electrical or electronic testing of Devices Under Test (DUTs) in combination with an insertion handler and a test head is disclosed. The carousel is configured to be placed on a test head of a tester in a first position with a first Device under Test (DUT) (such as a system-on-a-chip (SOC) integrated circuit (IC)) loaded in a first test position of the carousel. A first electrical or electronic test is performed on the first DUT at the first position, after which the carousel is advanced to a second position and a second DUT is loaded in a second test position of the carousel. While the carousel is positioned at the second position, the first test is performed on the second DUT and a second electrical or electronic test is performed on the first DUT.

Abstract: A design-for-test (DFT) circuit for an integrated circuit (IC) for enabling accurate quiescent current testing. The IC includes a voltage supply pin, a ground pin and an internal voltage regulator coupled between the voltage supply and ground pins for providing an internal output voltage. The DFT circuit includes a voltage storage device which couples to the voltage regulator to temporarily maintain the internal output voltage when the voltage regulator is disabled. The mode control circuit detects a quiescent current test mode, disables the voltage regulator and decouples the voltage regulator from the voltage storage device when the quiescent current test mode is detected. The DFT circuit may include an enable circuit which generates a freeze signal when the quiescent current test mode is detected, and at least one switch which decouples the voltage regulator from the voltage storage node. The DFT circuit is particularly useful for low pin-count ICs.

Abstract: An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The test plate is coupled to a test receiver circuit to receive and output the data signal detected at the test plate capacitively coupled to the signal terminals. Alternatively, the test plate is coupled to a test transmitter circuit to transmit data signals to signal terminals through the capacitively coupled test plate. A test unit can be coupled to the semiconductor device to evaluate the detected data signal against test criteria. Testing and evaluation is accomplished by capacitively coupling a test plate to a plurality of signal terminals. Data signals transmitted from a signal terminal and detected by the test plate or transmitted from the test plate and detected by the signal terminals are evaluated against a test criteria.

Abstract: An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The test plate is coupled to a test receiver circuit to receive and output the data signal detected at the test plate capacitively coupled to the signal terminals. Alternatively, the test plate is coupled to a test transmitter circuit to transmit data signals to signal terminals through the capacitively coupled test plate. A test unit can be coupled to the semiconductor device to evaluate the detected data signal against test criteria. Testing and evaluation is accomplished by capacitively coupling a test plate to a plurality of signal terminals. Data signals transmitted from a signal terminal and detected by the test plate or transmitted from the test plate and detected by the signal terminals are evaluated against a test criteria.

Abstract: A detection circuit for detecting the output power of a power amplifier comprises a first current minor transistor (Ti 1) having a base, which is connectable to a power transistor (T10), and a collector, a RF detection means (RF-det) for detecting the RF current flowing through the current mirror transistor (T11). Said RF detection means (RFdet) is connected to the collector of said first current mirror transistor (T11). Said detection circuit further comprises a biasing means (bias-RF-det) for biasing said RF detection means (RF-det), wherein said biasing means is connected to said collector of said first current mirror (T11) and said RF detection means (RF-det).

Abstract: A semiconductor integrated circuit device has a plurality of circuit elements, a plurality of connection elements each of which becomes a conductive state or a nonconductive state, interconnects for supplying control signals for placing the connection elements in the conductive state or the nonconductive state, and a plurality of circuit selection switching elements, wherein said circuit selection switching elements are driven in response to the circuit configuration instruction signal, control signals are output from the circuit selection switching elements. As the connection elements, preferably use is made of magnetoresistance effect elements or resistance control elements which become the conductive state or the nonconductive state in accordance with application of a magnetic field. As the circuit elements, use can be made of magnetoresistance effect elements or resistance control elements.

Abstract: An apparatus and methods for a sublithographic programmable logic array (PLA) are disclosed. The apparatus allows combination of non-restoring, programmable junctions and fixed (non-programmable) restoration logic to implement any logic function or any finite-state machine. The methods disclosed teach how to integrate fixed, restoration logic at sublithographic scales along with programmable junctions. The methods further teach how to integrate addressing from the microscale so that the nanoscale crosspoint junctions can be programmed after fabrication.

Abstract: A circuit for shifting a signal from a first voltage level to a second voltage level. In one embodiment, a voltage translator circuit has first and second transistors that are cross-coupled; a third transistor having a gate coupled with the input signal, the third transistor being coupled between the gate of the second cross-coupled transistor and the drain of the first cross-coupled transistor; and a fourth transistor having a gate coupled with an inverted version of the input signal, the fourth transistor being coupled between the gate of the first cross-coupled transistor and the drain of the second cross-coupled transistor. In another embodiment, the circuit may have, as part of its output stage, a first and second output transistors connected in series, and a third output transistor coupled between the second output transistor and ground, the third output transistor having a gate coupled with a high voltage supply.

Abstract: A semiconductor integrated circuit able to reduce a load of a layout design when arranging switches in power lines for preventing leakage current and able to reduce the influence of a voltage drop occurring in the switches on a signal delay, wherein a plurality of groups of power lines are arranged in stripe shapes, power is supplied to circuit cells by a plurality of groups of branch lines branching from the groups of power lines, power switch cells arranged in the groups of branch lines turn on or off the supply of power to the circuit cells, the power switch cells are arranged dispersed in the area of arrangement of the circuit cells, and the supply of power by the power switch cells is finely controlled for every relatively small number of circuit cells.

Abstract: Structures and methods of implementing an adder circuit in a programmable logic device (PLD). The PLD includes dual-output lookup tables (LUTs) and additional programmable logic elements. The adder circuit includes a 3:2 (3 to 2) compressor circuit that maps three input busses into two compressed busses, and a 2-input cascade adder circuit that adds the two compressed busses to yield the final sum bus. The dual-output LUTs implement both the 3:2 compressor circuit and a portion of the 2-input adder. The remaining portion of the 2-input adder is implemented using the additional programmable logic elements of the PLD. In some embodiments, the 3:2 compressor circuit is preceded by an M:3 compressor, which changes the 3-input adder into an M-input adder. In these embodiments, a second input bus is left-shifted with respect to the first input bus, and a third input busses is left-shifted with respect to the second input bus.

Abstract: Circuitry and methods are provided for control and configuration of a PLD. An embodiment of the invention comprises hard IP circuitry embedded in the PLD. The circuitry may include a gigabit MAC, a hard processor, and a DMA engine. The invention permits a variety of operations, including real-time control and remote programming, without the use of dedicated external circuitry.

Abstract: A dedicated protocol generation unit provides the ability to detect validity of data received from a configurable logic block, such as a programmable logic device (PLD). Data valid signaling is provided by the configurable logic block, such that invalid data received from the configurable logic block is replaced with programmable insertion data prior to transmission, while valid data is allowed to be transmitted without replacement. Also, data received by Input/Output (I/O) portions of the dedicated protocol generation unit are compared to programmable data patterns. After a positive comparison, matching data is either truncated and not delivered to the configurable logic block, or the matching data is delivered to the configurable logic block with appropriate data valid signaling.

Abstract: In an integrated circuit including an array of substantially similar tiles, a tile includes a logic block and at least one column of routing multiplexers driving interconnect lines that can be used to programmably interconnect the logic blocks. An output terminal of the logic block drives a vertically adjacent subset of the routing multiplexers in the column. Optionally, the tile also includes a second column of routing multiplexers. The logic block output terminal also drives a vertically adjacent subset of the routing multiplexers in the second column, and in some embodiments the two subsets are physically located in horizontal alignment with one another within the tile. The tile can also include a column of input multiplexers for the logic block. The logic block output terminal also drives a vertically adjacent subset of the input multiplexers, and the subsets of routing multiplexers and input multiplexers can be horizontally aligned within the tile.

Abstract: An integrated circuit (IC) includes a number of function blocks (FB), of which at least one is re-configurable. Each of the FBs may be a reconfigurable function or a non-reconfigurable function or recursively expanded with additional “nested” function blocks. The IC further includes a number of input pins, a number of output pins, an adder, and a number of crossbar devices. The elements, at least at the IC level, are coupled in a manner such that all input signals are provided to the FBs through a first subset of the crossbar devices, all internal signals are routed from one FB to another FB through a second subset of crossbar devices, and all output signals are routed from the FBs to the output pins through a third subset of crossbar devices. To increase routability and speed each of the crossbar device output has a single fanout. Additionally, each of the crossbar devices may provide only one input to each other crossbar device.

Abstract: There is provided a CML to CMOS converter comprising two current sources both connected between a first power supply, having a first potential, and a driving node, first and second push-pull drive stages each having a current path connected between a second power supply, having a second potential, and the driving node, and each having a control input for one half of a CML signal and an output node. Each of the two output nodes is connected to the control node of a respective one of the current sources, each current source being connected to decrease the current it supplies to the driving node if the potential of its respective output of the converter moves towards the potential of the first power supply.

Abstract: Discloses are CMOS circuit designs that combine MTCMOS and hybrid orientation technology to achieve the dual objectives of high performance and low standby leakage power. The invention utilizes novel combinations of a thick-oxide high-VTH PFET header with various gate- and body-biased schemes in HOT technology to significantly reduce the performance penalty associated with conventional PFET headers. A first embodiment of the invention provides a HOT-B high-VTH thick oxide bulk PFET header scheme. This header scheme can be expanded by application of a positive gate bias VPOS (VPOS>VDD) to the HOT-B PFET header during standby mode and a negative gate bias VNEG (VNEG<GND) in active mode. Another embodiment provides a HOT-A high-VTH thick oxide SOI PFET header scheme. A further embodiment provides a HOT-A body biased high-VTH thick oxide SOI PFET header scheme.

Abstract: An integrated circuit includes a first and a second amplifier circuit (10, 20), which are in each case driven by an input signal (Vin) having a high and a low signal level and a reference signal (Vref) having a constant signal level and, on the output side (D11, D21) generate a first control signal (S1) and a second control signal (S2). The control signals (S1, S2) are generated independently of one another and are used to regulate a first controllable resistor (31) and a second controllable resistor (32) of a third amplifier circuit (30). Depending on the resistance value of the first and second controllable resistors (31, 32) of the third amplifier circuit, an output signal (Vout) that is amplified in comparison with the input signal (Vin) can be generated at an output terminal (A). The integrated circuit can be used as an input amplifier of an integrated semiconductor memory and permits an adaptive behavior of the input amplifier with regard to fluctuations of the average absolute input signal level.

Abstract: An offset current independent sense circuit is switchable between a store state and a sense state. In the store state, the sense circuit stores an offset current to a capacitor, and the influence of the offset current is eliminated by a transistor to regenerate the offset current based on a signal provided by the capacitor in the sense state.