Abstract: A sense amplifier for use in a memory device and in a memory-resident system. The sense amplifier operates on a lower voltage consistent with the voltage range of the differential input data and the sense amplifier further operates on a higher voltage to level-shift the output signal concurrently with the sensing operation. The sense amplifier includes a pair of differential cross-coupled inverters whose inputs are coupled to receive the data from the memory. Once the input nodes of the cross-coupled inverters are charged, the cross-coupled inverters are further coupled to pull-up and pull-down circuits that span the higher voltage range for performing the level-shifting functionality. In order to recondition the sense amplifier for a subsequent sensing process, a clamp circuit shorts the level-shifted outputs together to prevent a higher voltage level from being inadvertently passed to the memory device when isolating pass gates are reactivated.

Abstract: An improved comparator circuit and associated methods are disclosed. In one embodiment, the comparator circuit comprises two voltage-to-time converter circuits, one for each input voltage to be compared, and an arbiter circuit for receiving the time-converted output of each converter. Each converter assesses the magnitude of its input voltage, and outputs a signal that is asserted at a time in inverse proportion to the magnitude of the input voltage. In one embodiment, producing the output signal at the asserted time comprises using the input voltage to gate a transistor whose discharge rate dictates the timing of the output signal. The two output signals arrive at an arbiter circuit whose function is to determine which output arrived at the arbiter first, as is indicative of the higher magnitude input voltage, and to set the output of the comparator accordingly.

Abstract: Method for controlling an analogue switch including a transistor to which a variable analogue input voltage Vin is applied on a first terminal between a source terminal and a drain terminal of the transistor while a second terminal between the drain and the source terminal is at a variable output voltage VST, including the steps of: during a first phase, applying a first voltage to the transistor gate, the first voltage equal to a sum of or a difference between Vin and a first constant potential V1, and configured to make the transistor conduct; and during a second phase, applying a second voltage to the transistor gate, the second voltage equal to a sum of or a difference between VST, Vin and a second constant potential V2, and configured to block the transistor, the difference between the first voltage and the second voltage being constant.

Abstract: As devices are often different in the characteristics from one another, semiconductor chips based on the devices have discrepancies in the performance. A semiconductor device having a semiconductor switching element and a drive controlling means (1) for generating from input signals (A) and (B) drive signals (a) and (b) to control the action of the semiconductor switching element is provided comprising a characteristic compensating means (2) for generating from a characteristic compensation input signal a compensation signal to eliminate variations in the transmission delay time of the drive controlling means (1).

Abstract: The present invention provides a semiconductor device that can adjust signal frequency bandwidths and consumption currents to be appropriately increased or reduced in source-follower amplifiers in all stages. The semiconductor device is comprised of a source-follower amplifier including a driver transistor D1, and a load transistor L1 that is connected to the driver transistor D1 and driven variably depending on a signal inputted to the driver transistor, wherein a gate of the load transistor L1 is applied with a variable bias voltage. The semiconductor device 1 is further comprised of a source-follower amplifier including a driver transistor D2, and a load circuit (load transistor L2) that is connected to said second driver transistor and driven variably depending on a signal outputted from the second driver transistor D2, wherein a gate of the load transistor L2 is applied with a variable bias voltage to vary a resistance value of the load transistor L2.

Abstract: A method and related apparatus drives a first semiconductor switching element, the load path of which is connected in series with a load path of a second semiconductor switching element in a half-bridge circuit and which is driven in the on state or in the off state according to switching signals transmitted via a transmission channel. The method includes detection of a load current through the half-bridge circuit, and repetition of the previous switching signal if the load current exceeds a predetermined maximum threshold value.

Abstract: A power source voltage monitoring circuit for monitoring self power source voltage comprises a reference voltage circuit which is supplied with a power source voltage, and generates and outputs a reference voltage in accordance with the power source voltage, a comparator which is supplied with an output voltage output from the reference voltage circuit and a voltage varying with the power source voltage, compares the voltages, and outputs a result of the comparison, and a control circuit which prevents the voltage in accordance with the power source voltage from being input to the comparator before the voltage output from the reference voltage circuit reaches a predetermined reference voltage.

Abstract: A power-on reset circuit is provided. The power-on reset circuit includes an adjusting circuit, a charging/discharging unit and an output circuit. The adjusting circuit receives and adjusts a clock signal so as to output a control signal, wherein a minimum level of the control signal is clamped to be higher than a pre-defined level. The charging/discharging unit having a capacitor apparatus receives the control signal, determines whether to charge/discharge the capacitor apparatus based on the control signal, and outputs a storage voltage of the capacitor apparatus. The output circuit receives the storage voltage and outputs the reset signal. Wherein, the adjusting circuit determines the charging/discharging duty cycle of the charging/discharging unit by adjusting the waveform and the minimum level of the control signal. The output circuit enables/disables the reset signal according to whether the storage voltage reaches the threshold voltage of the output circuit.

Abstract: An apparatus and method for generating phase related clocks, includes delaying a clock input by a cycle delay magnitude to generate a cycle delay signal and N delay taps is disclosed. Each delay tap has a delay equal to a fractional amount of the cycle delay magnitude. The method further includes delaying the clock input by an alignment magnitude to generate a first aligned phase signal and delaying each of the N delay taps by fractional amounts of the alignment magnitude to generate N phase aligned signals. A feedback loop is closed by a phase comparison between the first aligned phase signal and the cycle delay signal. The phase comparison result is used to adjust the cycle delay magnitude, which adjusts delays of the cycle delay signal and the N delay taps, and adjust the alignment magnitude, which adjusts delays of the first aligned phase signal and the N phase aligned signals.

Abstract: An improved coarse tuning process for fractional-N frequency synthesizers is provided. In general, a coarse tuning circuit controls a phase lock loop (PLL) of a frequency synthesizer such that the phase lock loop operates in an integer division mode during coarse tuning, thereby eliminating jitter due to fractional-N operation during coarse tuning. The coarse tuning circuit includes divide value generation circuitry that provides an integer divide value to an N divider of the PLL during coarse tuning and a fractional-N sequence to the N divider during fractional-N operation.

Abstract: A system for clockless synchronous data recovery is provided. The system includes an input rate demultiplexer receiving a serial data stream of bits of data transmitted at a bit rate and generating two or more parallel data streams from the serial data stream. One or more delays coupled to the input rate demultiplexer each receives one of the generated parallel serial data streams and delays bits of data and feeds them back to the input rate demultiplexer.

Abstract: A frequency synthesizer IC is disclosed that includes a variable delay circuit, a fractional-N phase locked loop circuit, and a feedback loop. The variable delay circuit is electrically coupled to the input of the fractional-N phase locked loop circuit. The feedback loop couples a first control signal from the fractional-N phase locked loop to the variable delay circuit. The variable delay circuit generates a reference signal that has a phase delay that varies in accordance with a second control signal and a first control signal. The fractional-N phase locked loop circuit is operable upon receiving the reference signal to generate the first control signal, the second control signal, and an output signal having a frequency that is a non-integer product of the reference signal.

Abstract: In an embodiment, a fine resolution of variable clock delay is implemented using a variable DC offset having fine resolution. The proportional ratio between the DC offset and the phase delay/advance of the clock is calibrated in a closed-loop manner. In another embodiment, in a calibration circuit, an adaptive positive DC offset is added to the output of a delay buffer to advance the phase of the clock output, which also has a phase delay from the delay buffer. The DC offset is adjusted in a closed-loop manner to make the phase advance, due to the DC offset, compensate for the phase delay, due to the delay buffer. Once the phase relationship of the DC offset to the clock phase advance is calibrated, the DC offset can be scaled and added to the output of another buffer of the same type to achieve a desired phase delay or advance of the clock signal.

Abstract: A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan input port, the data input ports coupled to a four-input, one-output multiplexer adapted to receive the functional data signals and to selectively output one of the functional data signals. The digital storage element also comprises a slave transparent latch coupled to the master transparent latch, the slave transparent latch comprising dedicated functional data and scan data output ports. While operating in a scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch, wherein the first and second clock signals are non-overlapping.

Abstract: A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan input port, the data input ports coupled to a four-input, one-output multiplexer that receives the functional data signals and selectively outputs one of the functional data signals. The element comprises a slave transparent latch coupled to the master transparent latch and comprising dedicated functional and scan data output ports. While operating in a scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch, wherein the first and second clock signals are non-overlapping. A first transistor is coupled to the master transparent latch and a second transistor is coupled to the slave transparent latch. When activated, the first or second transistor resets the element.

Abstract: The circuitry comprises successive stages, each comprising a combinatory logic circuit connected to the input of a first latch. Staggered clock signals are respectively associated with the first latches of the odd and even stages. Means for detecting a transient disturbance affecting the first latch of a stage and liable to propagate downstream, compare, in each stage, a value present on the output of the first latch of the stage considered at an observation time with a value present on the input of said first latch at a predetermined observation time taking account of the various propagation times.

Abstract: Disclosed herein are improved, simplified designs for a hierarchical delay line (HDL). The HDL is useful in providing precise phase control between an input clock signal and an output clock signal, and has particular utility as the variable delay in a delay-locked loop (DLL). In one embodiment, a coarse unit delay provides a delayed representation of an input clock. The original and delayed versions of the input clock are presented to a phase mixer block, which is controllable to weight its output to a phase between one of the two input clock signals. The output of the phase mixer block is then provided to a controllable variable delay line capable of adding further coarse delay into the processed signal. To assist in boundary switching, multiplexers are provided in the path between the original and delayed versions of the input clock and the phase mixer block, which provides the ability to boundary shift without having to reset the phase mixer.

Abstract: A measure control delay includes a measuring delay line and a signal generating delay line, each of which include a plurality of series-connected delay units. A digital signal is applied to an initial delay unit in the measuring delay line and it sequentially propagates through the delay units until a second digital signal is received. These outputs are applied to control inputs to the signal generating delay line to control the number of delay units through which a clock signal propagates before being output from a final delay unit. Each of the delay units in the measuring delay line includes a pair of series connected NOR gates. A NOR gate to which the digital signal is initially applied is coupled to a second NOR gate as a flip-flop so that the output of the NOR gate remains constant after the digital signal has been applied to the measuring delay line.

Abstract: A digital circuit according to the present invention includes a pulse delay circuit where a driving current of an inverter is variable, for causing timing of a clock signal to be variable; and the pulse delay circuit has a stabilizing circuit for an amount of a pulse delay by a delay synchronizing loop, and a generating circuit for a pulse delay amount setting voltage with nonlinear characteristics. The present invention makes it possible to realize a timing delay circuit with high resolution, which is not influenced by an operating environment and requires only a small area for the circuit.

Abstract: An apparatus and method for an analog fine delay line, a hybrid delay line, and a delay locked loop (DLL) is described. In the DLL, a coarse phase detector compares a reference signal and feedback signal in controlling coarse phase adjustment signals indicating whether a delay of a coarse delay line should be increased or decreased. Similarly, a fine phase detector compares the reference signal and feedback signal to generate a locking bias signal, which may increase or decrease a delay of an analog fine delay line. The analog fine delay line and coarse delay line may be connected in series creating the hybrid delay line having a total delay comprised of the coarse delay and the fine delay. Additionally, a fine bias generator may control the fine delay in response to an initiating bias signal from an analog phase generator or the locking bias signal.

Abstract: A clock control cell for production of an output clock signal from an input clock signal has a hold element and an output stage. The hold element is preceded by a signal level converter, with the signal level converter designed such that it converts an input signal to an output signal at predetermined signal levels, wherein the input clock signal is the input signal of the signal level converter.

Abstract: A gate driver for a power switch, comprising a gate drive circuit coupled to the gate of the power switch for at least one of turning on and turning off the power switch; a gate voltage control circuit in the gate drive circuit for controlling a voltage applied to the gate of the power switch during at least one of turning on and turning off the power switch; and a signal supplied to the gate voltage control circuit indicative of a voltage rate of change per unit time to be applied in at least one of turning on and turning off the power switch.

Abstract: A tracking switch includes an MOS switching transistor with a control terminal coupled to a CMOS inverter. The relative geometries of the transistors that make up the inverter are significantly imbalanced, resulting is substantially different drive strengths (i.e., substantially different on-resistances). The gate of the switching transistor exhibits parasitic capacitances between its current-handling terminals and its control terminal. When the switching transistor is on, these capacitances shunt a portion of the switched signal to a power-supply node, with the problem increasing with the frequency of the propagated signal. The geometry of the transistor used to turn on the switching transistor is selected to produce a high on-resistance, which introduces a high-impedance path from the control terminal of the switching transistor to ground when the switch is closed.

Abstract: An adaptive gate drive for an inverter includes control circuitry having a Field Programmable Gate Array (FPGA) and includes power circuitry having a plurality of FETs for operating a switching device, such as a Trench Gate Insulated Gate Bipolar Transistor (IGBT device). The control circuitry provides switching signals for operating the switching device. In addition, the control circuitry receives signals of output current of the IGBT device, temperature of the IGBT device, and DC link voltage. The FPGA has a plurality of operating points stored therein. Each operating point has corresponding parameters for a control signal that is used to control the turn-on or turn-off behavior of the IGBT device. During operation, the control circuitry compares the measured current, voltage and temperature operating points stored in the FPGA and sends the corresponding parameters to the gate drive circuit.

Abstract: A pulse multiplexed output subsystem is disclosed. In one particular exemplary embodiment, the output subsystem may comprise a plurality of pulse generators, a first pair of transistors, and a second pair of transistors, wherein each of the first pair of transistors is coupled to a respective one of a first pair of the plurality of pulse generators, and wherein each of the second pair of transistors is coupled to a respective one of a second pair of the plurality of pulse generators. The output subsystem may also comprise a first pair of resistive loads, wherein each of the first pair of resistive loads is coupled to a respective one of the first pair of transistors and a respective one of the second pair of transistors, and a first current source coupled to the first pair of transistors and the second pair of transistors.

Abstract: A voltage transfer circuit outputs an equivalent to an input voltage when enabled. Otherwise, the transfer circuit is in standby and outputs an equivalent to a standby voltage (e.g., signal ground). The voltage transfer circuit includes a switching circuit, a standby circuit, and an input-transfer circuit. The output of the transfer circuit is fed back to both the switching circuit and the input-transfer circuit. When the transfer circuit is in standby, the feedback of the output voltage provides for voltage-balancing in the input-transfer circuit, thereby reducing or eliminating leakage current in the input-transfer circuit. Similarly, when the transfer circuit is in active mode, the feedback of the output voltage provides for voltage-balancing in the standby circuit, thereby reducing or eliminating leakage current in the standby circuit.

Abstract: A switching circuit uses multiple common-drain JFETs to serve as the low-side switches of the switching circuit, and each of the low-side JFET is coupled between a high-side switch and a power node. Since a JFET can endure high voltage at both drain side and source side, and has good heat dissipation capability at drain side, the drain of the low-side JFET is coupled to the power node to enhance the heat dissipation capability and accordingly, all the low-side JFETs are allowed to be packaged in a same package to reduce the PCB layout area.

Abstract: A well-bias system dynamically adjusts well-bias set points to optimal levels across an integrated circuit (IC) for enhanced power savings and component reliability during a standby or low-power mode of operation. A controller within the IC determines if the chip power supply voltage will be reduced during an imminent standby or low power mode and sets a register controlling a negative well-bias set point for asserting well-bias to charge wells of the IC accordingly. To minimize leakage current without compromising reliability, the well-bias set point is set to (1) an optimal well-bias set point if a reduced supply voltage is to be applied to the IC, or (2) a minimum well-bias set point when a nominal or high supply voltage is to be applied to the IC.

Abstract: A booster circuit for boosting an externally supplied voltage includes a plurality of parallel-connected charge pump units. The charge pump units are activated successively in accordance with a boosted voltage to suppress peak current at start-up of the booster circuit and reduce fluctuation of power supply voltage.

Abstract: A temperature-independent voltage reference containing two independent bias circuits powered by the reference voltage, each bias circuit containing components with an exponential dependence of current on voltage and one containing a resistive impedance, and further including voltage dividers and an active component.

Abstract: A current sharing apparatus and a method thereof are provided. The current sharing apparatus comprises an input terminal, an output terminal, a current-sharing control terminal, a pass transistor, a constant voltage generating unit, a feedback control circuit and a current-sharing control unit. The current-sharing control terminal provides a current-sharing control interface. The pass transistor receives an input voltage and provides an output voltage and an output current. The feedback control circuit senses the output current to provide a current-sense signal and regulates a control signal of the pass transistor for controlling an output of the current-sharing apparatus. Moreover, the current-sharing control unit electrically coupled to the current-sharing control terminal and the feedback control circuit generates a bus signal in response to the current-sense signal and a reference voltage and generates a reference signal in response to the reference voltage, the bus signal and the current-sense signal.

Abstract: A power amplifier circuit comprising first and second modules, a current source and a push-pull module. The push-pull module comprises two intermediate transistors and two output transistors. The circuit also comprises third and fourth modules, operating in current mirror mode. Inputs of the third module are respectively connected to one main electrode of one of the intermediate transistors and to a node internal to the first module. Outputs of the fourth module are respectively connected to a main electrode of the other intermediate transistor and to a node internal to the second module. The circuit is designed to form a power output stage of an operational amplifier.

Abstract: A transmitter includes a first variable gain amplifier (VGA) and a second VGA coupled to an output of the first VGA. The first and second VGAs each comprise a plurality of parallel gain stages. Gains of the first and second VGAs are equal to the sum of the gains of the activated parallel amplifiers within each corresponding plurality of parallel amplifiers. Each parallel amplifier comprises a parallel differential amplifier controlled by a pair of switches to activate and deactivate the parallel differential amplifier. The gains of the first and second VGAs are increased by activating additional parallel amplifiers. The gains of the first and second VGAs are decreased by deactivating additional parallel amplifiers. The variable gains of the first and second VGAs provide an extended gain control with improved local oscillator (LO) leakage interference rejection.

Abstract: A device and method for enhancing current driving are provided. The device comprises an operational amplifier, a monitor device, and an auxiliary output device. The monitor device is adopted to monitor whether the non-inverse input signal is close to a maximum or minimum voltage of an input source of the operational amplifier. When the non-inverse input signal is close to the maximum or minimum voltage, the auxiliary output device outputs an auxiliary current to an output terminal of the device of enhancing current driving.

Abstract: In the present invention, pre-distortion of drive signal and generation of bias signal to a power amplifier are both controlled dependent on an instantaneous size of the input signal, for producing a predetermined gain characteristics. Preferably, the bias signal is kept low in amplitude ranges having a high probability to occur, thus giving a high efficiency, and is allowed to increase towards higher amplitudes, preferably all the way to the maximum amplitude. The pre-distorted drive signal is preferably higher than the input signal in the high-efficiency ranges. Preferably, the drive signal is predominantly composed of low-order components. In cases where signal paths of bias signal and drive signal differs significantly, inverse filtering is applied to ensure the simultaneousness at the input of the amplitude element.

Abstract: The invention relates to an input amplifier stage, in AB class, having a controlled bias current and comprising a differential cell, inserted between a first supply voltage reference and a second voltage reference, having a differential pair of input transistors receiving respective differential signals and a pair of bias transistors, as well as an output-buffer circuit portion coupled to the cell by means of at least a supplementary parallel branch of transistors. This stage also comprises an additional circuit block, able to output the absolute value of an input current, inserted between a node of the differential cell of the input stage and a node of the supplementary branch in order to add the absolute value of a portion of the signal current to the differential cell bias current.

Abstract: The invention relates to a feedback or feedforward type variable gain wideband amplifier. The variable gain wideband amplifier includes a feedback-type inversion amplifier circuit 310 for amplifying input Vin, a feedback-type non-inversion amplifier circuit 320 for amplifying input Vin, a power source circuit 330 for controlling the gain of the non-inversion amplifier circuit 320 and a load circuit 340 connected between a junction of output terminals of the inversion and non-inversion amplifier circuits 310 and 320 and power voltage potential VDD to control the gain of the amplifier circuits 310 and 320. The variable gain wideband amplifier of the invention is feedforward type, and outputs signals from the inversion and non-inversion amplifier circuits 310 and 320 via a single output terminal in order to attenuate third order intermodulation frequency IM3 generated from the amplifier circuits 310 and 320. Then, predetermined frequencies f1 and f2 included in the input signal are amplified.

Abstract: A dynamic bias circuit for an RF amplifier is provided to overcome the drawbacks of conventional bias circuits. The dynamic bias circuit of the present invention is best used for an RF amplifier having an FET amplifying transistor. It automatically raises the DC bias point as the input power increases. As a result, the saturation of output power in the pinch-off region can be avoided. This dynamic bias circuit not only improves the operating characteristics of the RF amplifier, such as high operating efficiency and high-linearity output power, but also consumes zero power in its internal circuitry. Furthermore, it has a simple circuit structure with very few circuit components and a reduced chip area. It can thus be easily integrated into an amplifier to achieve a cost reduction.

Abstract: Disclosed herein is a layout structure of a signal driver. The layout structure of the signal driver of the present invention includes a first signal response unit, a second signal response unit, and a current source unit. The first signal response unit responds to a first input signal, and the second signal response unit responds to a second input signal. The current source unit has a plurality of bias unit pairs for restricting currents provided to the first and second signal response units to respective source currents thereof. The bias unit pairs each include at least two bias units, which are separately arranged on opposite sides of a predetermined imaginary centerline. According to the layout structure of the signal driver of the present invention, there is a benefit in that current mismatch occurring between the first and second current response units is reduced, thus consequently improving the operating characteristics of the signal driver.

Abstract: A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.

Abstract: During a period of preparation for actual operation, a reference clock is supplied to both a comparison clock input portion and a feedback clock input portion of a phase comparator while a feedback loop of a PLL (phase-locked loop) is interrupted, and a delay of a reset signal within the phase comparator is adjusted so as to reduce a detection dead zone of phase differences in the phase comparator.

Abstract: A standing wave oscillator to generate at least one voltage standing wave, comprising a closed-loop coplanar stripline including two conductors, and at least one amplifier disposed between the two conductors at a first location. The two conductors are connected together at a second location different from the first location to provide a zero voltage node for the at least one voltage standing wave. One or more of a tailored distributed amplification scheme, a plurality of linear conductive strips disposed in proximity to the coplanar stripline, and a tapered coplanar stripline configuration may be used with the closed loop structure. A particular amplifier configuration involving cross-coupling of the coplanar stripline conductors may be employed to facilitate single mode operation, using a particular resonator topology so as to avoid inducing significant loss in the oscillator.

Abstract: A microstrip stabilized quantum well resonance-tunneling generator which generates electromagnetic waves for millimeter and submillimeter wavelength range is provided The generator includes a resonant tunneling semiconductor quantum well diode, and a microstrip resonator. The resonant tunneling diode, the microstrip resonator and interconnecting lines and junctions are fabricated as a monolithic integrated device on a common substrate. As a result, the monolithic integrated device provides the expansion of the operation frequency range toward the terahertz region as a result of reduction of the parasitic inductance as well as of minimizing the other parasitic parameters of the electric circuitry connecting the resonant tunneling diode and resonator.

Abstract: Methods and apparatus are disclosed for adjusting the frequency tuning range of an oscillator circuit. The oscillator circuit is comprised of at least two MOS devices; a first reactance connecting a drain electrode of a first MOS device to a gate electrode of a second MOS device and a second reactance connecting a drain electrode of the second MOS device to a gate electrode of the first MOS device; and a tank circuit connected to the source and drain electrodes. The first and second reactance may comprises a capacitor or a diode or a combination thereof. In addition, one or more resistors may optionally be connected between a gate electrode of at least one of the MOS device and a power source.

Abstract: A circuit for controlling the switching frequency of an oscillator for a PWM controller for a switching mode power supply, comprising a first stage providing a signal which is related to the temperature of the controller for the switching mode power supply; and an oscillator having an oscillation frequency and being responsive to the signal from the first stage for changing the oscillation frequency such that the oscillation frequency decreases as the temperature increases and vice versa.

Abstract: A method is performed for influencing the signal shape of an output signal of an RF power resonance amplifier and an RF excitation arrangement including an RF power resonance amplifier. A basic signal of a basic frequency is amplified and modulated with a modulation signal, and an output oscillating circuit of the RF power resonance amplifier is tuned to a frequency in the range of the basic frequency, and is excited with the basic signal during normal operation. At times that are or can be predetermined, the output oscillating circuit is driven with a driving signal that differs from the basic signal, for a time period that is or can be predetermined. This reduces the dying down time of the output oscillating circuit and increases the steepness of the output signal edges.

Abstract: A balun in which the phase shift may be reduced significantly is disclosed. The balun has three lines, i.e. a first line b, a second line a and a third line c, arranged in parallel with the ground surface. The second line a and the third line c are arranged at the same height from the ground surface GC, the longitudinal length of each respective one of the first line b, second line a and third line c are specified to be equal to a quarter (¼) of the wavelength at the central frequency in the working band, and the capacitance Ca between the second line a and the ground surface GC is specified to be equal to the capacitance Cab between the second line a and the first line b.

Abstract: A balun including a pair of metal coil structures and an intervening dielectric layer having a thickness that is selected in response an operating frequency of the balun. The thickness of the dielectric layer may be used to tune the balun and enhance its self-inductance at its operating frequency. In addition, a balun with a pair of metal coil structures formed with an asymmetry that is selected to minimize an amplitude error in its output signal. A balun according the present teachings may also include an asymmetry in the positioning of its output terminals. The positioning of the output terminals of a balun may be adjusted to minimize phase errors at its output signal.

Abstract: A waveguide-transmission line converter has a waveguide including side walls which have inner corners at an open end of the waveguide. The inner corners are beveled to provide tapered inner surfaces. Even if a dielectric substrate is assembled out of alignment with the waveguide due to an assembling error, edges of a ground metal layer on the dielectric substrate are exposed from the beveled inner corners at the open end of the waveguide. The beveled inner corners keep the waveguide spaced widely from edges of a matching element on the dielectric substrate, preventing an electric field concentration from occurring between the waveguide and the matching element. The waveguide-transmission line converter has electromagnetic energy passing and reflecting characteristics prevented from varying.

Abstract: An input-matching network including an acoustic resonator providing a virtual impedance to match impedance between a first component and second component. As an example, the first component may be an antenna and the second component may be an amplifier. The acoustic resonator provides a virtual impedance to match impedance between the antenna and the amplifier. The acoustic resonator may be, for example, a film bulk acoustic (fbar) resonator or a surface acoustic wave (saw) resonator.