Abstract: A charged particle beam apparatus is provided which comprises a charged particle source for producing a primary beam of charged particles, aperture means for collimating said primary beam of charged particles, wherein said aperture means is adapted to switch between a collimation of said primary beam resulting in a width appropriate for serial imaging of a sample as well as a collimation of said primary beam to a width appropriate for parallel imaging of said sample, a condenser lens for condensing said primary beam of charged particles, scanning means for deflecting said primary beam of charged particles, an objective lens for focusing said condensed primary beam, a sectorized detector for detecting a secondary charged particles. Also, several different operation modes of the beam apparatus are described allowing for serial imaging as well as parallel imaging.

Abstract: A method of controlling the coordinate sensitivity in a superconducting microbolometer employs localized light, heating or magnetic field effects to form normal or mixed state regions on a superconducting film and to control the spatial location. Electron beam lithography and wet chemical etching were applied as pattern transfer processes in epitaxial Y—Ba—Cu—O films. Two different sensor designs were tested: (i) a 3 millimeter long and 40 micrometer wide stripe and (ii) a 1.25 millimeters long, and 50 micron wide meandering-like structure. Scanning the laser beam along the stripe leads to physical displacement of the sensitive area, and, therefore, may be used as a basis for imaging over a broad spectral range. Forming the superconducting film as a meandering structure provides the equivalent of a two-dimensional detector array. Advantages of this approach are simplicity of detector fabrication, and simplicity of the read-out process requiring only two electrical terminals.

Abstract: A gamma vector camera detects and determines the energy and the direction of an incident gamma ray. The gamma vector camera includes a detector that produces scintillation light upon interaction with the incident gamma ray. A sensor records the locations and the intensities of the scintillation light produced in the detector. A processor determines the energy and the direction of the incident gamma ray based on the locations and the intensities of the scintillation light recorded by the sensor.

Abstract: A ?-ray signal processing section 60? determines a detection time of a ? ray based on a ?-ray detection signal outputted from a semiconductor radiation detector for detecting the ? ray, and determines the energy of the ? ray. Then, a time correction circuit 70 obtains, based on the energy of the ? ray, a detection value of the detection time that corresponds to the energy of the ? ray from a time correction table indicating the relationship between the energy of the ? ray and the correction value of the detection time of the ? ray, and corrects the detection time according to the obtained correction value of the detection time. Coincidence counting is performed on the ? ray in a coincidence counting circuit 80 based on the corrected detection time.

Abstract: A scintigraphic device includes a case open at an application end, and coated by a shielding shell; a collimator positioned inside the case, made of a material with high atomic number and high density and having a plurality of collimation channels extending mutually parallel according to a predefined direction of measurement; a measuring member positioned inside the case in proximity to the collimator and including a scintillation crystal for converting each ionizing radiation originating from a source in exam into light radiation, and at least one photosensor, for determining the energy and the position of each detected event. The measuring member and the collimator are relatively movable to increase and/or reduce the distance between the converter and the application end and consequently to vary the total length of the collimator. The collimator may include two or more blocks at least one of which is movable relative to the others.

Abstract: The gamma-radiation module includes a housing having a box-like container and a cover for hermetically sealing a pair of cylinders within the housing. Each cylinder includes scintillation material and a photomultiplier tube on a common cylindrical axis. The hermetically sealed module may be used singly or in multiple modules in portal applications whereby gamma-radiation from a source may be detected through a gamma-radiation transparent cover on the module.

Abstract: A radiation detector is disclosed for the detection of ionizing radiation, preferably in a medical diagnosis and/or therapy system, having at least one detector element which is at least partially enclosed by an encapsulation compound. The encapsulation compound at least partially reflects light which is produced during the absorption of the ionizing radiation in the at least one detector element. Further, the detection of the radiation is carried out indirectly by detection of the generated light, wherein the encapsulation compound is made of a multicomponent mixture which converts compounds produced because of radiation, which generate color changes of the encapsulation compound, at least partially into colorless nonabsorbing compounds.

Abstract: The invention relates to a detector, and to a method for the production thereof, for detecting a high-energy and high-intensity particle beam (2), which comprises a crystalline semi-conductor plate (3) having a metal coating (4) and which is arranged on a substrate (5), the semi-conductor plate (3) being a diamond plate (6), which is coated on both faces with metal structures (7, 8). The metal structures (7, 8) comprise aluminium and/or an aluminium alloy and form electrodes, which are arranged to be connected to various electrical potentials by way of conductor tracks (10) on the substrate (5), the substrate (5) being a ceramic plate (11) having a central orifice (24), which is covered by the diamond plate (6).

Abstract: The present invention is related to an apparatus for irradiating products conveyed on a pallet, comprising a beam source (3) for producing a radiation beam, a shielding wall (4) encompassing an irradiation chamber (2) and a revolving cylindrical door (6) having a recess (8) for holding said pallet, for bringing said pallet in and out of the irradiation chamber (2) wherein said high-energy radiation beam is directed towards a lateral side of said revolving door (6), for irradiating said pallet in said recess (8), or brought before said recess (8). The present invention is also related to a process wherein a product pallet is brought into an irradiation chamber (2) through a revolving cylindrical door (6) having a recess (8), and irradiated while in said recess (8) or in front of said recess (8).

Abstract: Methods and systems that excite a test structure with an excitation beam and then sense the response of the test structure after some prescribed time interval with respect to the excitation. One or more detectors detect an emission from the test structure at a location of the test structure that is offset from a position on the test structure that is coincident with the excitation beam as the beam is scanned across the test structure.

Abstract: A method spectrally and temporally characterizing the fluorescence and/or phosphorescence of a material includes using a frequency-domain cross-correlation fluorometer-phosphorimeter employing an interferometer. A flux-modulated excitation signal is used to excite the material. An interferometer is used to generate an optical path difference (OPD) between portions of an emission signal produced by the excited material to obtain an optical interference signal. The optical interference signal is detected by a heterodyning detection system to determine phase shift and demodulation of the emission signal relative to the excitation signal. Phase shift and demodulation data are acquired at a series of OPD values generated by the interferometer and at a plurality of light source flux-modulation frequencies at each OPD to spectrally and temporally resolve the emission signal.

Abstract: A projection system comprises an array of lenses MLA, each lens transmitting a unique part of a patterned beam. Measuring devices measure a distance between the array of lenses MLA and a substrate W. A controller controls an actuator to adjust a position (e.g., height and/or tilt) of the microlens array MLA.

Abstract: The invention is directed to an apparatus for generating soft x-radiation, particularly EUV radiation, by laser-induced plasma. The object of the invention, to find a novel possibility for generating EUV radiation by means of a laser-induced plasma by which a temporally stable radiation emission in the desired wavelength region is ensured when interacting with the target without active regulation of the laser beam, is met according to the invention in that at least one laser is directed to the target, wherein the laser has at least one defined plane with a highly stable spatial distribution of the power density of the laser, and this defined plane is imaged on the target by an optical imaging system so as to be reduced so that the optical image of the defined plane is active for the plasma generation instead of the laser focus. The invention is applied in exposure machines for semiconductor lithography for spatially stable generation of radiation.

Abstract: An elastic, radiation shielding material that can be severed readily with conventional tools, such as scissors and is sufficiently flexible so as to allow wrapping it around piping and tubing. The radiation shielding material comprises a rubber component and a radiation attenuating metal in amounts effective to obtain a desired balance of flexibility and radiation attenuation, respectively. By varying the amount of rubber and metal in the material a desired level of flexibility and radiation attenuation may be obtained.

Abstract: An apparatus for document processing comprises an optical sensor including a light source, a light detector and an optical element. The optical sensor is adapted so that, during operation of the apparatus, at least a first portion of light from the source that enters the optical element travels along paths in the optical element so as to be re-directed by total internal reflection toward the detector and wherein the total internal reflection is maintained when the optical element is wet. Signals form the optical sensor may be used to determine, for example, the state of a document storage cassette or the location of a document with respect to the cassette.

Abstract: A method for reading radiation image information in which a cassette is lowered while keeping each short side of the cassette extending vertically, and then inserted into a radiation image reading apparatus which has a cassette loading inlet in its upper surface and the inserted cassette is taken into the apparatus, and next the front base and the back base are disengaged in the apparatus and both are separated, and after the radiation image information is read from the stimulable phosphor sheet of the back base which are separated from the front base, and then the front base and the back base are joined and ejected from the insertion opening of the apparatus. The apparatus height is smaller than in the method in which the stimulable phosphor sheet is pulled downward from the cassette and is read, and the operation of lifting the cassette against the force of gravity up to the height of the upper surface of the apparatus becomes unnecessary at the time of inserting the cassette.

Abstract: A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a chalcogenide glass region is provided with a plurality of alternating tin chalcogenide and metal layers proximate thereto. The method of forming the device comprises sputtering the alternating tin chalcogenide and metal layers.

Abstract: A composition for the formation of an electric field programmable film, the composition comprising a matrix precursor composition or a dielectric matrix material, wherein the dielectric matrix material comprises an organic polymer and/or a inorganic oxide; and an electron donor and an electron acceptor of a type and in an amount effective to provide electric field programming. The films are of utility in data storage devices.

Abstract: A TFT including a gate metallic layer, a body layer doped with a dopant having a first polarity, a source layer and a drain layer doped with a dopant having a second polarity, a semiconductor layer formed between the source layer and the drain layer, and a contact coupling the gate metallic layer and the body layer.

Abstract: A thin film transistor including an active layer formed on an insulating substrate and having channel, source, and drain regions formed therein, wherein a voltage is applied to the channel region to discharge hot carriers generated in the channel region.

Abstract: The present invention provides a method for forming by plasma CVD a silicon nitride film that can be formed over heat-sensitive elements as well as an electroluminescent element and that has favorable barrier characteristics. Further, the present invention also provides a semiconductor device, a display device and a light-emitting display device formed by using the silicon nitride film. In the method for forming a silicon nitride film by plasma CVD, silane (SiH4), nitrogen (N2) and a rare gas are introduced into a deposition chamber in depositing, and the reaction pressure is within the range from 0.01 Torr to 0.1 Torr.

Abstract: A method of fabricating a substrate for an organic electroluminescent display device includes forming a first electrode on a substrate in a pixel region and a non-pixel region, the first electrode including a first conductive material, forming an auxiliary electrode on the first electrode in the non-pixel region, the auxiliary electrode including a second conductive material and contacting the first electrode, the first and second conductive materials being different from one another, forming a bank corresponding to the auxiliary electrode, the bank surrounding the pixel region, forming an organic electroluminescent layer on the first electrode, the organic electroluminescent layer in the pixel region surrounded by the bank, and forming a second electrode on the organic electroluminescent layer, the second electrode corresponding to the organic electroluminescent layer.

Abstract: A light emitting device includes a substrate, a doped substrate layer, a layer of first conductivity type overlying the doped substrate layer, a light emitting layer overlying the layer of first conductivity type, and a layer of second conductivity type overlying the light emitting layer. A conductive transparent layer, e.g., of indium tin oxide, and a reflective metal layer overlie the layer of second conductivity type and provide electrical contact with the layer of second conductivity type. A plurality of vias may be formed in the reflective metal and conductive transparent layer as well as the layer of second conductivity type, down to the doped substrate layer. A plurality of contacts are formed in the vias and are in electrical contact with the doped substrate layer. An insulating layer formed over the reflective metal layer insulates the plurality of contacts from the conductive transparent layer and reflective metal layer.

Abstract: An electronic or optoelectronic device fabricated from a crystalline material in which a parameter of a bandgap characteristic of said crystalline material has been modified locally by introducing distortions on an atomic scale in the lattice structure of said crystalline material and the electronic and/or optoelectronic parameters of said device are dependent on the modification of said bandgap is exemplified by a radiation emissive optoelectronic semiconductor device which comprises a junction (10) formed from a p-type layer (11) and an n-type layer (12), both formed from indirect bandgap semiconductor material. The p-type layer (11) contains an array of dislocation loops which create a strain field to confine spatially and promote radiative recombination of the charge carriers.

Abstract: A light emitting device having an anti-reflective member. The light emitting device includes an anti-reflective member including a reflective layer and a first electrode; a second electrode; and a light emitting layer disposed between the first electrode and the second electrode. The first electrode of the present invention has both electrode and anti-reflective functions. Ambient light is reflected by the first electrode to obtain a first reflected light and reflected by the reflective layer to obtain a second reflected light. The first reflected light and the second reflected light have phase difference; thus, the reflection of ambient light is reduced.

Abstract: Light emitting diode systems are disclosed. An optical display system that includes a light emitting diode (LED) and a cooling system is disclosed. The cooling system is configured so that, during use, the cooling system regulates a temperature of the light emitting diode.

Abstract: It is an object of the present invention to provide an active matrix light emitting device which can efficiently prevent a diffusion of impurities from a substrate to a transistor, as well as reducing a reflection of light in a process of extracting light toward the outside of the light emitting device. One feature of the present invention is a light emitting device including a substrate, a first insulating layer provided over the substrate, a transistor provided over the first insulating layer, and a second insulating layer having a first opening portion which is provided to expose the substrate as well as covering the transistor, wherein a light emitting element is provided inside the first opening portion.

Abstract: Boron containing phosphor compositions having the formulas (1) M3Ln2(BO3)4 doped with at least one activator selected from the group of Eu2+, Mn2+, Pb2+, Ce3+, Eu3+, Tb3+, and Bi3+ where M is at least one of Mg, Ca, Sr, Ba, or Zn, and Ln is at least one of Sc, Y, La, Gd, or Lu; (2) M2?xM?x(Al, Ga)2?y(Si, Ge)yB2O7?zNz:Eu2+, Mn2+, Pb2+ where M? is one or more of alkali metals Na and/or K, M? is one or more of alkaline earth Mg, Ca, Sr, Ba or Zn, 0?x?2, 0?y?2, 0?z?4; and z=x+y; (3) M?2?x+y?M?x?y?(Al, Ga)2?y(Si, Ge)yB2O7?z?y?NzXy:Eu2+, Mn2+, Pb2+, where M? is one or more of alkali metals Na and/or K, M? is one or more of alkaline earth metals Mg, Ca, Sr, Ba and/or Zn, 0?x?2, 0?y?2, 0?z?4; z=x+y, X?F and/or Cl, and 0?y??2; (4) M?2?xM?xAl2?y+y?Siy?y?B2O7?z?y?NzXy:Eu2+, Mn2+, Pb2+, where M? and M? are defined above, 0?x?2, 0?y?2, 0?z?4; z=x+y, X?F and/or Cl, and 0?y??2; (5) M?2?x+x?M?x?x?Al2?y+y?Siy?y?B2O7?z?x??y?NzX(x?+y?):Eu2+, Mn2+, Pb2+, where M? and M? are defined above, 0?x?2, 0?y?2, 0?z?4; z=x+y, X?F and/or C

Abstract: The present invention provides a tri-gate lower power device and method for fabricating that tri-gate semiconductor device. The tri-gate device includes a first gate [455] located over a high voltage gate dielectric [465] within a high voltage region [460], a second gate [435] located over a low voltage gate dielectric [445] within a low voltage core region [440] and a third gate [475] located over an intermediate core oxide [485] within an intermediate core region [480]. One method of fabrication includes forming a high voltage gate dielectric layer [465] over a semiconductor substrate [415], implanting a low dose of nitrogen [415a] into the semiconductor substrate [415] in a low voltage core region [440], and forming a core gate dielectric layer [445] over the low voltage core region [440], including forming an intermediate core gate dielectric layer [485] over an intermediate core region [480].

Abstract: An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry. The ESD protection circuit includes a silicon controlled rectifier (SCR) having at least one first type high dopant region coupled to a first reference potential of the protected circuitry, and at least one second type high dopant region coupled to a second reference potential of the IC. The SCR is triggered by an external on-chip trigger device, which is adapted for injecting a trigger current into at least one gate of the SCR.

Abstract: In accordance with the objectives of the invention a new arrangement is provided for ESD protection of mounted flip chips. In a first embodiment of the invention, the Input/Output cells and power cells are provided with ESD protection that is connected to a dedicated bump pad. The substrate of the flip chip package interconnects all of the dedicated bump pads, completing the ESD network. Under the second embodiment of the invention, the Input/Output cells and power cells are provided with ESD protection that is connected to a dedicated bump pad, a last metal layer interconnects all of the dedicated bump pads, completing the ESD network.

Abstract: The invention includes a semiconductor processing method wherein an insulative mass is formed across a first electrical node and a second electrical node. The mass has a pair of openings extending therethrough to the electrical nodes. The individual openings each have a periphery defined by one of the electrical nodes and at least one sidewall. One of the openings extends to the first electrical node and is a first opening, and the other of the openings extends to the second electrical node and is a second opening. A dielectric material layer is formed within the openings to narrow the openings. Conductive material plugs are formed within the narrowed openings. The conductive material plug within the first opening is a first material plug, and is separated from the first electrical node by the dielectric material; and the conductive plug within the second opening is a second material plug, and is not separated from the second electrical node by the dielectric material.

Abstract: Apparatus, packaging, and methods of manufacture of an integrated circuit are provided. The integrated circuit includes a component of a first type fabricated on a first substrate containing a first material, and a component of a second type fabricated on a second substrate containing a second material. The first material has better compatibility than the second material with fabrication and/or performance of the component of the first type, while the second material has better compatibility than the first material with fabrication and/or performance of the component of the second type. Also described, is a method of making the above-mentioned integrated circuit, the method including, among other steps, the step of disposing the first and second substrates opposite one another, and the step of establishing an electrical connection between the components.

Abstract: In a field effect transistor (FET), and a method of fabricating the same, the FET includes a semiconductor substrate, source and drain regions formed on the semiconductor substrate, a plurality of wire channels electrically connecting the source and drain regions, the plurality of wire channels being arranged in two columns and at least two rows, and a gate dielectric layer surrounding each of the plurality of wire channels and a gate electrode surrounding the gate dielectric layer and each of the plurality of wire channels.

Abstract: A charge splitter for separating an incoming charge packet into two outgoing packets while the charge is in a static state, i.e., not while it is flowing down a channel or over a barrier. A splitting gate may have a biasing charge impressed upon it, such as via the application of voltage or current sources to opposite ends thereof, applying a bias to a semiconductor body portion of the gate structure, or by physically separate the splitting gate into multiple sections that each have different applied voltages or currents When discharge barrier gates are operated, different amounts of charge will thus flow to different output storage gates.

Abstract: A fin-type field effect transistor (FinFET) has a fin having a center channel portion, end portions comprising source and drain regions, and channel extensions extending from sidewalls of the channel portion of the fin. The structure also includes a gate insulator covering the channel portion and the channel extensions, and a gate conductor on the gate insulator. The channel extensions increase capacitance of the channel portion of the fin.

Abstract: CMOS and CCD imaging devices comprising different in-pixel capacitors and peripheral capacitors and methods of formation are disclosed. The capacitors used in periphery circuits have different requirements from the capacitors used in the pixel itself. Dual stack capacitors comprising two dielectric layers may be provided to achieve low leakage and high capacitance. A single masking step may be provided such that one region has a dual dielectric capacitor and a second region has a single dielectric capacitor. A different dielectric may also be provided in one region compared to another region wherein the inter-electrode insulator comprises a single dielectric in both regions.

Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.

Abstract: The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. The transistors have gates that are wider than the underlying sub-regions. The invention also includes a semiconductor construction that has transistor constructions with insulative spacers along gate sidewalls. Each transistor construction is between a pair source/drain regions that extend beneath the spacers. A source/drain extension extends the source/drain region farther beneath the transistor constructions on only one side of each of the transistor constructions. The invention also includes methods of forming semiconductor constructions.

Abstract: Techniques for reducing switching fields in semiconductor devices are provided. In one aspect, a semiconductor device comprising at least a first magnetic layer and a second magnetic layer with a spacer layer therebetween is provided. The semiconductor device is configured such that a thickness of at least one of the first magnetic layer and the second magnetic layer maintains a desired activation energy of the semiconductor device in the presence of an applied offsetting magnetic field. A method of reducing a switching field of a semiconductor device having at least a first magnetic layer and a second magnetic layer with a spacer layer therebetween is also provided.

Abstract: A ferroelectric/paraelectric multilayer thin film having a high tuning rate of a dielectric constant and small dielectric loss to overcome limitations of a tuning rate of a dielectric constant and dielectric loss of a ferroelectric thin film, a method of forming the same, and a high frequency variable device having the ferroelectric/paraelectric multilayer thin film are provided. The ferroelectric/paraelectric multilayer thin film includes a perovskite ABO3 structure paraelectric seed layer formed on a substrate, and an epitaxial ferroelectric (BaxSr1-x)TiO3 thin film formed on the paraelectric seed layer. The high frequency variable device can realize a RF frequency/phase variable device having a high speed, low power consumption, and low prices and excellent microwaves characteristics.

Abstract: The invention includes methods of forming rugged electrically conductive surfaces. In one method, a layer is formed across a substrate and subsequently at least partially dissociated to form gaps extending to the substrate. An electrically conductive surface is formed to extend across the at least partially dissociated layer and within the gaps. The electrically conductive surface has a rugged topography imparted by the at least partially dissociated layer and the gaps. The topographically rugged surface can be incorporated into capacitor constructions. The capacitor constructions can be incorporated into DRAM cells, and such DRAM cells can be incorporated into electrical systems.

Abstract: A memory cell array includes memory cells with storage capacitor and an access transistor. The access transistors are formed in active areas. The memory cell array further includes bit lines oriented in a first direction and word lines oriented in a second direction. The active areas extend in the second direction. The bottom side of each gate electrode of the transistors is disposed beneath the bottom side of each word line. In addition, the word lines are disposed above the bit lines.

Abstract: The invention includes methods of forming rugged electrically conductive surfaces. In one method, a layer is formed across a substrate and subsequently at least partially dissociated to form gaps extending to the substrate. An electrically conductive surface is formed to extend across the at least partially dissociated layer and within the gaps. The electrically conductive surface has a rugged topography imparted by the at least partially dissociated layer and the gaps. The topographically rugged surface can be incorporated into capacitor constructions. The capacitor constructions can be incorporated into DRAM cells, and such DRAM cells can be incorporated into electrical systems.

Abstract: A non-volatile memory is provided. A substrate has at least two isolation structures therein to define an active area. A well is located in the substrate. A shallow doped region is located in the well. At least two stacked gate structures are located on the substrate. Pocket doped regions are located in the substrate at the peripheries of the stacked gate structures; each of the pocket doped regions extends under the stacked gate structure. Drain regions are located in the pocket doped regions at the peripheries of the stacked gate structures. An auxiliary gate layer is located on the substrate between the stacked gate structures. A gate dielectric layer is located between the auxiliary gate layer and the substrate and between the auxiliary gate layer and the stacked gate structure. Plugs are located on the substrate and extended to connect with the pocket doped region and the drain regions therein.

Abstract: In a nonvolatile memory cell having at least two floating gates, each floating gate (160) has an upward protruding portion. This portion can be formed as a spacer over a sidewall of the select gate (140). The spacer can be formed from a layer (160.2) deposited after the layer (160.1) which provides a lower portion of the floating gate. Alternatively, the upward protruding portion and the lower portion can be formed from the same layers or sub-layers all of which are present in both portions. The control gate (170) can be defined without photolithography. Other embodiments are also provided.

Abstract: Non-volatile field effect devices and circuits using same. A non-volatile field effect device includes a source, drain and gate with a field-modulatable channel between the source and drain. Each of the source, drain, and gate have a corresponding terminal. An electromechanically-deflectable, nanotube switching element is electrically positioned between one of the source, drain and gate and its corresponding terminal. The others of the source, drain and gate are directly connected to their corresponding terminals. The nanotube switching element is electromechanically-deflectable in response to electrical stimulation at two control terminals to create one of a non-volatile open and non-volatile closed electrical communication state between the one of the source, drain and gate and its corresponding terminal. Under one embodiment, one of the two control terminals has a dielectric surface for contact with the nanotube switching element when creating a non-volatile open state.

Abstract: A NAND memory device has a source line connected to two or more columns of serially-connected floating-gate transistors. The source line includes a first conductive layer formed on a substrate and coupled to source select gates associated with the two or more columns of serially-connected floating-gate transistors. The source line also includes a second conductive layer formed on the first conductive layer, where the second layer has a greater electrical conductivity than the first conductive layer.

Abstract: There are provided highly integrated semiconductor memory devices being suitable for storing two bits of data in one unit cell, and methods of fabricating the same. The unit cell of the semiconductor memory device includes a semiconductor substrate and source and drain regions formed in the semiconductor substrate and spaced from each other. First and second data lines are formed to run across over a channel region between the source and drain regions and to be disposed adjacent to the source and drain regions respectively. A first MTJ barrier layer pattern is disposed between the first data line and the channel region. A second MTJ barrier layer pattern is disposed between the second data line and the channel region. A first floated storage node is disposed between the first MTJ barrier layer pattern and the channel region. A second floated storage node is disposed between the second MTJ barrier layer pattern and the channel region.

Abstract: Structures and methods for in service programmable logic arrays with low tunnel barrier interpoly insulators are provided. The in-service programmable logic array includes a first logic and a second logic plan having a number of logic cells arranged in rows and columns that are interconnected to produce a number of logical outputs such that the in service programmable logic array implements a logical function. The logic cell includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of PbO, Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5 and/or a Perovskite oxide tunnel barrier.