Abstract: A method according to one embodiment may include providing a heatsink having a base having a first region with a thickness greater than a second region. The heatsink may further include a plurality of fins extending from the base with at least one fin oriented at an angle to at least another fin. The method of this embodiment may also include thermally coupling the heatsink to the heat generating component. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract: A supporting plate includes a metal plate and is utilized to support a heat sink module in an electronic device. The heat sink module has a thermal pad, and the electronic device has a first heat generating element and a second heat generating element. In addition, the heat sink module is contacted to the first heat generating element for conducting heat generated by the first heat generating element to the thermal pad. Moreover, the metal plate has a first concave portion and a second concave portion. The first concave portion is contacted to the thermal pad, and the second concave portion is contacted to the second heat generating element for conducting heat generated by the second heat generating element to the heat sink.

Abstract: A method and assembly for mounting power electronics modules in an equipment cabinet, cubicle or other like equipment space. According to the invention, the power electronics modules are mounted in the equipment space (1) with the help of mounting bases (3), such that the mounting bases (3) comprise fixture means (13, 14) for fixing the mounting base in the equipment space (1) and a mounting plate (16) fixed supportedly by the fixture means (13, 14) so that the first end of the mounting plate is situated closer to the fixture means (14) of the first end than the opposite end (11) of the mounting plate (3) from the fixture means (13) of this opposite end, whereby the mounting plate (16) becomes aligned in a slanted position in the equipment space.

Abstract: A circuit with a magnetically variable transformer having primary and secondary windings wound on a magnetic core wherein the transformer core with associated windings is placed in close proximity to an independently wound control coil. The transformer core is placed within the bore of the control coil and an optional focusing armature concentrates the magnetic field at the poles. Application of a control current forms poles at the control coil extremities and causes a change in permeability of the transformer core thereby altering the power output of the transformer inversely to the magnitude of the control current. The control current from the output of the secondary coil of a current transformer in series with the load and conditioned by a feedback conditioning circuit modulates the level of the control current. The magnetically variable transformer controls a D.C. to A.C. inverter circuit, which is useful in supplying power to a fluorescent lamp and other A.C. receptive loads.

Abstract: A switching power system for converting an input voltage to an output voltage across a transformer is disclosed. The system includes a control circuit. The control circuit has a control input coupled for receiving the output voltage and an output coupled to a primary winding of the transformer. The system includes a bias circuit for supplying an operating voltage to the control circuit. The bias circuit includes a capacitor. The capacitor has a first terminal coupled to a first terminal of a first secondary winding of the transformer. A first diode is coupled between a second terminal of the first secondary winding and a second terminal of the first capacitor. A second diode is coupled between the second terminal of the capacitor and a bias input of the control circuit. A method of making the same is disclosed.

Abstract: An improved power converter that produces reduced-levels of common-mode voltages, or even entirely eliminates such voltages, is disclosed herein, along with a method of reducing common-mode voltages. In at least some embodiments, the improved power converter is equipped with common-mode filter inductors and a link coupling input and output ports of the power converter with one another to communicate a ground point associated with the input ports of the converter (and the source) to the load. Further, in at least some embodiments, the method includes providing common mode filter inductors as part of the converter, where the inductors are connected at least indirectly to at least one of a rectifier and an inverter of the converter, and communicating a grounded neutral from input ports of the converter to output ports of the converter by way of at least one additional linkage.

Abstract: Provided is an electronic instrument in which a starting voltage of a power supply is less than a starting voltage of a general booster circuit, and which is capable of starting efficiently. The electronic instrument includes: a power supply for supplying power; a first booster circuit that is started with the power from the power supply; a capacitor for storing power of the first booster circuit; a second booster circuit that is started with the power in the capacitor; a load circuit operating with power of the second booster circuit; a voltage detection circuit for detecting a voltage of the capacitor; and a switching element controlled by a voltage detection signal, in which, when determining that the voltage of the capacitor is a predetermined voltage or more, the voltage detection circuit turns off the switching element and starts the second booster circuit with the power of the capacitor.

Abstract: The invention relates to a converter circuit having a series circuit of class E converter modules for optimizing the DC supply voltage of the individual converter module (for example C7, C11, Z1, S1, L1, L2).

Abstract: A converter circuit for converting an output voltage from an AC power supply includes a rectifier circuit for rectifying the output voltage of the AC power supply; first and second capacitors connected in series, for smoothing the output of the rectifier circuit; and a switch circuit for switching the connections between the respective capacitors and the AC power supply so that the output voltage of the AC power supply is applied to each of the respective capacitors at a cycle that is shorter than the cycle of the AC power supply.

Abstract: A ternary content addressable memory (TCAM) device comprising a plurality of TCAM cells for storing data, each TCAM cell having two memory cells and a comparison circuit for comparing between data stored in the memory cells and data input on a search line pair connected to the comparison circuit, wherein the comparison circuit comprises a first plurality of MOS transistors connected between a match line and a second plurality of MOS transistors, the second plurality of MOS transistors being connected to ground, wherein the first plurality of MOS transistors are gated by signals from the memory cells connected thereto and the second plurality of transistors are gated by signals from a search line pair. The TCAM device includes redundant memory cells which replaces by corresponding column memory cells determined to be defective. Each line of a search line pair is connected to a defective cell is discharged to ground.

Abstract: A novel array fault testing for a TCAM system that includes a plurality of TCAM blocks that is organized into at least one rectangular array having rows each having a plurality of TCAM blocks, a group of TCAM cells and associated read/write bit lines connecting the group of TCAM cells to write driver and decoding block. The data decode bypass circuit of the TCAM cell provides a raw write feature to detect faults in a full suite of memory related tests. The debug input of the data debug bypass circuit of the TCAM cell when asserted in the test mode enables the TCAM cell to write raw, unencoded data into the array, and when deasserted in the test mode, enables the testing of the TCAM array. The resulting TCAM cell provides exhaustive fault testing thereby detecting and eliminating faults in TCAM.

Abstract: The invention comprises data processing systems and components thereof. Such systems may include a memory controller, a plurality of memory devices, a data bus coupling the memory controller with the plurality of memory devices, and at least one bus switch located in the data bus between the memory controller and one of the plurality of memory devices. Memory integrated circuits and memory modules including at least one switch in the data bus are also provided.

Abstract: Provided is a memory system having a multi-drop bus structure. The memory system includes a bus, a memory controller in which a port connected to the bus is terminated by a resistor having a first impedance value, a connector connected to a point having the first impedance value from the memory controller on a bus line, and a memory module connected to the connector. The memory module includes a first load connected to the connector and having the first impedance value, a second load connected to the first load and having a second impedance value, a first chip in which a port connected to the second load is terminated by a resistor having the second impedance value, a via hole penetrating a printed circuit board of the memory module between the first load and the second load, a third load connected to the via hole and having the second impedance value, and a second chip in which a port connected to the third load is terminated by a resistor having the second impedance value.

Abstract: Provided are a semiconductor memory device having a wordline enable signal line arrangement scheme, which can reduce VPP power consumption and can increase the speed of driving a sub-wordline, and a method of arranging wordline enable signal lines in the semiconductor memory device. In the semiconductor memory device, a wordline enable driver is arranged in a row decoder region outside a memory array region, and the wordline enable signal lines are formed of an uppermost metal layer among three metal layers constituting the semiconductor memory device. Each of the wordline enable signal lines is connected to a sub-wordline driver, rather than to a pair of sub-wordline drivers. In other words, the wordline enable signal lines vertically and horizontally extend forming an inverse L shape.

Abstract: Methods of operating an integrated circuit memory device include providing a first address and a first command to the memory device and executing the first command within the memory device. This step of executing the first command is performed concurrently with providing at least one of a second address and a second command to the memory device prior to terminating execution of the first command. This providing of at least one of the second address and the second command prior to termination execution of the first command improves timing efficiency by reducing delay associated with execution of each new command.

Abstract: A method for programming a phase-change memory array and circuit of a phase-change memory device, each having a plurality of phase-change memory cells, may enable all the phase-change memory cells therein to be changed or set at a set resistance state, and may reduce the time needed to change the phase-change memory array to the set resistance state. In the method, a set current pulse having first through nth stages may be applied to the cells of the array to change the cells to the set resistance state. A minimum current level of the set current pulse applied to the phase-change memory cells in any stage may be higher than a reference current level for the cells of the array. A given current level of the set current pulse may be sequentially reduced from stage to stage.

Abstract: A semiconductor memory element that stores data as a resistance difference. The memory element comprises a MIS transistor, a two-terminal variable resistor element, and a fixed resistor element. The MIS transistor has a gate. The two-terminal variable resistor element is connected between the gate of the MIS transistor and a first power-supply terminal. The variable resistor element has a resistance that changes in accordance with a current flowing in the variable resistor element or the direction in which the current flows and that remains unchanged when the current is made to stop flowing. The fixed resistor element is connected between the gate of the MIS transistor and a second power-supply terminal.

Abstract: A compact dynamic random access memory (DRAM) cell and highly efficient methods for using the DRAM cell are disclosed. The DRAM cell provides reading, writing, and storage of a data bit on an ASIC chip. The DRAM cell includes a first transistor acting as a pass gate and having a first source node, a first gate node, and a first drain node. The DRAM cell also includes a second transistor acting as a storage device and having a second drain node that is electrically connected to the first drain node to form a storage node. The second transistor also includes a second source node and a second gate node. The second source node is electrically floating, thus increasing the effective storage capacitance of the storage node.

Abstract: An SRAM cell 1 includes inverters 10, 20, N-type FETs 32, 34, 36, 38, word lines 42, 44, bit lines 46, 48, and voltage applying circuits 50, 60. The voltage applying circuits 50, 60 apply a voltage Vdd to the word lines 42, 44 at the time of a read operation of the SRAM cell 1. The voltage applying circuits 50, 60 apply a voltage (Vdd+?) to the word lines 42, 44 at the time of a write operation of the SRAM cell 1. Here, ?>0. Namely, the SRAM cell 1 is configured in such a manner that a voltage applied to word lines 42, 44 at the time of the write operation is higher than at the time of the read operation.

Abstract: A random access memory includes a memory cell having an access device. The access device is switched on or off in accordance with a signal on a wordline to conduct a memory operation through the access device. A logic circuit is coupled to the wordline to delay or gate the wordline signal until an enable signal has arrived at the logic circuit. The access device improves stability and eliminates early read problems.

Abstract: A magnetic random access memory (MRAM) is compensated for write current shunting by varying the bit size of each MRAM cell with position along the write line. The MRAM includes a plurality of magnetic tunnel junction memory cells arranged in an array of columns and rows. The width of each memory cell increases along a write line to compensate for write current shunting.

Abstract: A single cell that has a gate insulating film formed with an ONO film is provided in a region in which two bit lines cross one word line. The single cell is a four-bit multi-value cell, and has four charge accumulation regions. Two plug-like control electrodes are provided in the region surrounded by the word line and the bit lines. A bias is applied to one of the plug-like control electrodes and the word line so that the portion on the surface of the semiconductor substrate that is located immediately below the word line and corresponds to the location of the bias-applied control electrode is put into an accumulation state or a depletion state. In this manner, the width of the channel is adjusted, and the charge holding state of each of the four charge accumulation regions is controlled through the channel width adjustment.

Abstract: A nonvolatile ferroelectric memory device is provided so as to control read/write operations of a nonvolatile memory cell using a channel resistance of the memory cell which is differentiated by polarity states of a ferroelectric material. In the memory device, an insulating layer is formed on a bottom word line, and a floating channel layer comprising a P-type drain region, a P-type channel region and a P-type source region is formed on the insulating layer. Then, a ferroelectric layer is formed on the floating channel layer, and a word line is formed on the ferroelectric layer. As a result, the resistance state induced to the channel region is controlled depending on the polarity of the ferroelectric layer, thereby regulating the read/write operations of the memory cell array.

Abstract: A non-volatile memory electronic device is integrated on a semiconductor with an architecture including at least one memory matrix organized in rows or word lines and columns or bit lines of memory cells. The matrix is divided into at least a first and a second memory portions having a different access speed. The first and second memory portions may share the structures of the bit lines which correspond to one another and one by one and are electrically interrupted by controlled switches placed between the first and the second portions.

Abstract: A method for erasing or programming a nonvolatile memory device comprising a memory cell, a sense amplifier, and a page memory, the method comprising the steps of: performing an erasure or programming operation in a manner dependent on the data stored in the page memory, reading out the content of the erased or programmed memory cells, modifying the content of the page memory in a manner dependent on the data read out, and performing a further erasure or programming operation in a manner dependent on the modified data, and the data read out from the erased or programmed memory cell being fed to the page memory, and the content of the page memory being modified in a manner solely dependent on these data and control signals controlling the temporal sequence.

Abstract: The method for programming non-volatile memory cells erases the memory cells to be programmed. The memory cells are then programmed to a reduced floating gate voltage that takes into account capacitive coupling between the floating gates of adjacent memory cells. In one embodiment, the programming method programs and verifies a first memory cell to the reduced floating gate voltage, programs and verifies an adjacent memory cell to the reduced floating gate voltage, and verifies the first memory cell to an increased floating gate voltage that is greater than the reduced floating gate voltage.

Abstract: A method and arrangement are provided for programming an electrically erasable programmable read-only memory cell capable of storing at least one information bit. The memory cell has a charge-trapping region. According to the invention, during a first period of time, a fixed voltage is applied to the memory cell to inject and store electrical charge in the charge-trapping region. This period of time is followed by second period of time during which a constant current is applied to the memory cell to complete the programming step. By monitoring a change in voltage during the second period of time, a monitoring of a resulting threshold voltage is possible directly during programming.

Abstract: A nonvolatile integrated circuit memory device includes a memory cell array having a plurality of memory cells. A high voltage generating unit generates first, second, and third program voltages used in programming the memory cell array. A program control unit controls times of applying the second and third program voltages to the memory cell array responsive to the first program voltage. Programming methods for the nonvolatile integrated circuit memory devices are also provided.

Abstract: A NOR flash memory device configured to perform a program operation using an ISPP scheme, and comprising a plurality of memory cells, a word line voltage generator, and a scan controller is provided. A method of programming the NOR flash memory device comprising a bit scan method is also provided. The maximum number of cells that may be programmed simultaneously in the bit scan method is indicated by a scan bit number. The scan bit number may be changed by the scan controller during the program operation.

Abstract: A plurality of cells in a flash memory device are coupled together in a series configuration, as in a NAND flash memory. A position of a first accessed cell is determined with reference to a ground potential in the flash memory device. A first word line signal is coupled to the first accessed cell. The first word line signal voltage level is adjusted in response to the position of the first accessed cell in its series of cells.

Abstract: A method for programming and erasing charge-trapping memory device is provided. The method includes applying a first negative voltage to a gate causing a dynamic balance state (RESET\ERASE state). Next, a positive voltage is applied to the gate to program the device. Then, a second negative voltage is applied to the gate to restore the device to the RESET\ERASE state.

Abstract: The conductance of a first switch circuit (T1) is periodically controlled in response to an error-amplification circuit (A1) whereby electric power, stored in an inductance circuit (L1) from INPUT VOLTAGE VIN, is released, through a rectifier circuit (D1), to a memory cell array (11) for providing BIAS VOLTAGE VPP stepped up to a set voltage value. At this time, a voltage regulating section (13) acts on the error-amplification circuit (A1) of the stepped up voltage supplying section (12) in response to LOCATIONAL INFORMATION AD about a memory cell as a voltage application target of BIAS VOLTAGE VPP and COUNTER INFORMATION COUNT, and directly regulates the voltage value of BIAS VOLTAGE VPP. Even for large storage capacity devices, it is possible to supply a bias voltage stepped up with a sufficient supply capability to the memory cell array (11).

Abstract: A level shifter circuit comprises a first output MIS transistor of a first conductivity, and a second output MIS transistor of a second conductivity type having a second threshold voltage. The former has a first threshold voltage, wherein the output voltage is positively fed back to a gate terminal and the power supply voltage is applied to a first terminal to generate a first voltage at a second terminal. In the latter, the first voltage is applied to a first terminal and a second voltage is applied to a gate terminal to control conduction to generate the output voltage at a second terminal. The first and second charge type MIS transistors and the discharge MIS transistor are connected between the first terminal and gate terminal of the second output MIS transistor to charge or discharge the potential of the gate terminal of the second output MIS transistor.

Abstract: A memory device includes a number of terminals for transferring input data and output data to and from a memory array. The memory device includes an auxiliary circuit for receiving input auxiliary information associated with the input data and for generating output auxiliary information associated with the output data. The input and output auxiliary information include inverting codes, parity codes, temperature information or time delay information. The input and output auxiliary information are transferred to and from the memory device on the same terminals that the input data and the output data are transferred.

Abstract: A synchronous double-data-rate semiconductor memory device is adapted to receive write data on both the rising and falling edges of a data strobe signal derived from an externally-applied system clock. In the write path circuitry for each data pin of the device, adjustable delay elements are provided to enable the adjustment of the setup and hold times of write data applied to the data pin relative to the data strobe signal. The delays are separately adjustable for data present during the rising edge of the data strobe signal and for data present during the falling edge of the data strobe signal. The setup and hold window for write data is thus optimizable on a per-bit basis rather than a per-cycle basis. In one embodiment, a delay circuit is provided for generating delaying the rising edge data and the falling edge data by different delay intervals.

Abstract: A system and method to reduce standby currents in input buffers in an electronic device (e.g., a memory device) is disclosed. The input buffers may be activated or deactivated by the state of a chip select (CS) signal. In case of a memory device, the active and precharge standby currents in memory input buffers may be reduced by turning off the input buffers when the CS signal is in an inactive state. A memory controller may supply the CS signal to the memory device at least one clock cycle earlier than other control signals including the RAS (row address strobe) signal, the CAS (column address strobe) signal, the WE (write enable) signal, etc. A modified I/O circuit in the memory device may internally delay the CS signal by at least one clock cycle to coincide its timing with the RAS/CAS signals for normal data access operation whereas the turning on/off of the memory input buffers may be performed by the CS signal received from the memory controller on the previous cycle.

Abstract: Methods and apparatuses for disabling a bad bitline for verification operations, and for determining whether a programming operation have failed, include setting a bitline disable latch for a bad bitline, and inhibiting operation of a program latch if the bitlines is excluded or if a programming operation fails.

Abstract: A semiconductor memory device has a non-auxiliary memory cell, an auxiliary memory cell, a first driver, and a second driver. The non-auxiliary memory cell is connected to a predetermined bit line and a first word line. The auxiliary memory cell is connected to the predetermined bit line and a second word line. The first driver operates the first word line. The second driver operates the second word line when the first driver operates the first word line.

Abstract: An apparatus and method for coupling a normal bit line pair and a second bit line pair onto a desired bit line pair are described. This method comprises driving the desired bit line pair to emulate the normal bit line pair during a read cycle. Additionally, if the second bit line pair is active, the apparatus and method include overdriving the desired bit line pair with strength sufficient to overpower the normal bit line pair, such that the desired bit line pair emulates the second bit line pair. Electrical current differences in the bit line pair may be sensed by a sense amplifier to assert or negate a data output such that it emulates the desired bit line pair. The normal bit line pair may be coupled to a normal memory column and the second bit line pair may be coupled to a redundant memory column.

Abstract: Disclosed is a semiconductor memory device equipped with an on-chip comparison and latching function, including a latch circuit which receives a comparison result signal, output from a compare circuit receiving read data signals from plural data bus signals and an input data signal from outside and comparing whether or not the signals coincide with each other, to output the result of latching of the fail information based on a control signal. The latch circuit latches and outputs the fail information of a preset number bit output from the compare circuit during the time when a control signal for latching and outputting the fail information is in active state.

Abstract: Architecture to calibrate read operations in non-volatile memory devices. In one embodiment, a synchronous flash memory is disclosed. The synchronous flash memory includes a read sense amplifier, a verification sense amplifier, a switch, and an output buffer. The switch alternates electrical connection of the output buffer with the read sense amplifier and the verification sense amplifier. By measuring the distributions of voltage thresholds of erased cells versus voltage thresholds of programmed cells, differences in offsets between read state and write state of memory cells are determined. A specific margin is determined to ensure proper reads of the memory cells.

Abstract: A high-density DRAM in a MTBL method which reduces interference noise between bit lines is provided. Duplication of sense amplifiers (SA) and bit switches (BSW) in a conventional MTBL method is eliminated, and one line of sense amplifiers and bit switches (BSW/SA) is arranged between cell areas. Specifically, arrays are horizontally moved and vertically cumulated so as to reduce the areas. Bit line pairs to be connected are alternately interchanged above and below, every one horizontally aligned sense amplifier (SA) such that there is only one bit line pair connected to each sense amplifier. Bit lines of a bit line pair 11 cross at one place on the way, and from the cross, a space between the bit lines is wider. Further, bit lines of a bit line pair 16 do not cross each other, and a space between the bit lines is wider on the way.

Abstract: A dynamic RAM incorporates a plurality of dynamic memory cells, each of which comprises a MOSFET having a gate set as a select terminal, one source and drain set as input/output terminals, and the other source and drain connected to storage nodes of a capacitor, a plurality of word lines respectively connected to the select terminals of the plurality of dynamic memory cells, a plurality of complementary bit line pairs respectively connected to the input/output terminals of the plurality of dynamic memory cells, and a sense amplifier array comprising a plurality of latch circuits which respectively amplify differences in voltage between the complementary bit line pairs placed so as to extend in directions opposite to each other from each pair of input/output terminals. Power supply lines are provided in mesh form inclusive of a portion above word drivers.

Abstract: A flash cell fuse circuit includes a fuse cell array, a plurality of switch circuits and a plurality of fuse sense amplifiers. The fuse cell array outputs first signals in response to word line enable signals after a program or erase operation. The switch circuits pass one of the first signals in response to a reset signal and one of the word line enable signals. The fuse sense amplifiers each generate a fuse signal by detecting and amplifying an output signal of a corresponding switch circuit.

Abstract: During writing of fail addresses to address registers, when writing of a number of fail addresses that is greater than the number of antifuses that have been provided in advance is about to be executed, or when a storage process of a number of fail addresses that is greater than the number of antifuses that have been provided in advance is about to be executed, delivering as output an overflow signal indicating that the writing or storage operation cannot be executed and reporting to the outside that remedy of defects by antifuses is no longer possible.

Abstract: An integrated circuit apparatus includes a SRAM cell array having a plurality of memory cells formed of CMOSFET arranged lattice-like. The SRAM cell array has a pair of power line and ground line in each of 1-bit sequences. The integrated circuit apparatus also includes a detector detecting the occurrence of latch-up for each 1-bit sequence and outputting a detection signal, and a power controller controlling a power supply voltage to the power line for each 1-bit sequence. The power controller reduces a voltage to be supplied to the power line in the 1-bit sequence where latch-up is occurring down to a predetermined value according to the detection signal.

Abstract: A non-volatile semiconductor memory includes: a cell array including a plurality of memory cells arranged in a matrix; a plurality of bit lines extending in a column direction of the matrix; a sense amplifier configured to amplify data read out from the memory cells via the bit lines; a shield power supply providing a voltage to shield the bit lines; and a bit line selection circuit, configured to connect even bit lines to the shield power supply when odd bit lines are connected to the sense amplifier, and to connect the odd bit lines to the shield power supply when the even bit lines are connected to the sense amplifier.

Abstract: A word line driver is provided for accessing a DRAM cell embedded in a conventional logic process. The DRAM cell includes a p-channel access transistor coupled to a cell capacitor. The word line driver includes an n-channel transistor located in a p-well, wherein the p-well is located in a deep n-well. The deep n-well is located in a p-type substrate. A word line couples the drain of the n-channel transistor to the gate of the p-channel access transistor. A negative boosted voltage supply applies a negative boosted voltage to the p-well and the source of the n-channel transistor. The negative boosted voltage is less than ground by an amount equal to or greater than the threshold voltage of the p-channel access transistor. The deep n-well and the p-type substrate are coupled to ground. The various polarities can be reversed in another embodiment.

Abstract: There is provided a wordline enable circuit and its method for reducing power consumption by controlling a wordline select signal in a self-refresh mode. The wordline enable circuit includes a wordline control signal generating unit for outputting an untoggled wordline control signal while a unit wordline block is enabled in a self-refresh mode; a wordline enable signal generating unit for generating a wordline enable control signal, controlled by the untoggled wordline control signal and a toggled address signal, and a first to an n-th wordline enable power supply signals; and a wordline block enable unit for enabling each wordline, controlled by the wordline enable control signal and the first to the n-th wordline enable power supply signals.

Abstract: The present invention for preventing a data error by satisfying specifications of tHD and tCBPH is provided. The semiconductor memory device having an enough margin for a write/read operation includes a pre-charging block for performing a pre-charging operation based on a chip selection control signal; a write/read strobe generating block for performing a write/read operation based on the chip selection control signal and a chip selection signal; and a chip selection buffering block for generating the chip selection control signal based on the chip selection signal to control a timing of the pre-charging operation and a timing of the write/read operation.