Abstract: The invention relates to a method and a device for operating a sensor cell (1) that is used for analyzing exhaust gas. The aim of the invention is to create a method and a corresponding device which supply reliable test results in each mode of operation of a sensor, also when using advantageous pulse width-controlled regulation of the heating element (6). Said aim is achieved by correcting the potential of the reference electrode (Ref) of the sensor substantially in synchrony with the mean of the supply voltage (Vpwm) of the electrical heating element (6).

Abstract: There are measured characteristics of a jig (fixture) used to calculate and measure circuit parameters of a device under test. There is provided a jig characteristic measuring device which measures the jig characteristics of a jig 3 which includes signal lines 3a, 3b, 3c, and 3d used to connect a DUT 2 and a network analyzer 1 with each other (namely, the reflection characteristics of signal lines 3a, 3b, 3c, and 3d, and the transmission S parameters), measures the reflection coefficients of the signal lines 3a, 3b, 3c, and 3d in an open state where the DUT 2 is not connected to the signal lines 3a, 3b, 3c, and 3d, measures the reflection coefficients of the signal lines 3a, 3b, 3c, and 3d in a short-circuit state where all the signal lines 3a, 3b, 3c, and 3d are grounded, and derives the jig characteristics of the jig 3 based on these measured results.

Abstract: Disclosed is a fault isolation and measurement system that provides multiple near-field scanning isolation techniques on a common platform. The system incorporates the use of a specialized holder to supply electrical bias to internal circuit structures located within an area of a device or material. The system further uses a multi-probe assembly. Each probe is mounted to a support structure around a common reference point and is a component of a different measurement or fault isolation tool. The assembly moves such that each probe can obtain measurements from the same fixed location on the device or material. The relative positioning of the support structure and/or the holder can be changed in order to obtain measurements from multiple same fixed locations within the area. Additionally, the system uses a processor for providing layered images associated with each signal and for precisely aligning those images with design data in order to characterize, or isolate fault locations within the device or material.

Abstract: Method and system for non-destructive evaluation for a conducting structure by measuring the electrical impulse response thereof including applying a PRBS test input signal to the conducting structure, detecting an output signal from the conducting structure and processing the data to assess the condition of the conducting structure via changes in the electrical impulse response and to locate any defects along the conducting structure.

Abstract: A method and a measurement apparatus are provided for determining the transition impedance between two electrode parts of a subdivided neutral electrode used in high-frequency surgery. These makes it possible for the purely capacitive component of the transition impedance to be measured. For this purpose a resonant-frequency shift is measured, which occurs when a basic resonant circuit is expanded to an expanded resonant circuit by incorporating the two electrode parts into it in parallel. In particular, in order to determine the basic resonant frequency of the basic resonant circuit and/or the sample resonant frequency of the expanded resonant circuit, the phase shift between current and voltage is measured and the frequency is adjusted until current and voltage are in phase.

Abstract: A method is provided and includes exciting a sensor with an incident signal and generating a reflected signal by reflecting the incident signal from the sensor. The incident signal and the reflected signal interfere to form a standing wave. The method also includes processing the signals to determine a sensed parameter based upon a frequency at which the standing wave exhibits a null.

Abstract: The present invention relates to a mobile apparatus and/or system that measures the thickness at one or more locations of a surface on at least a part of a substrate and methods of using said apparatus and/or system. The mobile apparatus and/or system in one embodiment includes an apparatus and/or system having a coating thickness monitor and, optionally, an apparatus and/or system for simultaneously regulating the coating thickness applied on a substrate. In another embodiment, the apparatus and system has the ability to measure coating thickness subsequent to the coating's formation.

Abstract: A circuit configuration for inductive displacement measurement using a sensor whose inductance changes as a function of the displacement to be measured, and having an evaluation circuit to which the sensor is connected. The sensor is connected between a first operational amplifier and a series connection of a second operational amplifier and a resistor. The first operational amplifier is switchable over between two specified voltages and the second operational amplifier is operable to adjust a specified constant voltage at the connecting point between the resistor and the sensor, and the output of the second operational amplifier is connected to an input of a comparator whose other input is switchable over between two specified voltages. The output signal of the comparator effecting the switchover of these voltages and the voltages of the first operational amplifier, and is the measuring output signal of the circuit configuration at the same time.

Abstract: A wireless sensor includes at least one capacitive plate for sensing a distance relative to an object of interest within a semiconductor-processing environment. The sensor includes an internal power source and wireless communication such that distance and/or parallelism measurements effected using the capacitive plate(s) can be provided wirelessly to an external device.

Abstract: Some embodiments of the invention may operate to measure a feedback error signal change as an indication of efficiency associated with a power stage, and to select a determined power stage parameter value to increase the efficiency responsive to the feedback error signal change.

Abstract: In a traditional method for automatically obtaining high-magnification images of defects by using an electron microscope for defect-reviewing of a semiconductor wafer, high-magnification images of a voltage contrast changing part are obtained in the case of defects generating voltage contrast change, this made difficult to observe defects themselves generating voltage contrast change. In the present invention, based on energy of secondary electron to be detected, after obtaining two types of images, namely an image making voltage contrast conspicuous easily, and an image not making it easily, and acquiring a shape change area adjacent to a voltage contrast change area based on this area as a defect location, a high-magnification image can automatically be obtained.

Abstract: A vertical probe head primarily comprise a substrate, a trace layer, and a plurality of vertical probes where the substrate has a first surface, a second surface, and a plurality of device holes penetrating through the first surface and the second surface. The trace layer is formed on the first surface. Each vertical probe has a bonding end and a probing end where the bonding ends are inserted into the device holes of the substrate and are electrically connected to the trace layer and the probing ends are protruded away from the second surface of the substrate. Resins are filled into the device holes to firmly fix the vertical probes so that the vertical probes will not easily be bent nor damaged.

Abstract: An approach is provided for fabricating probe elements for probe card assemblies. Embodiments of the invention include using a reusable substrate, a reusable substrate with layered probe elements and a reusable substrate with a passive layer made of a material that does not adhere well to probe elements formed thereon. Examples of probe elements include, without limitation, a cantilever probe element, a vertically-oriented probe element, and portions of probe elements, e.g., a beam element of a cantilever probe element. Probe elements, or portions of probe elements, may be formed using any of a number of electroforming or plating processes such as, for example, plating using masking techniques, e.g., using lithographic techniques such as photolithography, stereolithography, X-ray lithography, etc.

Abstract: A probe for a dermal phase meter includes a handle with an extension that terminates with a displaceable center conductor. A replaceable tip attaches to the distal end of the extension and includes a center conductor that engages the center conductor in the extension and an outer conductor that establishes electrical connection through the extension. Substituting different replacement tips provides a probe with an articulation capability. Probe tips with a layer of a patient compatible, compressible elastomer overmolded onto the outer conductor provides insulation and minimizes the potential for irritating tissues during a measurement in an anatomical cavity.

Abstract: A probing system for use with a measurement device has a probe head substrate shaped to form dual cantilever members, a resistive element disposed on each cantilever member and connected to respective signal contact elements. Each resistive element is electrically connected to center conductors of respective probe cables, which are adapted for connection to the measurement device.

Abstract: An inverter includes a first circuit board (100) including a plurality of first conductor trace lines (102) for providing electronic connections among a plurality of electronic components disposed thereon, and a second circuit board (200) including a plurality of second conductor trace lines (202) for providing electronic connections among a plurality of electronic components disposed thereon. The second circuit board is disposed above the first circuit board, and is substantially perpendicular with and electrically connected to the first circuit board via at least one of the second conductor trace lines and at least one of the first conductor trace lines.

Abstract: Structure and methods of determining the complete location of a buried short using voltage contrast inspection are disclosed. In one embodiment, a method includes providing a test structure having a PN junction thereunder; and using the PN junction to determine the location of the buried short using voltage contrast (VC) inspection. A test structure may include a plurality of test elements each having a PN junction thereunder, wherein a location of the buried short within the test structure can be determined using the PN junction and the VC inspection. The PN junction forces a change in illumination brightness of a test element including the buried short, thus allowing determination of the complete location of a buried short.

Abstract: An apparatus for testing emissions from a packaged integrated circuit is described. The apparatus comprises an ATE for generating input stimulus to said integrated circuit, a universal PEM board. The apparatus further has an electrical connector between said ATE and said universal PEM board and means for wiring the connections from ATE leads to pin leads of said packaged integrated circuit so that the packaged integrated circuit can be biased and stimulated correctly. Jumper wires are provided to allow many to one and one to many connections; and the apparatus includes a photodetector to collect the emitted photons.

Abstract: An embodiment of the present invention is a technique to form stress sensors on a package in situ. A first array of carbon nanotubes (CNTs) aligned in a first orientation is deposited at a first location on a substrate or a die in a wafer. The first array is intercalated with polymer. The first polymer-intercalated array is covered with a protective layer. A second array of CNTs aligned in a second orientation is deposited at a second location on the substrate or the die. The second array is intercalated with polymer.

Abstract: A multilayer printed wiring board having a compact test coupon formed on each of the signal wiring layers is provided, and accurate and efficient method of characteristic impedance measurement for each signal wiring layer is realized. The test coupon is constituted by a plurality of linear parts extending parallel to each other and folded-back parts mutually connecting the linear parts. A through hole is provided for serially connecting the respective test coupons of the signal wiring layers adjoining each other. Two measuring pads, one is connected to one end of the serially connected test coupons and another is connected to the ground layer, are also provided. The measurement is performed by applying a step pulse between two measuring pads and measuring voltages of reflection waves from the serially connected test coupons.

Abstract: A device for detecting a frozen image on a liquid crystal display screen comprises at least one photoelectric cell capable of delivering a luminance signal l(t) to means (8) for processing this signal. The cell is placed facing a display area (A) of the screen. In this display area, a variable pattern is displayed at a characteristic frequency fc. The processing means are capable of detecting the characteristic frequency in the signal l(t). If this signal is not detected, they trigger a corresponding alarm.

Abstract: The present invention provides a low swing current mode logic circuit including: a current mode logic block having data inputs and outputs; a pre-charging circuit for pre-charging the outputs; a dynamic current source; an evaluation circuit for evaluating the logic block during an evaluation phase; and, a feedback path arranged between the outputs and the dynamic current source which is responsive to a difference between the outputs. The simplicity of generating the low swing, achieved by the feedback which may be implemented by only two transistors, is in contrast with the complexity introduced by some methods used by other logic styles for achieving low swing.

Abstract: A semiconductor memory device for testing whether an ODT circuit is on or off during a data read mode includes an on-die termination (ODT) circuit and an ODT state information output unit. The ODT circuit includes at least one ODT resistor. The ODT state information output unit outputs an ODT state information signal indicating whether the ODT circuit is on or off, in response to an ODT control signal during a data read mode when data is output from memory cells. With a semiconductor memory device and method capable of testing whether an ODT resistor is on or off during a data read mode, it is possible to test whether an ODT circuit is on or off during reading of data.

Abstract: A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexes with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output. The controls are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.

Abstract: A voltage level shift circuit is provided. The circuit includes an input buffer unit, a level shift unit and a voltage stabilizing capacitor. The input buffer is coupled between a first voltage source and a first ground terminal. The level shift unit is coupled between a second voltage source and a second ground terminal. An input terminal of the level shift unit is coupled to an output terminal of the input buffer unit. The voltage stabilizing capacitor is coupled between the first voltage source and the second ground terminal. When a state transition occurs in the level shift unit, the voltage stabilizing capacitor maintains a voltage difference between the output terminal of the input buffer unit and the second ground terminal.

Abstract: A complementary signal generating circuit according to an embodiment of the present invention includes: an inverting element inverting a first signal to generate a second signal; a first transistor connecting a first power supply potential and a first output terminal electrically in accordance with the first signal; a second transistor connecting the first output terminal and a second power supply potential electrically in accordance with the second signal; a third transistor connecting the first power supply potential and a second output terminal electrically in accordance with the second signal; and a fourth transistor connecting the second output terminal and the second power supply potential electrically in accordance with the first signal.

Abstract: A device includes a first combinatorial logic stage having a first input to receive a first data value, a second input to receive a bypass value and an output to provide one of a representation of the first data value or a first predetermined value based on the bypass value. The device further includes a latch stage having a first input to receive a second data value, a second input to receive the bypass value and an output to provide one of a latched representation of the second data value or a second predetermined value based on the bypass value. The device additionally includes a second combinatorial logic stage having a first input coupled to the output of the first combinatorial logic stage, a second input coupled to the output of the latch stage, and an output.

Abstract: At least one of a scanning-line drive part and a data-line drive part includes: a shift register for outputting transfer signals in sequence; a first enable supply line for supplying a plurality of series of first enable signals having a first pulse width smaller than that of the transfer signals; a second enable supply line for supplying one series of second enable signal having a second pulse width smaller than the first pulse width; and pulse-width restricting circuits for receiving input of the transfer signals, the first and the second enable signals. The pulse-width restricting circuits restricts the pulse width of the transfer signals to the first pulse width by shaping each pulse of the input transfer signals based on the individual first enable signals, and restricts the pulse width of the transfer signals to the second pulse width by shaping all the pulses of the transfer signals after restricted to the first pulse width based on the second enable signal.

Abstract: Methods are described for providing an adaptive trip point detector circuit that receives an input signal at an input signal node and generates an output signal at an output signal node, the output signal changing from a first value to a second value when the input signal exceeds a trip point reference value. In particular, the trip point reference value is adjusted to compensate for variations in process or temperature.

Abstract: A comparator based circuit with effective offset cancellation includes first and second amplifiers and an offset capacitor operatively connected to the first and second amplifiers. An offset voltage source generates an offset voltage. A first switch connects the offset voltage source to ground during a first time period. The first amplifier generates an output voltage in response to the first switch connecting the offset voltage source to ground during the first time period. A second switch connects the offset capacitor to ground during a second time period. The first switch disconnects the offset voltage source from ground during a third time period, and the second switch disconnects the offset capacitor from ground during the third time period.

Abstract: In one embodiment, the present invention includes an input buffer with a common gate amplifier having input terminals coupled to receive an incoming common mode voltage. The common gate amplifier may be configured to receive the incoming common mode voltage over a wide range of levels extending from a low end lower than a supply voltage of the input buffer to a high end exceeding the supply voltage.

Abstract: A drive circuit is provided for driving a voltage-driven semiconductor element by producing a drive signal depending upon an input signal. The drive circuit comprises an output stage and a current-suppressing circuit. The output stage includes two semiconductor elements connected in series. The voltage-driven semiconductor element is connected to a common connection point of the two semiconductor elements. The current-suppressing circuit controls one of the two semiconductor elements to provide an output current flowing through either one of the two semiconductor elements if a voltage applied to the voltage-driven semiconductor element reaches a limit level, which is in excess of a level for conducting the voltage-driven semiconductor element by a predetermined voltage.

Abstract: In one embodiment a circuit, comprises a first terminal coupled to a voltage source switchable between a first voltage level and a second voltage level, a driver comprising a first inverter, a second inverter, an output stage comprising a PFET and an NFET having source drain paths connected in series across opposite power supply terminals, the PFET and NFET each having a gate electrode that switches on and off in response to a voltage applied to the gate electrode being on opposite sides of a threshold, first pulse shaping circuitry coupled to the first inverter and the PFET and comprising a first resistor and a first capacitor, the first capacitor being connected across the gate electrode of the PFET and a first of the power supply terminals, the first capacitor comprising an NFET, and second pulse shaping circuitry coupled to the second inverter and the NFET and comprising a second resistor and a second capacitor, the second resistor being connected the gate electrode of the NFET and a first of the power su

Abstract: An initialization signal generation circuit is provided which includes a voltage divider for dividing an external voltage, generating an enable signal, and outputting the enable signal to a first node, a controller including at least one fuse, and adjusting a voltage level of the enable signal according to a cutting of the at least one fuse, and a signal generator for generating an initialization signal of a semiconductor device in response to the enable signal of the first node.

Abstract: A clock and data recovery circuit including: means for generating a first and a second clock signal; means for receiving the first clock signal and for generating a third clock signal from the first clock signal and means for receiving the second clock signal and for generating a fourth clock signal, wherein at least one of the third and the fourth clock signals differ in phase from the first and the second clock signal respectively; means for receiving the third and fourth clock signals and a serial data stream and for generating a reconstructed serial data stream and a phase error signal; means for receiving the phase error signal and for generating a phase adjustment signal and means for receiving the phase adjustment signal by the by the clock generation circuit in a feedback loop to adjust the phases of the first and second clock signals.

Abstract: A voltage-controlled oscillator, has a tank circuit that has a first inductor having one end connected to a power supply potential, a second inductor having one end connected to said power supply potential, and a first variable capacitor connected between the other end of said first inductor and the other end of said second inductor and having a capacitance controlled in accordance with an oscillation frequency controlling voltage; a first MOS transistor connected between the other end of said first inductor and a ground potential and having the gate connected to the other end of said second inductor; a second MOS transistor connected between the other end of said second inductor and said ground potential and having the gate connected to the other end of said first inductor; a third inductor having one end connected to said power supply potential; a third MOS transistor connected between the other end of said third inductor and said ground potential and having the gate connected to the gate of the first MOS t

Abstract: A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase detector, which compares the phase of the output clock signal to the phase of the input clock signal. The output clock signal is generated by a voltage controlled oscillator having a control input coupled to receive an output from the phase detector, and a frequency multiplier coupled to the output of the voltage controlled oscillator. As a result, the CLKOUT signal generated by the frequency multiplier has a relatively high frequency while the voltage controlled oscillator, by operating at a relatively low frequency, uses relatively little power.

Abstract: The object is to prevent, or at least to reduce, disturbance signals at the output of the voltage supply circuit, appearing when switching off a voltage supply circuit, in particular a data signal device appertaining to a household device, which can be connected to additional data signal devices by way of a data network, on a cut-off signal. The output voltage thereof is reduced initially to a determined minimum level, such that when a greater requirement of the output current of the current/voltage supply device, which can be controlled by a voltage output circuit, is signaled, the cut-off signal appears and the device produces an output voltage and an output current corresponding to determined output. The output voltage is reduced to the determined minimum level and it is then switched off.

Abstract: Improvement of quantization errors that arise in a delay line with finite resolution. A direct digital synthesizer (DDS), which contains a numerically controlled oscillator (NCO) and a digital-to-phase converter (DPC), is placed in the feedback loop of a phase locked loop (PLL). The DDS is used as a fractional divider of the voltage controlled oscillator (VCO) frequency, such that the reference frequency of the DDS is made variable. Alignment of the edges provided by the DDS delay line may then be adjusted. Mismatch errors in the DDS delay line are reduced by utilizing independently tunable delay elements.

Abstract: A digital-to-time converter (DTC) is provided, made from a plurality of series-connected cells. Each cell has an input interface to accept a signal, a control interface to accept a digital command, a delayed signal path, a minimum delay signal path, and an output interface. The signal path is selected in response to the command. The time delay associated with the delayed signal path of each cell can be varied, so that the plurality of series-connected cells is able to provide a large range of delay combinations. For example, if there are n series-connected cells, then the jth series-connected cell, where j varies from 1 to n, conducts the signal through 2j MOS gates in the delayed signal path. Assuming a digital control word with n bit places, the jth series-connected cell accepts the jth bit place of the control word to select a delay path.

Abstract: A first variable delay circuit delays an input signal, introduces a first delay into a first edge of the input signal, and generates a first delay signal. A second variable delay circuit delays the input signal, introduces a second delay into a second edge, and generates a second delay signal. A control circuit controls the first variable delay circuit and the second variable delay circuit such that the first delay and the second delay are identical. A generation circuit combines the first edge of the first delay signal and the second edge of the second delay signal, and generates a third delay signal.

Abstract: A method for clock synchronisation between an amplitude-modulated or phase-modulated received signal (r(t)) and a transmitted signal (s(t)) estimates the timing offset (?) between the received signal (r(t)) and the transmitted signal (s(t)) by means of a maximum-likelihood method. The maximum-likelihood method in this context is realised by an estimation filtering (S40; S140) dependent upon the transmission characteristic, a subsequent nonlinear signal-processing function (S50; S150) and an averaging filtering (S60, S100; S180, S200) The received signal (r(t)) is especially a modified vestigial-sideband-modulated received signal (rVSB?(t)). The nonlinear signal-processing function (S50; S150) maintains the alternating component in the spectrum of the pre-filtered vestigial-sideband-modulated received signal (vVSB?(t)).

Abstract: A sensor circuit has a first input terminal, a second input terminal and an output terminal, a capacitive sensor connected between the first input terminal and the output terminal, a field-effect transistor coupled to the output terminal at one of a source and a drain terminal and coupled to the second input terminal at the other one of the source and drain terminals, and a driver implemented to set a potential at a control terminal of the field-effect transistor such that in sensor operation the field-effect transistor is operated in a sub-threshold voltage range.

Abstract: Disclosed are embodiments of an apparatus incorporating a detection circuit adapted for determining the state of selected fuses and a programming circuit for blowing selected fuses on demand. Also, disclosed are embodiments of an associated method. The detection circuit comprises a plurality of fuses in identical signal and reference legs in order to increase the signal margin for detecting blown fuses and/or current sources configured to pass offset currents through the signal and reference legs in order to set the trip point for detecting blown fuses between the un-blown and the minimum blown resistances. Thus, the invention provides the flexibility of single-sided fuse state detection devices with even greater sensitivity than both single-sided and differential fuse state detection device.

Abstract: A charge pump system including a clock circuit and a charge pump circuit is provided. The clock circuit provides a first clock with a frequency based on a memory block select signal indicative of load capacitance of a charge node. The charge pump circuit receives the first clock and charges the charge node at a rate based on the frequency of the first clock and the load capacitance of the charge node. The memory block select signal indicates which of the memory blocks are coupled to the charge node and thus indicates the load capacitance of the charge node. The frequency of the first clock is adjusted based on the load capacitance of the selected block so that the slew rate of the charge node is about the same. Thus, the slew rate of the voltage ramp on the charge node is about the same regardless of the load capacitance.

Abstract: A swing width control circuit and a high voltage pumping circuit using the same are disclosed. The swing width control circuit includes a swing width controller for receiving a first pumping signal having a first swing width and generating a second pumping signal having a second swing width larger than the first swing width of the first pumping signal, in accordance with a level of a supply voltage to pump or precharge a voltage of a specific node, and a swing width holding device for maintaining a swing width of the specific node to be equal to the second swing width of the second pumping signal.

Abstract: The boosting voltage generating circuit of example embodiments may include a boosting level detection unit, a first boosting pump, and a second boosting pump. The boosting level detection unit may be configured to generate a target level detection signal and a margin level detection signal. The target level detection signal may have a logic state according to a level of a boosting voltage compared with a target voltage level, and the margin level detection signal may have a logic state according to a level of the boosting voltage compared with a margin voltage level, the margin voltage level being higher than the target voltage level. The first boosting pump may be controlled based on a target voltage level. The second boosting pump may be controlled based on a margin voltage level. According to the boosting voltage generating circuit of example embodiments, overshoot of the boosting voltage by the second boosting pump may remarkably decrease.

Abstract: A charge pump provides a programmable multiplication factor for generating an output voltage. A first output voltage may be generated by connecting a first plurality of N capacitors in a first plurality of (N+1) configurations. A second output voltage may be generated by connecting a second plurality of M capacitors in a second plurality of M+1 configurations. The first plurality of N capacitors and the second plurality of M capacitors have one or more capacitors in common. The integers M and N may be equal, although this is not required. The first plurality of configurations is different than the second plurality of configurations, thereby providing different multiplication factors for the first and second pluralities of configurations. In one embodiment, the first plurality of (N+1) configurations results in an output voltage of about ¾× an input voltage.

Abstract: A semiconductor apparatus includes a constant voltage circuit that converts an input voltage and outputs a prescribed constant voltage. The constant voltage circuit includes an output transistor that receives an input of a control signal and outputs a current (from an input terminal to an output terminal) in accordance with the control signal. Also included is an error amplifier circuit that controls the output transistor to create a voltage in proportion to an output voltage outputted from the output terminal becomes a prescribed reference level. A direct current power source supplies direct current power to the constant voltage circuit. A voltage creating circuit creates and outputs a voltage higher than that of the direct current power.

Abstract: In a receiving section, a first mixer and a second mixer generate an I signal and a Q signal from a modulated reception signal, a local signal, and a local signal obtained by shifting a phase by 90 degrees. These I signal and Q signal are supplied to a digital signal processing section via a low path filter, a capacitor, a variable gain amplifier, and an ADC. In addition, the generated I signal and Q signal are directly supplied to the digital signal processing section. The digital signal processing section detects a sign of the I signal and a sign of the Q signal, the signals being directly input. In addition, the detected sign of the I signal is multiplied with the I signal input from the ADC, and then, the detected sign of the Q signal is multiplied with the Q signal input from the ADC, whereby the signs are commonly established in a positive state. Then, the I signal and the Q signal are added, and decoded into two-values.