Abstract: An integration scheme for providing Si gates for nFET devices and SiGe gates for pFET devices on the same semiconductor substrate is provided. The integration scheme includes first providing a material stack comprising, from bottom to top, a gate dielectric, a Si film, and a hard mask on a surface of a semiconductor substrate that includes at least one nFET device region and at least one pFET device region. Next, the hard mask is selectively removed from the material stack in the at least one pFET device region thereby exposing the Si film. The exposed Si film is then converted into a SiGe film and thereafter at least one nFET device is formed in the least one nFET device region and at least one pFET device is formed in the at least one pFET device region. In accordance with the present invention, the least one nFET device includes a Si gate and the at least one pFET includes a SiGe gate.

Abstract: A field effect transistor for detecting an analyte having a thiol group includes a substrate, a source region and a drain region formed apart from each other on the substrate, the source region and the drain region being doped such that a polarity of the source and drain region is opposite to a polarity of the substrate, a channel region disposed between the source region and the drain region, an insulating layer formed of an electrically insulating material and disposed on the channel region, a gold layer disposed on the insulating layer and a reference electrode disposed apart from the gold layer.

Abstract: A transistor structure comprising an active semiconductor layer with metal source and drain contacts formed in electrical contact with the active layer. A gate contact is formed between the source and drain contacts for modulating electric fields within the active layer. A spacer layer is formed above the active layer and a conductive field plate formed above the spacer layer, extending a distance Lf from the edge of the gate contact toward the drain contact. The field plate is electrically connected to the gate contact and provides a reduction in the peak operational electric field.

Abstract: Disclosed are an improved hetero-junction bipolar transistor (HBT) structure and a method of forming the structure that incorporates a silicon-germanium emitter layer with a graded germanium profile. The graded germanium concentration creates a quasi-drift field in the neutral region of the emitter layer. This quasi-drift field induces valence bandgap grading within the emitter layer so as to accelerate movement of holes from the base layer through the emitter layer. Accelerated movement of the holes from the base layer through the emitter layer reduces emitter delay time and thereby, increases the cut-off frequency (fT) and the maximum oscillation frequency (fMAX) of the resultant HBT.

Abstract: A multi-gate transistor and a method of forming a multi-gate transistor, the multi-gate transistor including a fin having an upper portion and a lower portion. The upper portion having a first band gap and the lower portion having a second band gap with the first band gap and the second band gap designed to inhibit current flow from the upper portion to the lower portion. The multi-gate transistor further including a gate structure having sidewalls electrically coupled with said upper portion and said lower portion and a substrate positioned below the fin.

Abstract: A semiconductor device includes a plurality of repeatable circuit cells connectable to one or more conductors providing at least electrical connection to the circuit cells and/or electrical connection between one or more circuit elements in the cells. Each of the circuit cells are configured having gates and active regions forming a grating, wherein, for a given active layer in the device, a width of each active region is substantially the same relative to one another, a spacing between any two adjacent active regions is substantially the same, a width of each gate is substantially the same relative to one another, and a spacing between any two adjacent gates is substantially the same.

Abstract: Memory cells and semiconductor memory devices using the same. A substrate comprises two cross-coupled inverters and first and second pass-gate transistors formed therein, the inverters having a data storage node and a date bar storage node coupled to first terminals of the first and second pass-gate transistors. A first conductive layer is disposed on the substrate and comprises a bit line and a complementary bit line electrically connected to second terminals of the first and second pass-gate transistors respectively. A second conductive layer is disposed on the first conductive layer and comprises two first power lines covering the bit line and the complementary bit line respectively, wherein the first power lines, the bit line and the complementary bit line are parallel.

Abstract: A semiconductor integrated circuit includes a function block arranged on a substrate, a first buffering cell arranged adjacent to a first side of the function block, a second buffering cell arranged adjacent to a second side adjacent to the first side of the function block, and signal wiring passing over the function block obliquely relative to the first side and the second side, connecting the first buffering cell and the second buffering cell.

Abstract: This document discloses an organic light emitting device comprising a first electrode and a wire comprising a contact part formed on a substrate, an insulating layer formed on the first electrode and a portion of the wire, the insulating layer comprising an opening which exposes a portion of the first electrode and a contact hole which exposes an entire upper surface of the contact part, an emission layer formed in the opening, a second electrode formed on the emission layer and the upper surface of the contact part though the contact hole.

Abstract: A semiconductor device includes: a semiconductor layer made of a group-III nitride semiconductor and having a first surface and a second surface opposed to the first surface; a Schottky electrode formed on the first surface of the semiconductor layer; and an ohmic electrode electrically connected to the second surface of the semiconductor layer. The semiconductor layer has, in at least the upper portion thereof, highly-resistive regions selectively formed to have a high resistance.

Abstract: A structure is provided which includes at least one semiconductor device and a diffusion heater in a continuous active semiconductor area of a substrate. One or more semiconductor devices are provided in a first region of the active semiconductor area and a diffusion heater is disposed adjacent thereto which consists essentially of a semiconductor material included in the active semiconductor area. Conductive isolation between the first region and the diffusion heater is achieved through use of a separating gate. The separating gate overlies an intermediate region of the active semiconductor area between the first region and the diffusion heater and the separating gate is biasable to conductively isolate the first region from the diffusion heater.

Abstract: A semiconductor structure is disclosed, including a substrate having therein a first well of a first conductivity type and a second well of a second conductivity type, a first MOS transistor of the first conductivity type and a second MOS transistor of the second conductivity type. The first MOS transistor is disposed on the second well, including a gate structure on the second well and a strained layer of the first conductivity type in an opening in the second well beside the gate structure. The difference between the cell parameter of a portion of the strained layer near the bottom of the opening and that of the substrate is less than the difference between the cell parameter of a portion of the strained layer apart from the bottom of the opening and that of the substrate. The second MOS transistor is disposed on the first well.

Abstract: A semiconductor image sensor and a method for fabricating the same are described. The semiconductor image sensor includes a substrate having at least a photoactive region therein and an IR cutting layer over the photoactive region.

Abstract: Field emitter arrays with split gates and methods for operating the same. A field emitter array may include one or more pairs of split gates, each connected to a corresponding voltage source, the split gates forming at least one gate hole for at least one emitter tip. Voltages, for example, AC voltages V1 and V2 may be applied to the split gates to perform one- or two-dimensional scanning or tilting depending on a ratio of V1 and V2.

Abstract: A gas-sensitive field-effect transistor (GasFET) for the detection or measurement of an amount of hydrogen sulfide present in ambient air includes a raised gate electrode and a transistor structure. The raised gate electrode may be formed from or coated with a gas-sensitive material such as tin oxide, or silver, silver oxide or mixtures thereof. An insulator layer may be disposed on top of the transistor structure. An air gap is formed between the gas-sensitive layer of the raised gate electrode and the insulator layer on top of the transistor structure.

Abstract: A semiconductor package with contacts on both sides of the dice on a wafer scale. The back side of the wafer is attached to a metal plate. The scribe lines separating the dice expose the metal plate without extending through the metal plate. A metal layer may be formed on the front side of the dice, covering the exposed portions of the metal plate and extending to side edges of the dice. The metal layer may cover connection pads on the front side of the dice. A second set of scribe lines are made coincident with the first set. Therefore, the metal layer remains on the side edges of the dice coupling the front and the back. As a result, the package is rugged and provides a low-resistance electrical connection between the back and front sides of the dice.

Abstract: Field effect transistors having a power density of greater than 40 W/mm when operated at a frequency of at least 4 GHz are provided. The power density of at least 40 W/mm may be provided at a drain voltage of 135 V. Transistors with greater than 60% PAE and a power density of at least 5 W/mm when operated at 10 GHz at drain biases from 28 V to 48 V are also provided.

Abstract: Source strap cells which are manufactured in a very similar way to conventional memory cells may be utilized to enable connections to the source of a memory cell. In other words, the source and the drain may be contacted by vias which are arranged identically in some embodiments. This may result in greater symmetry, reduced die size, and greater manufacturing efficiencies in some embodiments.

Abstract: A thin film transistor includes a metal substrate, a first conductive barrier layer placed on the metal substrate to prevent diffusion of substance of the metal substrate, a protective insulating film placed on the first conductive barrier layer, a semiconductor layer placed on the protective insulating film and including a source region, a drain region and a channel region, a gate insulating film placed on the semiconductor layer, and a gate electrode placed above the semiconductor layer with the gate insulating film interposed therebetween. The first conductive barrier layer and the semiconductor layer are electrically connected through a first opening of the protective insulating film.

Abstract: A semiconductor device includes: a substrate; a first junction region and a second junction region formed separately from each other in the substrate; an etch barrier layer formed in the substrate underneath the first junction region; and a plurality of recess channels formed in the substrate between the first junction region and the second junction region.

Abstract: A lateral DMOS-transistor is provided that includes a MOS-diode made of a semi-conductor material of a first type of conductivity, a source-area of a second type of conductivity and a drain-area of a second type of conductivity which is separated from the MOS-diode by a drift region made of a semi-conductor material of a second type of conductivity which is at least partially covered by a dielectric gate layer which also covers the semi-conductor material of the MOS-diode. The dielectric gate-layer comprises a first region of a first thickness and a second region of a second thickness. The first region covers the semi-conductor material of the MOS-diode and the second region is arranged on the drift region. A transition takes place from the first thickness to the second thickness such that an edge area of the drift region which is oriented towards the MOS-diode is arranged below the second area of the gate layer. The invention also relates to a method for the production of these types of DMOS-transistors.

Abstract: An imaging circuit, an imaging sensor, and a method of imaging. The imaging cell circuit including one or more imaging cell circuits, each imaging cell circuit comprising: a transistor having a floating body for holding charge generated in the floating body in response to exposure of the floating body to electromagnetic radiation; means for biasing the transistor wherein an output of the transistor is responsive to the electromagnetic radiation; and means for selectively connecting the floating body to a reset voltage supply.

Abstract: P type semiconductor well regions 8 and 9 for device separation are provided in an upper and lower two layer structure in conformity with the position of a high sensitivity type photodiode PD, and the first P type semiconductor well region 8 at the upper layer is provided in the state of being closer to the pixel side than an end portion of a LOCOS layer 1A, for limiting a dark current generated at the end portion of the LOCOS layer 1A. In addition, the second P type semiconductor well region 9 at the lower layer is formed in a narrow region receding from the photodiode PD, so that the depletion layer of the photodiode PD is prevented from being obstructed, and the depletion is secured in a sufficiently broad region, whereby enhancement of the sensitivity of the photodiode PD can be achieved.

Abstract: To securely prevent hydrogen from entering a ferroelectric layer of a ferroelectric memory. A first hydrogen barrier layer 5 is formed on the lower side of ferroelectric capacitors 7. Upper surfaces and side surfaces of the ferroelectric capacitors 7 are covered by a second hydrogen barrier layer. All upper electrodes 7c of the plural ferroelectric capacitors 7 to be connected to a common plate line P are connected to one another by an upper wiring layer 91. The upper wiring layer 91 is connected to the plate line P through a lower wiring 32 provided below the ferroelectric capacitors 7. A third hydrogen barrier layer 92 is formed on the upper wiring layer 91 such that all edge sections 92a of the third hydrogen barrier layer 92 come in contact with the first hydrogen barrier layer 5.

Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The bottom portions can have substantially vertical sidewalls, and can join to the upper portions at steps which extend substantially perpendicularly from the sidewalls. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.

Abstract: A switching circuit configured for controlling static power consumption in integrated circuits includes a plurality of three-terminal, phase change material (PCM) switching devices connected between a voltage supply terminal and a corresponding sub-block of integrated circuit logic. Each of the PCM switching devices further includes a PCM disposed in contact between a first terminal and a second terminal, a heating device disposed in contact between the second terminal and a third terminal, the heating device positioned proximate the PCM, and configured to switch the conductivity of a transformable portion of the PCM between a lower resistance crystalline state and a higher resistance amorphous state; and an insulating layer configured to electrically isolate the heater from said PCM material, and the heater from the first terminal.

Abstract: A semiconductor device is fabricating using a photoresist mask pattern, and selectively removing portions of a liner nitride layer in a cell region and a peripheral circuit region. A modified FinFET is formed to reduce the influence of signals transmitted by adjacent gate lines in a cell region. A double FinFET and a substantially planar MOSFET are formed in a core region and in a peripheral region, respectively, concurrently with the formation of the modified FinFET.

Abstract: A storage capacitor, particularly for use in a storage cell, exhibits two storage electrodes and a dielectric arranged between the two storage electrodes, an intermediate layer essentially consisting of carbon.

Abstract: A capacitor device having a three-dimensional structure includes: a lower electrode formed on a semiconductor substrate to have a three-dimensional shape; a capacitor insulating film formed to cover the lower electrode and made of a ferroelectric material; and an upper electrode formed on the capacitor insulating film to have a step portion. A stress control layer is formed on the upper electrode to cause tensile stress and function as a moisture diffusion barrier.

Abstract: A poly-insulator-poly (PIP) capacitor includes a first polysilicon plate; a first capacitor dielectric layer disposed on the first polysilicon plate; a second polysilicon plate stacked on the first capacitor dielectric layer, wherein the first polysilicon plate, the first capacitor dielectric layer, and the second polysilicon plate constitute a lower capacitor; a second capacitor dielectric layer disposed on the second polysilicon plate; and a third polysilicon plate stacked on the second capacitor dielectric layer, wherein the second polysilicon plate, the second capacitor dielectric layer, and the third polysilicon plate constitute an upper capacitor. Preferably, the first polysilicon plate and the third polysilicon plate are electrically connected to a first terminal of the PIP capacitor, while the second polysilicon plate is electrically connected to a second terminal of the PIP capacitor.

Abstract: Techniques for manufacturing an electronic device. In certain embodiments, a substrate includes a lower patterned layer that has a target conductor. A hybrid-vertical contact may be disposed directly on the target conductor. The hybrid vertical contact may include a lower-vertical contact directly on the target conductor and an upper-vertical contact directly on the lower-vertical contact. The upper-vertical contact may have an upper width that is greater than a lower width of the lower-vertical contact.

Abstract: A semiconductor device having superior capacitance may include interconnections formed on a semiconductor substrate, an interlayer insulation layer on the interconnections and having vias exposing a portion of the top surface of the interconnections, a capacitor which may be on the interlayer insulation layer and having a bottom electrode, a dielectric layer pattern, and a top electrode which may be sequentially stacked, and a pad structure may be connected to the interconnections through the vias. The pad structure may include pads for bonding with external electronic devices and a first upper interconnection connected to the top electrode of the capacitor.

Abstract: A display device and a method of fabricating the same, the display device including a first substrate having a display region, a light emitting layer disposed within the display region, a first voltage pad disposed outside the display region, on the first substrate outside of the display region and supplying a predetermined voltage to the display region, a second substrate provided above the first substrate and corresponding to the display region, a second voltage pad disposed on a surface of the first or second substrate provided opposite to a direction of light emitted from the light emitting layer and a flexible film electrically connecting the first voltage pad and the second voltage pad.

Abstract: A DRAM cell in a substrate has a deep trench (DT) extending from a surface of the substrate into the substrate, a word line (WL) formed on the surface of the substrate adjacent the deep trench, and oxide (TTO) disposed in a top portion of the trench and extending beyond the trench in the direction of the word line. In this manner, when silicided, there is oxide rather than silicon on the surface of the substrate in a gap between the word line (WL) and a passing word line (PWL) disposed above the deep trench.

Abstract: It is an object to provide a nonvolatile semiconductor memory device having excellent writing property and charge-retention property. A semiconductor layer including a channel forming region between a pair of impurity regions which are formed to be apart from each other is provided. In an upper layer portion thereof, a first insulating layer, a floating gate, a second insulating layer, and a control gate are provided. The floating gate has at least a two-layer structure, and a first layer in contact with the first insulating layer preferably has a band gap smaller than that of the semiconductor layer. Furthermore, by setting an energy level at the bottom of the conduction band of the floating gate lower than that of the channel forming region of the semiconductor layer, injectability of carriers and a charge-retention property can be improved.

Abstract: A nonvolatile semiconductor memory device which is superior in writing property and charge holding property, including a semiconductor substrate in which a channel formation region is formed between a pair of impurity regions, and a first insulating layer, a floating gate, a second insulating layer, and a control gate over the semiconductor substrate. The floating gate includes at least two layers. It is preferable that a band gap of a first layer included in the floating gate, which is in contact with the first insulating layer, be smaller than that of the semiconductor substrate. For example, it is preferable that the band gap of the semiconductor material for forming the floating gate be smaller than that of the channel formation region in the semiconductor substrate by 0.1 eV or more.

Abstract: According to an aspect of the embodiment, there is provided a ferroelectric storage device including: a plurality of memory cells repeatedly arranged in a predetermined direction, each memory cell including a ferroelectric film divided for each memory cell; and a word line formed on the ferroelectric film and shared by the plurality of memory cells.

Abstract: A p-type doped nanowire and a method of fabricating the same. The nanowire has a p-type doped portion which is formed by chemically binding a radical having a half-occupied outermost orbital shell to the corresponding portion of the nanowire, which corresponding portion of the nanowire donates an electron to the radical to thereby form the p-type doped portion.

Abstract: The present invention is a method, and resulting device, for fabricating memory cells with an extremely small area. The small area requirement is met due primarily to two significant factors. First, a judicious use of spacers allows a control gate/wordline or select line to be fabricated in extremely close proximity to an associated plurality of floating gates. Additionally, each of the plurality of floating gates is supplied with a majority carrier (e.g., electrons) through a charge injector. Each of the plurality of injector regions is made by doping a localized area (e.g., through injector ion implantation) creating a subsurface highly-doped region that is setup to receive bias from a nearby contact for charge generation, i.e., a tunneling injector.

Abstract: The present invention relates generally to semiconductors, and more specifically to semiconductor memory device structures and an improved fabrication process for making the same. The improved fabrication process allows the self-aligned contacts and local interconnects to the processed simultaneously. The process allows the minimal distance requirement between the self-aligned contacts and the local interconnects to be widened, which makes the patterning of self-aligned contacts and local interconnects easier. The widened minimal distance requirement also allows further memory cell shrinkage. The improved structures of self-aligned contacts and local interconnects also have excellent isolation characteristic.

Abstract: A semiconductor memory device includes a semiconductor substrate, an isolation insulation film filled in a plurality of trenches formed in the semiconductor substrate to define a plurality of element formation regions, a floating gate of polysilicon provided on each of the element formation regions through a first insulation film, a second insulation film, provided on the floating gate, containing a metal element, a control gate of polysilicon, provided on the second insulation film, and source/drain regions provided in the semiconductor substrate, both a polysilicon conductive layer containing a metal element and a mutual diffusion layer composed of a silicate layer of a mixed oxide material composed of a silicon element contained in the floating gate and the control gate and a metal element contained in the second insulation film are provided on a surface of each of the floating gate and the control gate, respectively.

Abstract: A non-volatile memory device and a method of manufacturing the same, in which the program speed can be enhanced and the interference phenomenon can be reduced. The non-volatile memory device includes a semiconductor substrate having an active region defined by isolation layers arranged in one direction, a control gate arranged vertically to the direction in which the isolation layers are arranged, a floating gate formed on the active region below the control gate and having a lateral curve so that the floating gate has a width narrowed upwardly, a gate insulating layer formed between the floating gate and the semiconductor substrate, and a dielectric layer formed between the floating gate and the control gate.

Abstract: A structure and method of forming a body contact for an semiconductor-on-insulator trench device. The method including: forming set of mandrels on a top surface of a substrate, each mandrel of the set of mandrels arranged on a different corner of a polygon and extending above the top surface of the substrate, a number of mandrels in the set of mandrels equal to a number of corners of the polygon; forming sidewall spacers on sidewalls of each mandrel of the set of mandrels, sidewalls spacers of each adjacent pair of mandrels merging with each other and forming a unbroken wall defining an opening in an interior region of the polygon, a region of the substrate exposed in the opening; etching a contact trench in the substrate in the opening; and filling the contact trench with an electrically conductive material to form the contact.

Abstract: An example embodiment of a strained channel transistor structure comprises the following: a strained channel region comprising a first semiconductor material with a first natural lattice constant; a gate dielectric layer overlying the strained channel region; a gate electrode overlying the gate dielectric layer; and a source region and drain region oppositely adjacent to the strained channel region, one or both of the source region and drain region are comprised of a stressor region comprised of a second semiconductor material with a second natural lattice constant different from the first natural lattice constant; the stressor region has a graded concentration of a dopant impurity and/or of a stress inducing molecule. Another example embodiment is a process to form the graded impurity or stress inducing molecule stressor embedded S/D region, whereby the location/profile of the S/D stressor is not defined by the recess depth/profile.

Abstract: A display apparatus includes a switching element having a first gate electrode, a source and drain electrode, a channel area formed between the source and drain electrode, and a second gate electrode. The second gate electrode is electrically insulated from the first gate electrode through the channel area, and different control voltages are applied to the second gate electrode according to the control period of the first gate electrode. The different control voltages are applied to the second gate electrode according to the turn on/off states of the switching element for increasing the turn on current in the channel area and for minimizing the turn off (leakage) current in the channel area.

Abstract: The SOI lateral semiconductor device includes a semiconductor region of a first conductivity type, a buried oxide film layer in the semiconductor region, a thin active layer on the buried oxide film layer, an anode region in the thin active layer, and a drain layer contacting the buried oxide film layer for confining the minority carriers injected from the anode region to the thin active layer within the thin active layer and for forming a structure that sustains a high breakdown voltage. The SOI lateral semiconductor device can provide a high breakdown voltage and low switching losses using the thin buried oxide film, which can be formed by an implanted oxygen (SIMOX) method.

Abstract: An exemplary TFT array substrate (200) includes a glass substrate (201); a source electrode (215), a channel (212), and a drain electrode (216) formed on the substrate, the channel being between the source electrode and the drain electrode; a gate insulating layer (203) formed on the channel; a gate electrode (214) formed on the gate insulating layer, and corresponding to the channel; and a passivation layer (206) formed on the source electrode, the drain electrode, the passivation layer having a dielectric constant less than that of the gate insulating layer. A width of the gate insulating layer is less than a corresponding width of each of the gate electrode and the channel, and portions of the passivation layer are located adjacent the gate insulating layer between the gate electrode and the channel.

Abstract: An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FETs. The SOI FETs may include Partially Depleted SOI (PD-SOI) FETs and Fully Depleted SOI (FD-SOI) FETs and the chip may include bulk FETs as well. The FETs are formed by contouring the surface of a wafer, conformally implanting oxygen to a uniform depth, and planarizing to remove the Buried OXide (BOX) in bulk FET regions.

Abstract: Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.

Abstract: An integrated circuit device that includes a semiconductor substrate, a well region formed inside the semiconductor substrate, a first isolation structure formed inside the well region, a second isolation structure formed inside the well region and spaced apart from the first isolation structure, a dielectric layer formed over the well region, and a layer of silicon, formed over the dielectric layer, including a p-type portion, an n-type portion and a center portion disposed between the p-type and n-type portions.