Abstract: A supply voltage sensing circuit comprises an internal power supply circuit, which provides a constant output voltage regardless of the supply voltage. A delay circuit generates a delayed signal by delaying a variation in the output voltage. A divider circuit generates a divided voltage by dividing the supply voltage at a certain division ratio. A p-type MOS transistor has a source given the delayed signal and a gate given the divided voltage and turns on when the supply voltage lowers below a certain value. An output circuit provides an output voltage based on a drain voltage on the p-type MOS transistor.

Abstract: In a circuit arrangement including a sample-and-hold device, the sample-and-hold device includes a first, a second, a third and a fourth charge store, and also a first and a second input terminal for feeding in a differential input signal comprising a first and a second component. A differential output signal is output via a first and a second output terminal. The charge stores are charged with the first or the second component of the differential input signal in a first phase of a time segment. In a second phase of the time segment, the differential output signal is generated in a manner dependent on the charges of the first, second, third and fourth charge stores.

Abstract: An output driver for an integrated circuit that asserts at very low power supply voltages includes a first input voltage node, a first power supply voltage node, an output voltage node, a first internal circuit node, a first resistive element coupled between the first power supply voltage node and the first internal node, a first transistor having a gate coupled to first input voltage node, a drain coupled to the first power supply voltage node, and a source coupled to ground, a second transistor having a gate coupled to the first internal circuit node, a drain coupled to the output voltage node, and a source coupled to ground, and a third transistor having a gate coupled to the first internal circuit node, a drain coupled to the output voltage node, and a source coupled to ground, wherein the first and second transistors have a first Vt threshold voltage, and the third transistor has a second Vt threshold voltage lower than the first threshold voltage.

Abstract: A contention-free keeper circuit including a keeper circuit having a first node and a second node, is provided. The contention-free keeper circuit may further include a delay element for providing time delay. The contention-free keeper circuit may further include a high-to-low contention element coupled between the first node and a first supply, and coupled to the delay element output. The contention-free keeper circuit may further include a low-to-high contention elimination element coupled between the first node and a second supply, and coupled to the delay element output, (i) wherein responsive to a low-to-high transition at the first node and the time delay, the low-to-high contention elimination element eliminates a low-to-high contention within the keeper circuit, and (ii) wherein responsive to a high-to-low signal transition at the first node and the time delay, the high-to-low contention elimination element eliminates a high-to-low contention within the keeper circuit.

Abstract: A frequency dividing phase shift circuit includes a first frequency divider and a second frequency divider. The first frequency divider is configured to perform 1/(2n+1) (n is a natural number) frequency division on an input signal having a frequency of (freq*2(2n+1)) (“freq” indicates a frequency) to generate a first signal having a frequency of (freq*2). The second frequency divider is configured to perform ½ frequency division on the first signal to generate 4-phase signals which are different in phase by 90 degrees one after another.

Abstract: A power-on reset circuit has a dummy flip-flop in addition to a setting flip-flop. Even if resetting is not performed by a power-on reset signal at power-on, output from the dummy flip-flop is used to perform resetting and initialization.

Abstract: An apparatus and method for extracting a maximum pulse width of a pulse width limiter are provided. The apparatus and method of the illustrative embodiments performs such extraction using a circuit that is configured to eliminate the majority of the delay cells utilized in the circuit arrangement described in commonly assigned and co-pending U.S. patent application Ser. No. 11/109,090 (hereafter referred to as the '090 application). The elimination of these delay cells is made possible in one illustrative embodiment by replacing an OR gate in the circuit configuration of the '090 application with an edge triggered re-settable latch. The replacement of the OR gate with the edge triggered re-settable latch reduces the amount of chip area used in addition to the power consumption of the circuit.

Abstract: The inventive technique can dynamically adjust the current being applied within the components of a prescaler or divider. This dynamic scaling of the current can improve the speed of the divider by a factor of two or reduce the average current in half when compared to the conventional prescaler. Inverters are used to directly adjust the dynamic value of the currents. The removal of the conventional NMOS device within the conventional circuit eliminates one gate delay in the CML prescaler. Second, the inventive prescaler circuits operate under a current injection/extraction technique. A group of small matched inverters can be used to drive each current switching circuit independently within the entire prescaler as compared to a large buffer driving the entire conventional prescaler. Finally, dynamic current scaling offers the designer additional flexibility in the design trade off between the maximum current applied to the load and achieving the maximum performance.

Abstract: A threshold personalization circuit for a reset or supervisor chip includes personalization fuses, which shift a resistor divider to provide a variety of selectable voltage thresholds. The personalization fuses may provide hundreds of millivolts of adjustment. The threshold personalization circuit further includes trim fuses to fine tune the threshold to within a few millivolts of the target threshold voltage. The threshold personalization circuit includes a test mode to cycle through to a particular personalization trim, such that at prelaser testing the personalized value is found (the fuse blow for personalization is emulated) and then the trim fuse amount can be based on the actual final personalized voltage. This results in very accurate threshold voltages for all personalized values.

Abstract: In a method and system for providing a digitally programmable delay, a variable gain circuit is operable to receive an input. The input is multiplied by a selectable gain to provide an output. A controller is coupled to receive an input vector. The controller selects the selectable gain in response to the input vector. A delay circuit is operable to receive a signal input and provide a delayed signal output, where the delay is controlled by the output having the selectable gain. The delay circuit provides the delayed signal output having a substantially linear time delay as a function of the input vector.

Abstract: An exemplary clock-pulse generator (60) includes an input port (63), an output port (64), a logic gate (601) having two inputs (602 and 603) and an output (604), an odd number of inverters (606) connected in series between the input port and one of the inputs of the logic gate, an even number of inverters (607 and 608) connected in series between the input port and the other input of the logic gate, and an inverter (605) connected between the output of the logic gate and the output port. The present invention also provides a shift register (6) using the clock-pulse generator.

Abstract: The invention relates to a current controlled level shifter which has an input stage having an input for supplying an input signal and having first and second outputs for providing a first and a second control current. A first shifter stage is connected to the outputs of the input stage and is designed to produce an output signal which is dependent on the first and second control currents. A feedback path is designed to provide at least one feedback signal which is dependent on the output signal and to supply it to the input stage. The input stage is designed to compare the input signal with the at least one feedback signal and to set the amplitudes of the control currents on the basis of this comparison.

Abstract: A voltage level shift circuit includes a first stage which receives an input signal having voltage levels Vcc and Vss, where Vcc>Vss, and which outputs complementary first and second intermediate signals, wherein the complementary first and second intermediate signals have voltage levels VIhigh and VIlow, where VIhigh>VIlow; and a second stage which receives the first and second intermediate signals, and which outputs complementary first and second output signals, wherein the complementary first and second output signals have voltage levels VOhigh and VOlow, where VOhigh>VOlow, wherein VIhigh>VOhigh or VIlow<VOlow, and wherein VOhigh>Vcc and VOlow<Vss.

Abstract: Setting a reference voltage for a bus agent including identifying a present configuration of a bus, the bus including conductive pathways connected to bus agents, the bus agents including computer hardware devices that use the bus for data communications among bus agents, the present configuration of the bus including the identity of the bus, the identities of one or more bus agents presently connected to the bus, and the order in which the bus agents presently are connected to the bus; identifying a reference voltage value for each bus agent; and applying a reference voltage to each bus agents in dependence upon the identified reference voltage value for each bus agent.

Abstract: A switch circuit to control a high voltage source is presented. It includes a JFET transistor, a resistive device, a first transistor and a second transistor. The JFET transistor is coupled to the high voltage source. The first transistor is connected in serial with the JFET transistor to output a voltage in response to the high voltage source. The second transistor is coupled to control the first transistor and the JFET transistor in response to a control signal. The resistive device is coupled to the JFET transistor and the first transistor to provide a bias voltage to turn on the JFET transistor and the first transistor when the second transistor is turned off. Once the second transistor is turned on, the first transistor is turned off and the JFET transistor is negative biased.

Abstract: A system and method for distributing a reference voltage in a system such as an integrated circuit wherein a master reference voltage is distributed via a differential pair of conductors Local reference voltage generators produce local reference voltages proportional to the master reference voltage, but referred to local ground and/or a local power supply voltage.

Abstract: This disclosure concerns a semiconductor integrated circuit that includes a semiconductor substrate, a plurality of well regions formed on one surface of the semiconductor substrate and electrically isolated from each other, a plurality of MOS transistors formed in the well regions and a substrate bias generator that applies substrate biases to the individual well regions based on actually measured process-derived variance of the MOS transistors in threshold voltage to bring the threshold voltages of the respective MOS transistors into conformity with a normal threshold voltage.

Abstract: A semiconductor integrated circuit device includes: a first bias generating circuit, a second bias generating circuit and a control circuit. The first bias generating circuit generates a first substrate bias voltage of a P-channel transistor. The second bias generating circuit generates a second substrate bias voltage of N-channel transistor. The control circuit controls the first bias generating circuit and the second bias generating circuit independently on the basis of operating states of circuits to which the first substrate bias voltage and the second substrate bias voltage are applied.

Abstract: The internal voltage generator includes a level detector for comparing an internal voltage with a reference voltage to output a level detecting signal; a pump controller for outputting a pump enable signal in response to a mode signal and the level detecting signal; and a voltage pump for generating the internal voltage in response to the pump enable signal.

Abstract: An apparatus for supplying a glitch-free, regulated voltage at a voltage output includes a main transistor, which is connected between an intermediate potential and the voltage output, a bypass transistor, which is connected between a supply potential and the voltage output, the intermediate potential being lower than the supply potential and the intermediate potential and the supply potential being derived from a common voltage source, a regulation circuit for applying a main control potential to the main transistor, in order to regulate a voltage at the voltage output to a desired voltage, and a control circuit for generating a bypass control potential as a function of the supply potential and the main control potential, and to apply the bypass control potential to the bypass transistor.

Abstract: An active bandpass filter is disclosed herein. The active bandpass filter has N transmission lines, N negative resistant circuits, a DC circuit, and at least (N?1) coupling circuit. Each transmission line has a first end and a second end. Each negative resistant circuit has a third end and a fourth end and is electrically coupled with a related transmission line, wherein the third end and the fourth end are electrically coupled with the first end and second end, respectively. The DC circuit provides a bias voltage for N negative resistant circuits, wherein the DC circuit electrically couples with N transmission lines via N coupling elements. Each coupling circuit has a fifth end and a sixth end and is electrically coupled with any two transmission lines, wherein the fifth end and sixth end are electrically coupled with the second end and the first end, respectively.

Abstract: A two-step tuning process for resistors and capacitors in an integrated circuit is described. In the first step of the tuning process, an on-chip adjustable resistor is tuned based on an external resistor to obtain a tuned resistor. The value of the tuned resistor is accurate to within a target percentage determined by the external resistor and the design of the adjustable resistor. In the second step, an adjustable capacitor is tuned based on the tuned resistor and an accurate clock to obtain a tuned capacitor having an accurate value. The adjustable capacitor may be tuned such that an RC time constant for the tuned resistor and the tune capacitor is accurate to within a target percentage determined by the accurate clock and the design of the adjustable capacitor. The resistors and capacitors of other circuits on the integrated circuit may be adjusted based on the tuned resistor and the tuned capacitor, respectively.

Abstract: A circuit including two operational amplifiers connected in parallel. For the purpose of this explanation, assume that an equivalent input noise of a circuit with one operational amplifier is too high. Where two operational amplifiers, are connected in parallel, the signals from the operational amplifiers add as currents at the output node of the parallel combination.

Abstract: A circuit for optimizing charging of a bootstrap capacitor connected to a high side floating supply voltage at a first terminal and to a switched node voltage at a second terminal, the circuit for optimizing being included in a gate driver circuit having a high- and a low-side driver circuits for driving high- and low-side switches connected at a switched node in a half bridge to provide current to a load, the high-side driver circuit receiving a first control voltage referenced to a first level and a low-side driver circuit receiving a second control voltage referenced to a second level, the bootstrap capacitor providing supply voltage for the high-side driver circuit.

Abstract: There is provided a calibration apparatus for calibrating an electronic device that outputs a demodulation signal in which a modulated component of a signal to be tested or evaluated is demodulated, having a DC component detecting section for detecting a DC component of the demodulation signal, a gain calculating section for calculating a gain in the electronic device based on the DC component of the demodulation signal and a calibrating section for calibrating the electronic device based on the gain in the electronic device.

Abstract: An amplifying circuit includes an input chopping circuit, an amplifier, and an output chopping circuit. The input chopping circuit is operably coupled to chop an input signal at a chopping rate to produce a chopped input signal. The amplifier has a first input transistor section, a second input transistor section, and a transistor load section. The first and second input transistor sections are operably coupled to receive the chopped input signal, wherein the first input transistor section amplifies the chopped input signal when the chopped input signal is in first signal level range, the second input transistor section amplifies the chopped input signal when the chopped input signal is in a second signal level range, and the first and second input transistor sections amplify the chopped input signal when the chopped input signal is in a third signal level range, wherein the transistor load section is coupled to the first and second input transistors sections to produce an amplified chopped signal.

Abstract: A pulse modulation type electric power amplifier includes a pulse modulator that receives as input a clock and an input signal, and converts the input signal to a pulse train, an output control circuit that receives as input the pulse train output by the pulse modulator, and controls output of the pulse train, an output circuit that performs switching according to the pulse train output by the output control circuit, a comparator that converts an output terminal voltage of the output circuit to a high or a low digital value, and a short-circuit determination circuit that determines whether an output short circuit has occurred based on a state of an output signal of the comparator, and outputs an output prohibition signal to the output control circuit when an output short circuit is detected. The output control circuit controls output of the pulse train when the output prohibition signal is input, so that the output circuit stops the switching operation.

Abstract: The invention relates to a switching converter for generating an output voltage (Vout) from an input voltage (vin), comprising: a control arrangement (30) for furnishing a control signal (Serr) dependent on the output voltage (Vout); a first converter stage (1A) and at least one second converter stage (1B, 1C), each of which has: an inductive storage element (11A, 11B, 11C), a current measurement arrangement (12A, 12B, 12C) which is designed to detect a current (IL1, IL2, IL3) across the inductive storage element (11A, 11B, 11C) and to furnish a current measuring signal (Is1, Is2, Is3) proportional to this current, a pulse width modulator (16A, 16B, 16C) which receives the control signal (Serr) and the current measuring signal (Is1, Is2, Is3) and which furnishes a pulse width modulated signal (PWM1, PWM2, PWM3), and a driver circuit which receives the pulse width modulated signal (PWM1, PWM2, PWM3) and the input voltage (Vin) and which applies the input voltage (Vin) in dependence on the pulse width modulat

Abstract: An apparatus for amplifying differential signals is provided. The apparatus comprises a differential amplifier, a first impedance component, a second impedance component, a voltage source and a high-pass filter. The differential amplifier receives an input differential signal with a first terminal and a second terminal. The differential amplifier also drains currents from the voltage source into a third terminal and a fourth terminal via the first and the second impedance components respectively. The high-pass filter receives the input differential signal and outputs a control differential signal to control the first and the second impedance components so that the impedance of the first and the second impedance components vary inversely in response to the voltages at the first and the second terminals respectively when the state of the input differential signal changes.

Abstract: Disclosed are a multi-level differential amplifier that includes first to third input terminals; an output terminal; first to third differential pairs; a current source circuit for supplying currents to the respective first to mth differential pairs; a load circuit connected to first and second nodes to which first and second outputs of each of output pairs of the first to third differential pairs are connected in common; an amplifier stage receiving a signal from at least one node of the first and second nodes as an input and having its output connected to the output terminal; and a capacitance element. A data output period includes first and second periods.

Abstract: An amplifier circuit is provided with a control section that respectively selectively supplies either a second voltage or a third voltage to gates of a plurality of second transistors and gates of a plurality of third transistors by respectively switching the connection states of a plurality of first switching elements and a plurality of second switching elements to their first input terminal sides or to their second input terminal sides.

Abstract: Various source follower circuits and methods for implementing such are disclosed. As one example, a class AB source follower circuit is disclosed that includes a source follower circuit that is actively biased. The dynamic biasing allows the source follower circuit to sustainably sink a DC current. In some instances of the embodiments, the class AB source follower circuits are operable to source and sink both AC and DC currents.

Abstract: A method and apparatus is provided for dynamically changing the biasing conditions of a voltage regulator to overcome the problems caused by various conditions. The invention includes a detector and a bias control circuit for applying bias current to the voltage regulator to compensate for a detected condition.

Abstract: To provide a high-frequency power amplifier capable of improving the linearity and efficiency of a high-frequency power amplifier by stabilizing, at high frequencies, the bias voltage of a bias circuit featuring the temperature compensating effect of a high-frequency amplifying transistor, a capacitor 61 is connected between the base of a bias supply transistor 41 and a reference potential. It is thus possible to possible to suppress variations in the base voltage of the bias supply transistor 41 in particular when the high-frequency power amplifier is at high output and improve the linearity of the high-frequency power amplifier.

Abstract: A new Class L amplifier which dynamically switches between multiple pairs of power rails, and has the ability to select the most advantageous combination of rails for the minimization of power dissipation in the amplifier. A bridged amplifier system using two Class L amplifiers to drive a load.

Abstract: An RF power amplification system having a power amplifier, a matching network, and an antenna power controller which compares a voltage at the matching network output to a voltage at the matching network input and uses a result of that comparison to manipulate the power amplifier and/or the matching network, to control the power applied to the antenna. In one embodiment, the power controller tristates one or more of a plurality of parallel power amplifier devices in the amplifier, to control the antenna power. In another embodiment, the power controller manipulates a plurality of parallel resistors or other impedances in the power amplifier, switching some impedances in and some impedances out, to maximize the power coupling to the antenna or to operate the amplifier device in a maximally efficient operating range.

Abstract: Disclosed are an apparatus and a method for preventing the degradation of RF performance due to a change in impedance of an antenna in a mobile communication terminal. The mobile communication terminal includes a plurality of impedance matching circuits and a controller of the mobile communication terminal is adapted to measure the reflection voltage of the antenna, select one impedance matching circuit corresponding to the measured reflection voltage, and connected with the antenna through the selected impedance matching circuit As a result, when the impedance value of the antenna is changed, it is possible to prevent the degradation of performance of the RF module of the mobile communication terminal by using an impedance matching circuit, which can optimize the reflection loss caused by the reflection voltage of the antenna according to a change in impedance value.

Abstract: A level converter level-converts an oscillation output signal of a reference frequency oscillator and supplies the level-converted signal to a phase comparator of a PLL/fractional synthesizer for controlling an oscillation frequency of an RF transmission voltage-controlled oscillator. The level converter includes a self-bias type voltage amplifier which amplifies a reference frequency signal of the reference frequency oscillator. The self-bias type voltage amplifier includes a coupling capacitor, an amplifying transistor, a load and a bias element and suppresses a variation in the level of each harmonic component even though an external power supply voltage varies.

Abstract: A voltage controlled oscillator circuit includes a ring oscillator including a plurality of delay circuits that are connected like a ring and a voltage to current converter circuit for controlling current flowing in the ring oscillator so as to change an oscillation frequency thereof. The voltage to current converter circuit 11 is provided with a shunt circuit for shunting a part of current obtained by converting input voltage, and the shunted part of the current is used for controlling the current flowing in the ring oscillator.

Abstract: A computer implemented method, testing system, computer usable program code, and apparatus are provided for measuring microprocessor susceptibility to internal noise A noise generator modulates a clock signal to generate noise on a targeted component within a microprocessor. A function generator executes microprocessor functions on a plurality of functional components within the microprocessor. A maximum execution frequency on the plurality of functional components is then measured and a set of frequency ranges where the functional components are susceptible to the generated noise is determined.

Abstract: An apparatus for use with an accelerator includes a circulator having a first port, a second port, a third port, and a fourth port, wherein the first port is configured to couple to a power generator, and the third port is configured to couple to an accelerator, a first phase shifter coupled to the second port, and a second phase shifter coupled to the fourth port. A method of regulating power to and from an accelerator includes providing power using a power generator, varying a magnitude of the power before the power is delivered to the accelerator, receiving a reflected power from the accelerator, and varying the phase of the reflected power from the accelerator. A method of regulating reflected power from an accelerator includes receiving a reflected power from an accelerator, varying the phase of the reflected power, and varying a magnitude of the reflected power.

Abstract: A low phase noise high speed stabilized time base uses a crystal resonator that operates directly at a desired high frequency of one hundred to several hundred MHz. An inverted mesa AT-cut quartz crystal meets this criteria. To promote frequency stability the crystal and its oscillator circuit are thermally clamped to a convenient temperature that need be only loosely regulated, say, at about room temperature. In an exemplary ATE setting that already provides a water flow heat removal system whose supply side is 26° C.,±0.5° C., a 400 MHz inverted mesa AT-cut crystal is simply given its own loop within that water supply. Other temperature stabilization techniques for loose regulation, such as Peltier cells, may be used. The result is a high frequency time base having adequate frequency accuracy and stability, but with the extremely low timing jitter of just the crystal resonator, since there is no contributory timing jitter from a frequency multiplying PLL.

Abstract: The object of the present invention is to provide a crystal oscillator with one IC capable of effectively responding to specifications or a frequency of an installed set, an output terminal of the oscillator 1 is connected to an input terminal of the inverter 2, an output terminal of which is connected to the first resistor 7 and one terminal of the second resistor 8, the other terminal of the first resistor 7 is connected to one terminal of the first capacitor 9 and an input terminal of the first transistor 3, the other terminal of the first capacitor 9 is connected to one terminal of the first switch 11, and the other terminal of the first switch 11 is grounded, the other terminal of the second resistor 8 is connected to one terminal of the second capacitor 10 and an input terminal of the second transistor 4, the other terminal of the second capacitor 10 is connected to one terminal of the second switch 12, and the other terminal of the second switch 12 is grounded, an output terminal of the first transisto

Abstract: A serpentine guard trace for reducing far-end crosstalk of a micro strip transmission line is provided. The serpentine guard trace reduces receiving-end crosstalk caused by an electromagnetic interference of a signal of a nearby transmission line when transmitting a high speed signal through a micro strip transmission line on a printed circuit board. The serpentine guard trace is located between two nearby transmission lines and has a line width narrower than that of transmission lines for an effective serpentine structure. A characteristic impedance of the serpentine guard trace increases due to the narrow line width. Termination resistors having impedance which is the same as the characteristic impedance of the serpentine guard trace are located on both ends of the guard trace to minimize a reflection wave generated in the serpentine guard trace. The receiving-end crosstalk can be effectively reduced by using the serpentine guard trace instead of a linear guard trace.

Abstract: A non-reciprocal circuit element is equipped with a ferrite-magnet assembly which includes a pair of permanent magnets and a ferrite sandwiched between the permanent magnets. A first center electrode and a second center electrode defined by conducting films are provided on principal surfaces of the ferrite, such that the first center electrode and the second center electrode are insulated from each other and intersect each other. The permanent magnets have principal surfaces having substantially the same shape as the principal surfaces of the ferrite. The ferrite has upper and lower surfaces provided with recesses. The recesses have a conductor material embedded therein, whereby intermediate electrodes and connector electrodes are provided.

Abstract: A compact RF differential circuit has a first differential I/O port comprising a first pair of signal carrying terminals which is connected to a source termination and a second differential I/O port comprising a second pair of signal carrying terminals which is connected to a load termination. The common mode impedance measured at either the first or second differential I/O port is zero. The differential mode impedance measured at the first differential I/O port is equal to the differential mode impedance of the source termination, and the differential mode impedance measured at the second differential I/O port of the circuit is equal to the differential mode impedance of the load termination.

Abstract: A miniaturised half-wave balun comprises a single-ended I/O port comprising a first signal carrying terminal for connection to a source impedance and a differential I/O port comprising second and third signal carrying terminals for connection to a load impedance. First and second transmission line sections of equal length and characteristic impedance are connected together at a common end and at opposite ends to the second and third terminals. The first signal carrying terminal is coupled to the first transmission line section. The combined length of the first and second transmission line sections is substantially less than one half of the wavelength of an RF signal at the operating frequency. First and second loading shunt capacitors are connected to respective first and second transmission line sections. A shunt capacitive element is connected at the common end of the transmission line sections.

Abstract: A micro-electro mechanical system (NEMS) device, such as a MEMS switch (100), includes a package seal (104) bonded to a substrate (102), wherein an electrode 106 (e.g., an actuation electrode associated with a switch) is provided on an inner surface (103) of the package seal (104). The MEMS switch (100) might include, for example, a central switch structure implementing a double-pole, single-throw switch using a push-pull arrangement of internal activation electrodes (106, 108). The central switch structure might include a cantilevered moveable actuation electrode (122) or an electrode supported in two or more peripheral regions.

Abstract: In an acoustic wave filter device, first and second longitudinally coupled resonator SAW filters are provided on a piezoelectric substrate. The first and second longitudinally coupled resonator SAW filters are connected in parallel to each other. The first and second longitudinally coupled resonator SAW filters are withdrawal-weighted. The withdrawal weighting in at least the longitudinally coupled resonator SAW filter is different from the withdrawal weighting in the other longitudinally coupled resonator SAW filter.

Abstract: A cable strand for the activation of electrically actuatable injection valves of internal combustion engines having a common-rail injection system, wherein the cable strand connects an engine control device with the injection valves. Electrical cables of the cable strand are molded and/or foamed in a carrier that largely prescribes the shape of the cable strand. At least one filter is also molded and/or foamed in the cable strand and is adapted to affect the electromagnetic compatibility of the cable strand arrangement.