Abstract: Multiple SQUID magnetometers that include at least two SQUID loops, each of which is composed of at least two Josephson Junctions connected in parallel with superconducting wires, are provided. The SQUID loops are fabricated such that they share a common Josephson Junction. Devices and application that employ the multiple SQUID magnetometers are also provided.

Abstract: A detection apparatus for detecting the presence of a sample, the detection apparatus comprising a chamber, ports for introducing a sample within the chamber, an actuation unit for establishing a controllable electromagnetic field in the chamber; and a sensing unit for sensing changes in the electromagnetic field due to the presence of the sample within the chamber. The sensing unit comprises a sensor device comprising a source and a drain embedded in a FET a gate for the FET, in which the gate is formed of a material whose conductivity is related to the electromagnetic field established in a nonconductive medium in contact with the gate.

Abstract: The invention concerns a device and a method for examining magnetic properties of objects, in particular of sheet material such as for example bank notes. Therein the invention proceeds from a device (1) and a method for examining magnetic properties of objects (BN), in particular of sheet material such as for example bank notes, with a magneto-optical layer (42) having magnetic domains, the optical properties of the magneto-optical layer (42) being influenceable by the magnetic properties of the object (BN) to be examined, at least one light source (2) for the generation of light incident upon the magneto-optical layer (42), and at least one sensor (6) for the reception of light which is transmitted and/or reflected by the magneto-optical layer (42), with a magnetic field (B?) in the area of the magneto-optical layer (42) which extends substantially parallel to the surface of the magneto-optical layer (42).

Abstract: System and methods for using nuclear magnetic resonance (NMR) T1 measurements for wireline, LWD and MWD applications and down-hole NMR fluid analyzers. The T1 measurements are characterized by insensitivity to motion, as the detrimental effects arising from tool motion or fluid flow are effectively reduced or eliminated. T1 measurements alone or in combination with other standard oil field measurements are shown to provide efficient data acquisition resulting in compact and robust data sets, the potential for substantially increased logging speeds, and simple methods for fluid typing, including direct and robust identification of gas.

Abstract: In a PPA MRT method and apparatus, a selected region of k-space containing respective portions of some of the incomplete, measured data lines and respective portions of some of the complete, reconstructed data lines is designated. For each data line in the selected region, a level of the noise therein is identified. For each reconstructed, complete data line in the selected region, a scaling factor is calculated that is dependent on the noise level in that reconstructed, complete data line and the noise level in at least one neighboring incomplete, measured data line in the selected region. The scaling factor is then applied to the reconstructed, complete data line in question, so that the contribution of that line to the overall reconstructed image is adjusted according to the scaling factor. The scaling factor can be limited dependent on where the selected region is located in k-space.

Abstract: Methods and related devices are provided for probing a surface by application of a hyperpolarized noble gas having a nuclear electric quadrupole moment to the surface. In an embodiment, the hyperpolarized noble gas is substantially free of alkali metal vapor, such as rubidium vapor used to hyperpolarize the noble gas. Noble gas interaction with the surface of interest is detected by measuring quadrupolar-driven events such as T1, T2 relaxation or coherent processes by nuclear magnetic resonance spectroscopy or by magnetic resonance imaging, for example. The method is capable of probing a variety of surfaces that are difficult to analyze by conventional methods, including biological or non-biological surfaces, to obtain detailed and reliable information related to surface chemical composition.

Abstract: In one aspect, a method of obtaining magnetic resonance (MR) and radio-frequency impedance mapping (RFIM) data from a region of an object arranged proximate a plurality of radio-frequency (RF) coils is provided. The method comprises detecting nuclear magnetic resonance (NMR) signals emitted from the region to form, at least in part, first MR data, obtaining at least one impedance measurement from the plurality of RF coils to form, at least in part, first RFIM data, and computing a first RFIM map indicating a spatial distribution in the region of at least one dielectric property, the first RFIM map computed based, at least in part, on the first RFIM data and the first MR data.

Abstract: Provided is a magnetic resonance imaging system capable of reducing degradation in a magnetic resonance spectrum derived from a change in a static magnetic field. A sequence controller performs non-water-suppressed spectrum measurement (pre-scan) cyclically during water-suppressed spectrum measurement (main scan) accompanied by repetitive measurement intended for averaging of signals, and cyclically detects a water resonant frequency (water-signal peak position) and a phase value at a water-signal peak from an obtained non-water-suppressed spectrum (the cyclic pre-scan makes it possible to sense a time-varying rate of static magnetic field strength (resonant frequency)). For the water-suppressed spectrum measurement (main scan) succeeding the pre-scan, a reception-initiating phase value that is used to detect a magnetic resonance signal is set to a value calculated using the phase value at the water-signal peak position detected during the pre-scan.

Abstract: A magnetic resonance imaging apparatus includes: a static magnetic field generating unit which generates a static magnetic field, a measuring unit which measures the strength distribution characteristic of the static magnetic field, a determination unit which determines correction amounts for first- to nth-order (n is a natural number of more than one) components of the strength distribution characteristic of the static magnetic field by fixing the correction amount for at least one of specific component which are part of the first- to nth-order components at a predetermined amount and determining the correction amounts for other components than the specific components on the basis of the strength distribution characteristic, and a correction magnetic field generating unit which generates correction magnetic fields to correct the static magnetic field on the basis of the correction amounts.

Abstract: It is an object of the present invention to provide means for measuring electric characteristics of dried objects having different shapes and characters, and means which, by measuring an impedance and an electrostatic capacity, non-destructively and high accurately measures a moisture content of the dried objects of different shapes and characters, using an appropriate regression manner. In detail, this invention is to provide a method of non-destructively measuring a moisture content of dried objects, comprising the steps of: introducing dried objects having different characters and shapes into a predetermined container; inserting four electrode terminals into the container; measuring electrical characteristics between two electrodes based on the dried objects and inputting measurement results into a high impedance voltmeter; and non-destructively measuring the moisture content of the dried objects.

Abstract: A group wiring system includes a hub of a server system, a distribution frame including a plurality of wire pair receptacles, a plurality of remote receptacles, a testing device, and a plurality of testing circuits. Each testing circuit is coupled between conductive wires of contacts of an associated wire pair receptacle. Each testing circuit includes a light emitting device and a filtering device. The light emitting device emits light when the testing device applies a testing voltage to the contacts. The testing voltage is a low-frequency voltage signal having a frequency higher than 200 Hz that creates a circuit impedance higher than an impedance of the filtering device when passing through the hub, thereby decaying and filtering the voltage signal and allowing locating test while the server system is on-line. A method for locating wire pairs in a group wiring system is also disclosed.

Abstract: A leakage detection circuit of the present invention includes a branch having a body ground, a protective resistance, a switch element, a detection resistance, and a variable power supply that are coupled in series. A low voltage side of the variable power supply is connected to a negative electrode of a power supply device that is a subject for observation. A computer turns on the switch element only upon leakage detection. Under the control of the computer, the variable power supply outputs the voltage of 0 (zero) volt for detecting the leakage on a high voltage side and the voltage of 10-odd volts for detecting the leakage on the low voltage side. A leakage current or a leakage resistance is determined by amplifying a voltage between both ends of the detection resistance.

Abstract: A method for measuring a stability margin at a node of a polyphase power grid injects suppressed-carrier stimulus into a node of the power grid by low-level amplitude modulation of the output voltage of a pre-exiting generator connected to the node. Response signals are obtained and product demodulated on a per-phase basis and summed in three-phase groups. Demodulated and summed responses contain signals that represent the suppressed-carrier impedance upstream and downstream of the stimulus injection point, and are processed to determine the stability margin at the node.

Abstract: A calibrated network analyzer is re-calibrated by measuring a circuit parameter of a standard device, specifying the type of error coefficient relating to this measured circuit parameter, and calculating an error coefficient of this specified type using this measured circuit parameter. Moreover, of the circuit parameters necessary for this calculation, a circuit parameter other than this measured circuit parameter is reproduced using the theoretical value of this circuit parameter and the standard coefficient obtained by this calibration.

Abstract: A method for determining attenuation of electromagnetic waves impacting an electromagnetic shield. A reference amplitude is provided. A signal exhibiting a first frequency is converted to a converted signal exhibiting a second frequency higher than the first frequency. Electromagnetic waves corresponding to the converted signal are transmitted from a first antenna toward a second antenna with the electromagnetic shield positioned between them. Attenuated remnants of the electromagnetic waves received by the second antenna are converted to a corresponding signal exhibiting a third frequency that is lower than the second frequency. The amplitude of the corresponding signal is compared to the reference amplitude.

Abstract: A sensor arrangement for a sensor arrangement remotely readable by radio frequencies. The sensor arrangement includes an LC resonator that includes a capacitor and a coil, and a sensor element coupled to the LC resonator whose properties change as a function of a measurable quantity. A sensor element according to the invention does not form a direct galvanic contact with the LC resonator, rather the coupling is implemented capacitively or inductively.

Abstract: For measuring a voltage difference between two measurement potentials at the input of a voltage converter that can be controlled via a control input, the measurement potentials are shifted by a voltage potential defined by a first pair of impression currents to obtain a first pair of shifted measurement potentials at the output of the voltage converter. Subsequently, the measurement potentials are shifted by a voltage potential defined by a second pair of impression currents different to the first pair to obtain a second pair of shifted measurement potentials. A controller determines measurement phases, in which the first or second pair of measurement potentials, respectively, is determined. An evaluator determines the voltage difference based on the first voltage difference between the first pair of shifted measurement potentials and based on the second voltage difference between the second pair of shifted measurement potentials and outputs the same at the output.

Abstract: A wired circuit board assembly sheet has a plurality of wired circuit boards, distinguishing marks for distinguishing defectiveness of the wired circuit boards, and a supporting sheet for supporting the plurality of wired circuit boards and the distinguishing marks. Each of the distinguishing marks has an indication portion for indicating a specified one of the wired circuit boards.

Abstract: A probe card for use in testing wafers for semiconductor devices is provided. In the probe card, a region having a plurality of probes corresponding to respective chips is divided into a plurality of subregions. A tester signal is switched between a pair of subregions thus divided so that the tester signal is supplied to one of the pair of subregions. The object to be measured by the probe card is switched according to chip arrangement on the semiconductor wafer by the switching of the tester signal, whereby useless parts in the periphery of the wafer are eliminated and the measurement efficiency is improved.

Abstract: A semiconductor integrated circuit includes a wiring capable of connecting a plurality of chips on a wafer and has a configuration which is capable of cutting the wiring electrically and which allows all the chips to be tested at one time. Specifically, an exclusive test circuit region capable of being shared for testing the plurality of chips is formed on the wafer, and a test circuit is removed from each chip. Terminals of the chips and a terminal of the test circuit are connected through a wiring on the wafer or a device outside the wafer to enable a general test to be performed in burn-in.

Abstract: A method for testing a semiconductor device incorporating a controller, which generates first and second complementary signals, and a memory, which operates in accordance with the first and second complementary signals. The method includes selectively switching the first and second complementary signals to an intermediate potential signal having an intermediate potential of the complementary signals. The method further includes conducting an operational test on the second device with the first and second complementary signals and the intermediate potential signal. This method enables detection of a defective connection between the devices.

Abstract: Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fuses (eFUSES).

Abstract: A universal serial bus (USB) device is comprised of a receiver for receiving signals from a USB host through data lines, and a pull-up resistor circuit connecting pull-up resistors to data lines in response to control signals. The pull-up resistor circuit selectively connects a plurality of pull-up resistors with a data line in response to control signals. The pull-up resistor circuit controls a number of the plurality of pull-up resistors connected with the data line to cause a voltage level of the signal to be lower than a threshold voltage when the USB host resets the USB device.

Abstract: Some embodiments provide a configurable integrated circuit (“IC”) with a configurable node array. A configurable node array may include configurable nodes arranged in rows and columns. It may also include direct offset connections, with each direct offset connection connecting two nodes that are neither in the same column nor the same row. In some embodiments, at least some direct offset connections connect pairs of nodes that are separated by more than one row and at least one column, or by more than one column and at least one row. Some embodiments establish a direct connection by a set of wire segments that traverse through a set of the IC's wiring layers, and a set of vias when multiple wiring layers are involved. Some of the direct connections may have intervening circuits (e.g. buffer circuits). In some embodiments, the nodes in the array are all similar to each other.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes a logic circuit for receiving input data sets and configuration data sets and performing several functions on the input data sets. Each configuration data set specifies a particular function that the logic circuit has to perform on the input data set. The IC also includes a connection circuit for supplying sets of the configuration data to the logic circuit at a particular rate for at least a particular time period. At least two supplied configuration data sets are different and configure the logic circuit to perform two different functions on the input data.

Abstract: Some embodiments of the invention provide a configurable IC that includes several configurable computational tiles and several memory tiles. Each computational tile has a set of configurable logic circuits for configurably performing a plurality of computations and a set of configurable routing circuits. The routing circuits of the tiles configurably route signals between configurable logic circuits. Each memory tiles includes a set of routing circuits and a memory array for storing data on which the logic circuit perform computation. In this IC, at least a first memory tile has the same set of configurable routing circuits as at least a second computational tile.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (“IC”). This IC includes several configurable circuits for receiving configuration data and configurably performing a set of operations based on the configuration data. It also includes several hybrid circuits. Each particular hybrid circuit can interchangeably perform as either a logic circuit or an interconnect circuit in the configurable IC.

Abstract: Some embodiments provide a reconfigurable IC that includes at least two sections, each with several configurable circuits. Each configurable circuit configurably performs a set of operations. Each section stores multiple configuration data sets for each configurable circuit. Each configuration data set for a particular configurable circuit specifies the operation that the particular configurable circuit has to perform from the circuit's set of operations, where the configurable circuits of different sections iterate through different numbers of configuration data sets.

Abstract: Some embodiments provide a circuit for accessing stored data in a configurable IC that includes several configurable circuits. The IC also includes several storage circuits. Each storage circuit has (1) several storage elements for storing data for the configurable circuits, and (2) output circuitry for outputting data stored in the storage elements. The output circuitry includes a first set of interconnects for receiving at least a first repeating periodic signal and for periodically outputting data from at least two storage elements to the configurable circuits.

Abstract: Some embodiments of the invention provide a configurable logic circuit. The logic circuits has inputs for receiving input data. It also has a first connecting circuit for receiving configuration data and at least a portion of the input data. Based at least partially on the received portion of the input data, the first connecting circuit selects configuration data sub-sets. The logic circuit also includes a second core-logic circuit for receiving configuration data sub-sets from the first connecting circuit and for providing the output data. At least two configuration data sub-sets configure the configurable logic circuit to perform at least two different functions on the input data to produce output data.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC). The configurable IC includes first and second interconnect circuits. The first interconnect circuit has a set of input terminals, a set of output terminals, and several connection schemes for communicatively coupling the input terminal set to the output terminal set. During the operation of the IC, the second connection circuit supplies sets of configuration data to the first interconnect circuit at a particular rate for at least a particular time period. At least two supplied configuration data sets are different and configure the first interconnect circuit to use two different connection schemes that differently couple the input and output terminal sets.

Abstract: Some embodiments of the invention provide a reconfigurable IC that has several reconfigurable circuits. Each reconfigurable circuit for configurably performing a set of operations and for reconfiguring at a first frequency. The reconfigurable IC also has at least one reconfiguration signal generator for receiving a clock signal at a second frequency and producing a set of reconfiguration signals with a third frequency. The reconfiguration signals are supplied to the reconfigurable circuits to direct the reconfiguration of the reconfigurable circuits at the first frequency.

Abstract: A semiconductor integrated circuit able to reduce a load of layout design when arranging switches in a power lines for preventing leakage current and able to reduce the influence of a voltage drop occurring in the switches on a signal delay, wherein a plurality of groups of power lines are arranged in stripe shapes, power is supplied to circuit cells by a plurality of groups of branch lines branching from the groups of power lines, power switch cells arranged in the groups of branch lines turn on or off the supply of power to the circuit cells, the power switch cells are arranged dispersed in the area of arrangement of the circuit cells, and the supply of power by the power switch cells is finely controlled for every relatively small number of circuit cells.

Abstract: Some embodiments provide a reconfigurable IC that includes several sections. Each section includes several configurable circuits, each of which of which configurably performs a set of operations, Each section stores multiple configuration data sets for each configurable circuit. Each configuration data set for a particular configurable circuit specifies the operation that the particular configurable circuit has to perform from the circuit's set of operations, where the configurable circuits of at least two different sections change configuration data sets at two different reconfiguration rates.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (“IC”). The IC includes several non-configurable memories for storing and outputting data. The IC also includes several configurable logic circuits that each can configurably perform a set of functions, and several configurable interconnect circuits that each can configurably perform a set of connection operations. The IC further includes several multiplexers, each multiplexer having input, output, and select terminal sets. During the operation of the IC, at least a first multiplexer's input terminal set receives the output of a first memory from a set of configurable interconnect circuits, while the select terminal set receives a set of select signals from at least one configurable logic circuit that direct the multiplexer to output a sub-set of the first memory's output data along the first multiplexer's output terminal set.

Abstract: Some embodiments provide a configurable IC that includes several configurable logic circuits for configurably performing computations. The configurable IC also includes several configurable routing circuits for configurable routing signals to and from the logic circuits. In some embodiments, at least a set of the routing circuits are routing/storage circuits. Each routing/storage circuit has an output and a storage section at the output for controllably storing a signal that the routing/storage circuit produces at the output.

Abstract: Some embodiments provide a configurable integrated circuit (“IC”) that includes several configurable tiles arranged in a tile arrangement. Each configurable tile has a set of configurable logic circuits and a set of configurable routing circuits for routing signals between configurable logic circuits. At least a first routing circuit of a first tile has at least one direct connection with a second circuit of a second tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (“IC”). The IC includes a first set of circuits and a second set of circuits interspersed among the first set of circuits. Each set of circuits includes at least ten volatile configurable circuits. Several circuits in at least one of the sets are user multiplexers. Each particular user multiplexer has input and output terminals and has a set of select terminals for receiving a set of user-design signals that directs the particular multiplexer to connect a set of the input terminals to a set of the output terminals. The user-design signals are signals generated internally by the IC.

Abstract: A configurable integrated circuit (“IC”) that includes several configurable tiles arranged in a tile arrangement. Each configurable tile has a set of configurable logic circuits and a set of configurable routing circuits for routing signals between configurable logic circuits. In some embodiments, at least a first logic circuit of a first tile has at least one direct connection with a second circuit of a second tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement.

Abstract: Some embodiments provide an IC with a configurable node array that has (1) two similar nodes within the interior of the array, and (2) two different connection schemes. The first connection scheme specifies a set of connections between the first node and a set of nodes in the array, while the second connection scheme specifies a second set of connections between the second node and a set of nodes in the array. The two nodes cannot connect to any nodes on the boundary of the array with any connection that is specified in any connection scheme.

Abstract: Some embodiments of the invention provide a first configurable integrated circuit (IC) that has a first configurable IC design. The first configurable IC implements a second IC design that is specified for a second IC that is to operate a particular design rate. The first configurable IC includes several configurable logic circuits. Each configurable logic circuit can configurably perform a set of functions. The IC also includes several configurable interconnect circuits that configurably couple the logic circuits. At least several configurable circuits can reconfigure faster than the particular design rate.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes first and second circuits. The first circuit is a logic circuit for receiving configuration data sets and performing at least a first function when receiving a first configuration data set and a second function when receiving a second configuration data set. The second circuit communicatively couples to the first logic circuit. The second circuit is for supplying configuration data sets to the first logic circuit. The second circuit has a first set of input terminals. The integrated circuit also has a second set of input terminals for carrying data. Several the second set of input terminals overlap several of the first set of input terminals. The IC also has a set of vias, where each via connects an input terminal in the first set with an input terminal in the second set.

Abstract: Some embodiments of the invention provide an configurable integrated circuit (“IC”). This IC has at least fifty configurable nodes arranged in an array that several rows and columns. The IC also has several direct offset connections, where each particular direct offset connection connects two offset nodes that are neither in the same column nor in the same row in the array. In some embodiments, several direct connections do not include any intervening circuits. On the other hand, in some embodiments, several direct connections have intervening circuits, which differ from the nodes in the array.

Abstract: A semiconductor integrated circuit able to reduce a load of layout design when arranging switches in a power lines for preventing leakage current and able to reduce the influence of a voltage drop occurring in the switches on a signal delay, wherein a plurality of groups of power lines are arranged in stripe shapes, power is supplied to circuit cells by a plurality of groups of branch lines branching from the groups of power lines, power switch cells arranged in the groups of branch lines turn on or off the supply of power to the circuit cells, the power switch cells are arranged dispersed in the area of arrangement of the circuit cells, and the supply of power by the power switch cells is finely controlled for every relatively small number of circuit cells.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes at least fifty configurable circuits arranged in an array having a plurality of rows and a plurality of columns. Each configurable circuit for configurably performing a set of operations. At least a first configurable circuit reconfigures at a first reconfiguration rate. The first configurable circuit performs a different operation each time the first configurable circuit is reconfigured. The reconfiguration of the first configurable circuit does not follow any sequential progression through the set of operations of the first configurable circuit.

Abstract: A process compensation circuit for an inverting element of a CMOS device, including a duplicate inverting element connected in parallel with the inverting element of the CMOS device. An upside-down inverter stage has an input connected to the output of the duplicate inverting element, and an output connected to the output of the inverting element of the CMOS device. The upside-down inverter stage is configured to counteract a delayed logic transition of the output of the inverting element of the CMOS device in the event of a process skew between NFET and PFET devices.

Abstract: Current feedback amplifiers circuits that generate common mode (CM) and/or differential mode (DM) currents are provided herein. This description is not intended to be a complete description of, or limit the scope of, the invention. Other features, aspects, and objects of the invention can be obtained from a review of the specification, the figures and the claims.

Abstract: A circuit and a method are provided to produce a novel comparator with Schmitt trigger hysteresis character. The circuit includes a current source which controls the magnitude of current flow through this comparator circuit. It has a first logic device which is turned ON by a reference voltage, and a second logic device is turned ON by a comparator input voltage. A first feedback device is turned ON by a negative comparator output. A first parallel resistor is connected in parallel to the first feedback device. A second feedback device is turned ON by a positive comparator output. A second parallel resistor is connected in parallel to the second feedback device. The first and second parallel resistors are used to provide the differential comparator with switching voltage offsets which result in the Schmitt trigger hysteresis character.

Abstract: Pre-emphasis circuitry and methods for signal transmission provide multiple levels of output signal amplification over one or more baud periods after an input signal transition. The multiple, gradually decreasing levels of output signal amplification reduce power consumption and better approximate the desired signal response.

Abstract: A D-type static latch circuit is provided that includes first and second circuits connected between a first reference potential and a second reference potential, with the first circuit comprising a first transistor, a second transistor and a third transistor connected in series, and the second circuit comprising a fourth transistor, a fifth transistor and a sixth transistor connected in series.