Abstract: An interface circuit outputting a clock signal and data to a data register configured to serially read in the data synchronously with the clock signal, in response to a change of a control signal for outputting the clock signal and the data from one logic level to the other logic level, the interface circuit comprising a clock output circuit configured to: detect a logic level of the clock signal when the control signal changes from the one logic level to the other logic level; output the clock signal on an as-is basis to the data register, when detecting one logic level of the clock signal; and output the clock signal after having changed from the other logic level to the one logic level, to the data register, when detecting the other logic level of the clock signal.

Abstract: A delay looked loop (DLL) having a charge pump gain independent of the operating frequency of the DLL.

Abstract: A duty cycle corrector includes a first controllable delay, a second controllable delay, a phase detector, and a compensation circuit. The first controllable delay is configured to delay a first signal to provide a second signal. The second controllable delay is configured to delay the second signal to provide a third signal. The phase detector is configured to adjust the first controllable delay and the second controllable delay to phase lock the third signal to the first signal. The compensation circuit is configured to compensate for a mismatch between the first controllable delay and the second controllable delay to provide a fourth signal in response to the first signal and a fifth signal approximately 180 degrees out of phase with the fourth signal in response to the second signal.

Abstract: A programmable delay circuit includes a plurality of delay blocks, a plurality of corresponding tri-state drivers and at least one decoder. The delay blocks are connected together so as to form a series chain. Each of the tri-state drivers includes an input connected to an output of a corresponding one of the delay blocks, and a control input adapted to receive one of multiple control signals. The tri-state driver is operative in one of at least a first mode and a second mode as a function of a corresponding one of the control signals. In the first mode, an output signal generated at an output of the tri-state driver is a function of a voltage level at the input of the tri-state driver, and in the second mode the output of the tri-state driver is in a high-impedance state. The output of each of the tri-state drivers is coupled together and forms an output of the programmable delay circuit. The decoder is connected to the plurality of tri-state drivers.

Abstract: An internal clock generator according to the present invention includes a detector, an internal signal generator and a clock output unit. The detector detects a transition point of an external clock signal and outputting a detection signal. The internal signal generator generates an internal signal in response to the detection signal and a pulse width control signal. The clock output unit outputs an internal clock signal having a pulse width, which is set based on the internal signal. A transition point of an external clock signal is detected and an internal clock signal is generated based on the detection result. It is therefore possible to maintain the pulse width of the internal clock signal to a set value regardless of variation in the pulse width of the external clock signal.

Abstract: Embodiments of threshold adjustment circuits are disclosed. An example circuit includes a first differential pair of first and second thin oxide transistors. The first and second thin oxide transistors decrease a DC voltage component of a first or second component of an input signal of the circuit. The example circuit further includes a second differential pair of third and fourth thin oxide transistors. The second and third thin oxide transistors increase a DC voltage component of the first or the second component of the input signal. The example circuit also includes a power supply for providing a supply voltage to the circuit, the power supply having a voltage level above a reliability level of the thin oxide transistors. In the example circuit, each of the differential pair thin oxide transistors is switched by a signal that keeps each of the first, second, third, and fourth thin oxide transistors operating in saturation.

Abstract: Systems and methods are disclosed for a clamping circuit for protecting against voltage overstresses. One embodiment of the system comprises a first voltage comparator adapted to detect when a selected voltage exceeds a first predetermined voltage and a second voltage comparator adapted to detect when the selected voltage falls below a second predetermined voltage, thereby preventing voltage overstresses.

Abstract: A level shifter is proposed.

Abstract: A method of linearising a non-linear opto-electronic apparatus that includes an opto-electronic Mach-Zehnder modulator that receives an incoming electrical signal for modulating a light signal passing through the modulator, where the transfer characteristic of the modulator is sinusoidal, and including means for detecting the modulating light signal and for digitising the detected signal, wherein the method comprises the following steps: injecting one or more calibration tones as an input electrical signal and obtaining a digitised form of the output signal obtaining the spectrum of said digitised form and measuring the spectral values at the frequencies of the input tone or tones and at the frequencies of spectral lines arising from the non-linearity; providing, from said spectral values, an inverse form of the non-linearity; and performing linearisation on subsequent output signals for arbitrary input signals by applying said inverse form of the non-linearity to the output signal.

Abstract: The invention relates to a hardware implemented filtering method including establishing a representation DIS of the derivative of at least a part of a time-quantized input signal IS, and establishing at least one sample of a time- and amplitude-quantized output signal OS by performing filtering on the basis of at least a part of a filter representation IFC1, IFC2, IFC3 and the representation DIS of the derivative of at least a part of the input signal IS. The invention further relates to a hardware implemented decimation method for decimating a time-quantized input signal IS including dividing the time-quantized input signal IS into intervals, for each of the intervals establishing a sample of a time- and amplitude-quantized output signal OS according to the above mentioned filtering method. The invention further relates to a fast filtering means FFM implementing the above-mentioned methods.

Abstract: Input stages for use in multiplexing, and methods for using the same, are provided herein. An input stage includes an input terminal and an output terminal. A voltage input signal is accepted at the input terminal of the input stage. When the input stage is selected, a substantially unmodified version of the voltage input signal is presented at the output terminal of the input stage, when the input stage is selected. When the input stage is deselected, a rejection voltage signal is produced, where the rejection voltage signal is of substantially equal magnitude and opposite polarity to the corresponding voltage input signal in order to reject the voltage input signal and thereby present a substantially constant voltage at the output terminal of the input stage regardless of variations in the voltage input signal.

Abstract: A high voltage pumping device is provided which includes a first high voltage detector for detecting a level of a high voltage, and generating a first pumping enable signal which is enabled when the high voltage is lower than a predetermined reference voltage, a pumping control signal generator for generating a pumping control signal adapted to control a high voltage pumping operation, in response to the first pumping enable signal and a first control signal which is enabled for a first period when an active mode is begun, an oscillator for generating a predetermined oscillation signal in response to the pumping control signal, and a pumping unit for pumping the high voltage to a predetermined level in response to the oscillation signal supplied from the oscillator.

Abstract: An embodiment of the present invention is directed to a low power voltage reference circuit. The circuit includes a first circuit for generating a PTAT voltage without using an operational amplifier. The circuit also includes a second circuit for generating the reference voltage. The first and the second circuit do not utilize a resistor.

Abstract: A semiconductor device of the invention comprises a logic circuit to which a power supply voltage, a sub-power supply voltage lower than the power supply voltage, a ground voltage and a sub-ground voltage higher than the ground voltage are supplied; a main power supply line supplying the power supply voltage; and a main ground line supplying the ground voltage. A unit circuit constituting the logic circuit includes first to third PMOS transistors and first to third PMOS transistors. The third PMOS transistor is connected between sources of the first and second PMOS transistors, the main power supply line is connected to its one node, and the sub-power supply voltage is generated at its other node. The third NMOS transistor is connected between sources of the first and second NMOS transistors, the main ground line is connected to its one node, and the sub-ground voltage is generated at its other node.

Abstract: Leakage currents across circuit components such as transistors are avoided by placing circuits into a low-leakage standby mode. The circuits are configured such that voltage differentials across leakage-prone circuit components are avoided when in standby mode. Various means are used to configure the circuits, such as configuration ports, data input lines, scan chains, etc. In embodiments containing reconfigurable devices, low-threshold transistors are used to implement the routing network.

Abstract: An embodiment of the invention uses a predistortion correction signal to combination the modulated RF signal by an analog multiplier for linearization of power amplifiers having nonlinear characteristics such as those used in wireless RF transmitters. A predistortion controller comprises a plurality of down converters for retrieving both the ideal non-distorted information and the feedback distorted information, together with pre-stored digitally-indexed predistortion information stored, for example, in a look-up table. The digitally-indexed information models nonlinear characteristics of the high power amplifier, and is stored prior to processing of pre-compensation in the power amplifier. When the predistortion information is combined with the modulated RF signal in the analog multiplier, the result is a substantially linear information transmission from the power amplifier.

Abstract: The present invention relates to an amplifier circuit and system, and to a method of compensating a gain imbalance generated in a complementary amplifier stage with first and second amplifier means (22, 24) in a bridge configuration. A compensation offset current is generated in response to the values of input signals supplied to respective inputs of said first and second amplifier means, and the compensation offset current is injected to a junction node between the inputs of the first and second amplifier means (22, 24). Thereby, it can be ensured that the gain of the first and second amplifier means does not depend on the kind of input signals, i.e. balanced or unbalanced input signals. An automatic gain correction can thus be achieved and the requirement of additional control signals or control terminals for selection of gain control circuits depending on the kind of input source or input configuration of the amplifier circuit can be dropped.

Abstract: There is provided with an amplifying device including: an input terminal configured to input an input signal; first to ith blocks including first to ith resonators having different first to ith resonance frequencies and first to ith amplifiers that amplify signals which have passed through the first to ith resonators; a divider configured to divide the input signal for the first to ith resonators; a combination section configured to combine the signals which have passed through the first to ith blocks to obtain a combined signal; and an output terminal configured to output the combined signal, wherein a jth (j: an integer between 1 and i?1) block includes a phase adjustment section which provides an output signal of the jth block with a phase difference within a range of {(180±30)+(360×n)} degrees (n: an integer of 0 or greater) from an output signal that passes through a (j+1)th block.

Abstract: A linearizer changes a gain characteristic to a valley characteristic in which a gain reduces and then increases. The linearizer includes: a signal path in which an RF signal input terminal (1), an input side bias blocking capacitor (4), a diode pair (8, 12) including diodes having opposite polarities to each other, an output side bias blocking capacitor (5), and an RF signal output terminal (2) in series in the stated order; a bias circuit in which a resistor is provided between and a signal path formed between the input side bias blocking capacitor (4) and the diode pair (8, 12) and a bias terminal (3); an RF short-circuiting capacitor (6) whose one end is connected with the bias circuit between the bias terminal (3) and the resistor (7) and whose other end is grounded; and a DC feed inductor (11) whose one end is connected with the signal path between the diode pair (8, 12) and the output side bias blocking capacitor (5) and whose other end is grounded.

Abstract: To cancel a reflected wave reflected from a connecting portion (22) and leaking into a feedback signal when a non-matched component is connected, the reflected wave is extracted by a circulator (30) and its phase and amplitude are adjusted by a vector adjusting circuit (32), and then the thus adjusted reflected wave is vector-summed with the feedback signal in a vector sum circuit (34).

Abstract: An amplifier in an embodiment of the present invention has MOS transistors connected serially between a power supply VDD and a ground terminal GND; an output terminal Vout connected to a node provided between the MOS transistors; a first mirror capacity provided between the gate of a MOS transistor and the output terminal Vout; and a second mirror capacity provided between the gate of another MOS transistor and the output terminal Vout. The amplifier further includes a first switching circuit for connecting one end of the first mirror capacity to the power supply terminal VDD or to the gate of a MOS transistor; and a second switching circuit for connecting one end of the second mirror capacity to the ground terminal GND or to the gate of another MOS transistor.

Abstract: A class AB folded cascode circuit includes a differential current follower having first and second cascode transistors with emitters connected to first and second input conductors. An input of a first current mirror is coupled to the first input conductor, and an input of a second current mirror is coupled to the second input conductor. Outputs of the second and first current mirrors are coupled to collectors of the first and second cascode transistors, respectively, and also to first and second outputs, respectively, of the differential current follower. A third current mirror converts a differential output current in the first and second output conductors to a corresponding single-ended output voltage on the second output conductor.

Abstract: The cascoded gain single stage amplifier includes: a common gate differential pair; a first amplifier having a first input coupled to a first leg of the differential pair, and a second input coupled to a second leg of the differential pair; a current mirror coupled to the differential pair; a second amplifier having a first input coupled to a first leg of the current mirror, and a second input coupled to a second leg of the current mirror.

Abstract: An amplifier circuit includes an operational amplifier having first and second input nodes and one output node which is connected to a data line for which a pixel is provided; a feedback circuit having first and second elements which are connected to one of the first and second input nodes at their one ends; and a first switch section. The first switch section switches an operation mode between a first drive mode in which the other end of the first element is connected to the output node and a second drive mode in which the other end of the second element is connected to the output node.

Abstract: An integrated circuit device includes a variable-gain amplifier, memory circuit and gain control update circuit. The variable-gain amplifier generates an amplified signal having an amplitude according to a gain control value that is stored, at least during a first interval, within the memory circuit. The update circuit generates an updated gain control value based on the amplified signal during the first interval, and outputs the updated gain control value to the memory circuit to be stored therein at a conclusion of the first interval.

Abstract: A chain-chopping current mirror and a method for stabilizing output currents are disclosed. The current mirror includes multiple output nodes, a bias source unit, multiple current mirroring units and multiple switch components. The bias source unit provides a reference bias according to the received current. Each of the current mirroring units outputs an output current according to the reference bias. The control terminal of each the switch component receives a clock signal and determines whether the first terminal thereof is coupled with the second terminal or the third terminal thereof according to the clock signal, wherein the first terminal of the ith switch component is coupled with the output terminal of the ith current mirroring unit, the second terminal thereof is coupled with the ith output node and the third terminal thereof is coupled with the (i+1)th output node, where i is a natural number.

Abstract: The present invention discloses a voltage-controlled oscillating apparatus to generate an oscillating signal. The voltage-controlled oscillating device includes: a regulating circuit, a biasing circuit, and an oscillator. In which the regulating circuit includes an amplifier, with a first input terminal coupled to a control voltage; and a voltage adjusting circuit, coupled between a second input terminal and an output terminal to feed a feedback voltage back to the second input terminal of the amplifier, and adjust the feedback voltage according to the output signal in the output terminal of the amplifier. The biasing circuit is coupled to the output terminal of the amplifier to generate a biasing signal according to the output signal in the output terminal of the amplifier; and the oscillator is coupled to the biasing circuit to generate the oscillating signal according to the biasing signal.

Abstract: The oscillating signal generator utilizes a rising edge phase difference and a falling edge phase difference of the input signal and a feedback signal to generate a rising control signal and a falling control signal, and generates an output signal according to the rising control signal and the falling control signal; wherein the feedback signal corresponds to the output signal.

Abstract: Phase locked loop circuit (PLL-circuit) comprising a phase comparator (30) for detecting a phase difference ?? between an input reference signal Uref and an input signal Up,in, wherein Kp is a phase detector gain of said phase comparator, a voltage controlled oscillator (VCO) for generating a periodic output signal Uvco,out having an angular frequency ?vco,out depending on an input signal UVCO,in, wherein Kvco is a voltage controlled oscillator gain of said voltage controlled oscillator, and a controller adapted to control the phase detector gain Kp during an operation of the phase locked loop circuit in such a way that a loop gain K:=Kp*Kvco remains within a predetermined range during the operation of the phase locked loop circuit.

Abstract: An oscillating circuit includes N nodes outputting oscillating signals, a main loop circuit including N inverting circuits, and a plurality of auxiliary loop circuits. Each inverting circuit in the auxiliary loop circuits is connected in parallel with even numbers of inverting circuits cascaded in the main loop circuit. The circuits for feeding back signals from outputs to inputs of the respective inverters of the main loop circuit have circuit configurations equivalent to each other. Each inverting circuit in the main loop circuit and the auxiliary loop circuits drives an output line such that a phase of an output signal is inverted with respect to a phase of an input signal and has driving power that becomes lower when the phases of the output signal and the input signal are inverted with respect to each other than when the output signal and the input signal are in phase with each other.

Abstract: A crystal oscillator for surface-mounting on a circuit board comprises a package body which includes a bottom wall layer, and a frame wall layer having an opening and laminated on the bottom wall layer, where the opening defines a recess in the package body, a crystal blank contained in the recess, an IC chip contained in the recess, and mounting terminals disposed at four corners on an outer bottom surface of the package body for use in mounting the crystal oscillator. An oscillation circuit using the crystal blank is integrated in the IC chip. The package body is formed with a cavity in at least a central region of the outer bottom surface thereof, and no electrode layer is disposed in the cavity.

Abstract: Provided is a dual mode quartz oscillator capable of suppressing a B mode interference securely and also accomplishing a stable third and fifth overtone oscillations. A dual mode quartz oscillation circuit, including a first oscillation unit for oscillating a third order overtone oscillation against a fundamental wave oscillation of a quartz oscillator; a second oscillation unit for oscillating a fifth order overtone oscillation against a fundamental wave oscillation of the quartz oscillator; and a band restriction unit for inhibiting an interference of the fifth overtone oscillation between the quartz oscillator and either one of the first or second oscillation unit.

Abstract: An oscillation circuit, including: a complementary metal oxide semiconductor (CMOS) inverter coupled between a first potential and a second potential; a first element unit whose one terminal is coupled to an input terminal of the CMOS inverter; a second element unit whose one terminal is coupled to the input terminal of the CMOS inverter and whose other terminal is coupled to an output terminal of the CMOS inverter; a third element unit whose one terminal is coupled to the output terminal of the CMOS inverter; and a fourth element unit whose one terminal is coupled to the other terminal of the first element unit and to the other terminal of the third element unit, and whose other terminal is coupled to either the first potential or the second potential; in that: the first, second, third, and fourth element units are any of a quartz crystal resonator, a resistor, an inductor, and a capacitor; the oscillation circuit oscillating at a frequency determined by the first, second, and third element units.

Abstract: A surface mount crystal oscillator comprises: a crystal unit having a crystal blank hermetically sealed in a package, and first external terminals formed on an outer bottom surface of the package; and a mounting substrate for containing an IC chip which has an oscillation circuit integrated therein, the oscillation circuit using the crystal blank. The mounting substrate includes second external terminals corresponding to the first external terminals on one main surface, and mounting terminals on the other main surface. The mounting substrate comprises a printed wiring board made up of a lower layer, an intermediate frame layer having an opening, and an upper layer laminated one on another. The IC chip is placed in a hollow space defined by the opening. The first external terminals are bonded to the second external terminals to integrate the crystal unit with the mounting substrate.

Abstract: A FET oscillator with increased frequency stability. This is accomplished by using a controlled voltage supply with error correction to power the amplifier stage of the oscillator. This voltage changes as the oscillator temperature increases in order to reduce the variation in frequency, caused by the amplifier and other frequency determining components changes. By using this compensated amplifier as the active section of an oscillator, the oscillator frequency stability is increased.

Abstract: A free running clock circuit includes a switching circuit for switching between first and second logic states at a predetermined frequency based upon a trip voltage. The switching circuit has an inherent temperature profile associated therewith. A voltage divider circuit outputs a defined trip voltage that is compensated over the temperature to offset the temperature profile of said switching circuit to provide an overall temperature compensated operation for the free running clock circuit. The voltage divider circuit has a top programmable resistor array connected in series with at least two programmable resistor arrays between two supply terminals of differing voltages.

Abstract: A free running clock circuit includes a switching circuit for switching between first and second logic states at a predetermined frequency based upon a trip voltage the switching circuit has a programmable temperature profile associated therewith. The switching circuit includes a comparator circuit that has first and second comparators. The first and second comparators have a reference input connected to receive the trip voltage, and the output of the comparators change logic states between a first logic state and a second logic state when the other input of the comparator passes the trip voltage. The first and second comparators have a programmable offset voltage enabling programming of the programmable voltage supply profile of the switching circuit. An RC timing circuit defines when the outputs of the comparators switch between the first and second logic states by providing a feedback to the other inputs of the two comparators.

Abstract: A frequency fine-tuning circuit includes first and second varactors. The first varactor is coupled between a tuning node with a first tuning voltage applied thereon and a first node with a second tuning voltage applied thereon. The second varactor is coupled between the first node and a second node with a bias voltage applied thereon. The second tuning voltage is in a range between the first tuning voltage and the bias voltage such as an average of the first tuning voltage and the bias voltage for increasing linearity of the frequency fine-tuning circuit.

Abstract: An active 90-degree phase shifter with LC-type emitter (source) degeneration is provided, which is practiced in an integrated circuit. The phase shifter comprises a first differential amplifier, having one first signal output end and comprising an inductor, a first transistor and a second transistor, wherein the inductor is connected to the emitters (sources) of the first and the second transistors; and a second differential amplifier, having one second signal output end and comprising a capacitor, a third transistor and a fourth transistor, wherein the capacitor is connected to the emitters (sources) of the third and the fourth transistors. Wherein the bases (gates) of the first and the fourth transistors are signal input ends, and the bases (gates) of the second and the third transistors are coupled together.

Abstract: A plurality of differential signal transmitters can transmit data signals differentially through a plurality of conductive signal lines. Ones of the signal lines can be shared between transmitters, and others of the signal lines need not be shared between transmitters.

Abstract: Four SP4T switches (31-34) are grouped in twos to form two switch pairs. First conductive lines (411-414, 421-424) are arranged in fours between the SP4T switches (31, 34; 32, 33) constituting the switch pairs. Each of four second conductive lines (51-54) connects to a corresponding one of different conductive lines of the first conductive lines which connect to the respective switch pairs. The first and second conductive lines are arranged on a dielectric layer having a lower surface on which a ground conductor (6) is formed. The dielectric, layer has a two-layer structure. The first conductive lines are arranged on the first dielectric layer as a lower layer. The second conductive lines are arranged on the second dielectric layer as an upper layer. This arrangement makes it possible to attain a reduction in the size of a matrix switch and a reduction in loss and allow broadband operation.

Abstract: A small-sized noise suppression circuit capable of suppressing noise in a wide frequency range is realized. A noise suppression circuit has first and second inductors inserted in series in a first conductive line, and a series circuit configured to have a third inductor and a first capacitor connected in series. One end of the series circuit is connected to a junction of the first and second inductors and the other end is connected to a second conductive line. Even when a coupling coefficient k between the first and second inductors is smaller than 1, by adjusting the value of the inductance of the third inductor in accordance with the value of the coupling coefficient k, an attenuation characteristic which is almost the same as or similar to that in an ideal state is obtained.

Abstract: In a multilayer bandpass filter, capacitances are produced between a ground electrode provided in a ground electrode formation layer and capacitor electrodes provided in a capacitor electrode formation layer. A plurality of inductor electrodes are defined by via-electrodes and line electrodes such that loop planes of inductor electrodes at least partially overlap each other when seen in a direction in which the inductor electrodes are arranged. The direction of the loop of the inductor electrode of the LC parallel resonator located (at a first stage) at an input end is set to be opposite to the direction of the loop of the inductor electrodes of the LC parallel resonator (at a second stage) adjacent to the inductor electrode of the LC parallel resonator located at the input end.

Abstract: An electronic part includes: a substrate; a comb-shaped electrode having a plurality of electrode fingers arranged parallel to one another on the upper surface of the substrate; and a protective film formed on the upper surface of the substrate so as to cover the comb-shaped electrode. The protective film has convex portions and concave portions. The convex portions are upwardly convex at the positions corresponding to the electrode fingers, and the concave portions are downwardly concave between the convex portions. The cross section of the protective film in the direction orthogonal to the extending direction of the electrode fingers has a downward convex curve between apex portions of the convex portions.

Abstract: A component includes a filter having a first structure and a second structure. The component also includes a substrate on which the first and second structures are arranged. The first structure has an approximately uniform layer thickness and an approximately uniform composition. The second structure has an approximately uniform layer thickness and an approximately uniform composition. At least one of the layer thickness or composition of the first structure differs from the layer thickness or composition of the second structure.

Abstract: A superconductor filter comprises a plurality of resonance elements arranged between input-output lines formed on a substrate. Metal conductor sections serving to inhibit the spatial coupling between the adjacent resonance elements are arranged between prescribed resonance elements, and a prescribed resonance element is coupled with another resonance element by a coupling transmission line. It follows that each resonance element is coupled with another resonance element by the direct coupling via the coupling transmission line or by the spatial coupling via the space.

Abstract: A high Q cavity resonator loaded with a metallic post and a ceramic disc, the resonator comprising an inner conductive post having a length less than a quarter wavelength. The resonance frequency of the resonator is tunable by changing a distance between a) an outer plate and b) a ceramic disc and an end cap where the ceramic disc is located between the outer plate and the end cap. The resonance frequency can be tuned when the outer plate, ceramic disc, and end cap are in contact with each other by varying a pressure between the contact surfaces of the ceramic disc, the end cap and the outer plate. Temperature compensation allows the resonator to hold a resonance frequency over a range of tunable frequencies despite changes in temperature, and can be achieved by selecting thermal coefficients of expansion of components holding or placing the ceramic disc and end cap relative to the outer plate.

Abstract: A coplanar waveguide CPW using multi-layer interconnection CMOS technology is provided. In the CPW including an interlayer insulator disposed on a substrate, metal multilayers disposed on the interlayer insulator, and a ground line-a signal line-a ground line formed of an uppermost metal layer, when a ground line of a lowermost layer is connected to the ground line of the uppermost layer, intermediate metal layers are designed to gradually increase or decrease in width, or to be uneven so as to maximize an area where an ultra-high frequency spreads, thereby minimizing CPW loss and maximizing a slow wave effect. As a result, it is possible to improve performance of an ultra-high frequency circuit and miniaturize the circuit.

Abstract: A pillbox vacuum window of the present invention has a first metal part and a second metal part. The first metal part includes a ceramic disk formed with a metallization layer in a peripheral area thereof, a larger diameter cylindrical portion, and a smaller diameter cylindrical portion having an inner diameter smaller than that of the larger diameter cylindrical portion, and coupled to the larger diameter cylindrical portion to form a step section at a joint, where the ceramic disk is fitted into the step section. The second metal part includes a cylindrical portion, where the cylindrical portion is inserted into the step section of the first metal part while the ceramic disk is placed in the step section of the first metal part.

Abstract: A circuit breaker includes separable contacts, an operating mechanism structured to open and close the separable contacts, a molded enclosure comprising a first molded portion and a second molded portion, a plurality of thread cutting screws fastening the first molded portion to the second molded portion, and a plurality of machine screws. The first molded portion and the second molded portion cooperate to form a plurality of exterior walls. The exterior walls define an interior volume, which encloses the separable contacts and at least a portion of the operating mechanism. The machine screws extend within and reinforce the exterior walls and restrict expansion of the exterior walls away from the interior volume.