Abstract: The present invention provides dynamic control of back gate bias on pull-up pFETs in a FinFET SRAM cell. A method according to the present invention includes providing a bias voltage to a back gate of at least one transistor in the SRAM cell, and dynamically controlling the bias voltage based on an operational mode (e.g., Read, Half-Select, Write, Standby) of the SRAM cell.

Abstract: A static random access memory is configured for operation at sub-threshold voltage levels. A bistable circuit is supplemented by buffer circuitry configured to improve read performance and float circuitry to improve write performance.

Abstract: This disclosure concerns a LSI comprising two bit lines; two input nodes; sense nodes transmitting a signal difference input to the two input nodes; an output node outputting the amplified signal; a current adjustment gate adjusting an amount of current flowing through one of the two sense nodes; a latch circuit controlling the current adjustment gate; two signal lines transmitting a voltage source and a comparison voltage via the two input nodes, the comparison voltage being obtained by subtracting a predetermined threshold voltage from the power source voltage; and two switching elements provided between the two input nodes and the two signal lines, wherein the latch circuit switches the current adjustment gate in the case where the amplified signal is an inversion signal of an amplified signal according to the threshold voltage when the power source voltage and the comparison voltage are respectively applied to the two input nodes.

Abstract: A data storage device and methods for storing and reading data are provided. The data storage device includes a data storage medium and second device. The data storage medium has an insulating layer, a first electrode layer over the insulating layer and at least one layer of resistance variable material over the first electrode layer. The second device includes a substrate and at least one conductive point configured to electrically contact the data storage medium.

Abstract: A magnetic memory cell, used in a magnetic memory device, includes a stacked magnetic pinned layer, serving as a part of the base structure. The stacked magnetic pinned stacked layer has a top pinned layer and a bottom pinned layer, between which there is a sufficient large magnetic coupling force to maintain magnetization of the top pinned layer on a reference direction. A tunnel barrier layer is disposed on the stacked magnetic pinned layer. A magnetic free stacked layer is disposed on the tunnel barrier layer. The magnetic free stacked layer includes a bottom free layer having a bottom magnetization and a top free layer having a top magnetization. When no assisted magnetic field is applied, the bottom magnetization is anti-parallel to the top magnetization and is perpendicular to the reference direction on the top pinned layer. A magnetic bias layer can be also disposed on the top free layer.

Abstract: A memory element is provided. The memory element includes a memory layer that retains information based on a magnetization state of a magnetic material, in which a magnetization pinned layer is provided for the memory layer through an intermediate layer, the intermediate layer is formed of an insulator, spin-polarized electrons are injected in a stacking direction to change a magnetization direction of the memory layer, so that information is recorded in the memory layer, and a fine oxide is dispersed in an entire or part of a ferromagnetic layer forming the memory layer.

Abstract: A phase change memory device comprises a memory cell array and a write driver circuit, and a column selection circuit. The memory cell array comprises a plurality of block units each connected between a corresponding pair of word line drivers. The write driver circuit comprises a plurality of write driver units each comprising a plurality of write drivers adapted to provide respective programming currents to a corresponding block unit among the plurality of block units. The column selection circuit is connected between the memory cell array and the write driver circuit and is adapted to select at least one of the plurality of memory blocks in response to a column selection signal to provide corresponding programming currents to the at least one of the plurality of memory blocks.

Abstract: By using a resistive film as a shunt, the snapback exhibited when transitioning from the reset state or amorphous phase of a phase change material, may be reduced or avoided. The resistive film may be sufficiently resistive that it heats the phase change material and causes the appropriate phase transitions without requiring a dielectric breakdown of the phase change material.

Abstract: The magnetic memory device comprises a magnetoresistive effect element 54 including a magnetic layer 42 having a magnetization direction pinned in a first direction, a non-magnetic layer 50 formed on the magnetic layer 42, and a magnetic layer 52 formed on the non-magnetic layer 50 and having a first magnetic domain magnetized in a first direction and a second magnetic domain magnetized in a second direction opposite to the first direction; and a write current applying circuit for flowing a write current in the second magnetic layer 52 in the first direction or the second direction to shift a magnetic domain wall between the first magnetic domain and the second magnetic domain to control a magnetization direction of a part of the magnetic layer 52, opposed to the magnetic layer 42.

Abstract: Column redundancy data storage circuit blocks storing column redundancy data for repairing defective columns are arranged in correspondence to memory cell array blocks, respectively. The storage data of the column redundancy data storage circuits is transferred to redundancy data hold circuits arranged in spare column decoder bands adjacent to the data paths for transferring internal data, and are decoded for selection of a page in the spare decoder bands in column access. Therefore, it is possible to reduce the occupation area of a fuse program circuit which programs redundancy data for repairing a defective column.

Abstract: A system, method and program product for determining a history state of data in a data retaining device are disclosed. A state of a partially-depleted silicon-on-insulator (PD SOI) device coupled to a data retaining device is measured to indicate a body voltage of the PD SOI device. The body voltage of the PD SOI device may indicate, among others, how long the PD SOI device has been idling, which indirectly indicates how long data in the data retaining device has not been accessed. As such, the current invention may be used efficiently with, e.g., a cache replacement algorithm in a management of the data retaining device.

Abstract: A method and apparatus for reducing power consumption needed to refresh a memory may receive data having been encoded using data bus inversion (DBI), the DBI data having a first delta between a number of zeros for different cases between zero and a DBI maximum, balance code the DBI data to balance the number of zeros across the DBI data, and output data having a number of zeros for different cases between a minimum number greater than zero and less than or equal to the DBI maximum and a maximum number equal to the minimum number plus a second delta, the second delta being less than the first delta.

Abstract: The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as “program disturb.” A system is proposed for programming and/or reading non-volatile storage that reduces the effect of program disturb. In one embodiment, different verify levels are used for a particular word line (or other grouping of storage elements) during a programming process. In another embodiment, different compare levels are used for a particular word (or other grouping of storage elements) during a read process.

Abstract: The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as “program disturb.” A system is proposed for programming and/or reading non-volatile storage that reduces the effect of program disturb. In one embodiment, different verify levels are used for a particular word line (or other grouping of storage elements) during a programming process. In another embodiment, different compare levels are used for a particular word (or other grouping of storage elements) during a read process.

Abstract: An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.

Abstract: A non-volatile semiconductor memory device includes a page buffer comprising a lower latch block and an upper latch block, and a memory array that is connected to the lower latch block via a lower common bit line and that is connected to the upper latch block via an upper common bit line. The memory array includes a plurality of non-volatile memory cells, a lower even bit line and a lower odd bit line that are selectively connectable to the lower common bit line, an upper even bit line and an upper odd bit line that are selectively connectable to the upper common bit line, a first switch that electrically connects the lower even bit line to the upper even bit line in response to a first connection control signal and a second switch that electrically connects the lower odd bit line to the upper odd bit line in response to a second connection control signal.

Abstract: The present invention provides an improved SRAM cell. Specifically, the present invention provides an SRAM cell having one or more sets of stacked transistors for isolating the cell during a read operation. Depending on the embodiment, the SRAM cell of the present invention can have eight or ten transistors. Regardless, the SRAM cell of the present invention typically includes separate/decoupled write word and read word lines, a pair of cross-coupled inverters, and a complimentary pair of pass transistors that are coupled to the write word line. Each set of stacked transistors implemented within the SRAM cell has a transistor that is coupled to a bit line as well as the read word line.

Abstract: A multitude of NAND flash memory cells coupled to a bit line of a NAND flash memory array includes, in part, a highly doped source region coupled to a first terminal and a highly doped drain region coupled to a second terminal of the multitude of cells. Each NAND memory cell includes, in part, a first gate layer and a second gate layer both adapted to receive a voltage. The second gate layers of the NAND flash memory cells are connected to one another.

Abstract: The invention provides methods and apparatus. A portion of a memory array has a string of two or more non-volatile memory cells, a first select gate coupled in series with one non-volatile memory cell of the string of two or more non-volatile memory cells, and a second select gate coupled in series with the first select gate. A length of the second select gate is greater than a length of the first select gate.

Abstract: A semiconductor storage apparatus according to one embodiment of the present invention, comprising: cell arrays, each having a plurality of memory cells connected to a pair of first and second bit lines; and sense amplifiers, each being provided corresponding to the pair of first and second bit lines and sensing data read out from the memory cell to be read out, wherein each of the sense amplifiers includes a current mirror circuit having first and second current paths connected directly or indirectly to the pair of first and second bit lines; and the current mirror circuit includes: a first transistor which has a source and a drain short-circuited to each other and flows a reference current between the source and the drain; and a second transistor, of which gate is commonly connected to a gate of the first transistor, and which flows a current passing through the memory cell to be read out between a source and a drain thereof.

Abstract: A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circuit with the reference current supplied from the reference current generating circuit. A control section is supplied with an output signal of the sense amplifier. When verifying the threshold voltage of the memory cell, the control section causes the voltage generating circuit to generate verify voltage which is the same as readout voltage generated at the time of data readout from the memory cell.

Abstract: A method is provided for programming a block of memory cells of a non-volatile memory device. A first group of memory cells of the block of memory cells is selected. At least one programming pulse is programmed into all memory cells of the first group. A threshold level is detected for each one of the memory cells of the first group only. The first group of memory cells is verified by comparing each one of the detected threshold levels with predefined target levels provided for each one of the first group of memory cells.

Abstract: According to a method of erasing data in a non-volatile semiconductor memory device, block-round type overerase verify is performed. Specifically, overerase verify and write back are performed sequentially from a first address to a last address. That is, even when a write back pulse is applied after a certain address is selected and verify is performed, address increment from one address to another is performed, regardless of whether verify has been performed or not. Therefore, it is not that the same address is cumulatively rewritten, but write back to a memory cell corresponding to a defective address is sequentially and gradually performed. Accordingly, as write to a memory cell in an overerased state can evenly be performed, influence by off-leakage is suppressed, and a memory cell having threshold voltage distribution with less variation can be implemented.

Abstract: A voltage regulator with a low noise discharge switch is used in non-volatile memory electronic devices, such as for discharging word lines from negative voltage potentials. The voltage regulator includes a first circuit portion with transistors for transforming a first voltage to a second voltage. The second voltage is applied to a second circuit portion with transistors. The output of the first circuit portion is coupled to ground by a discharge transistor. A third circuit portion with transistors receives a third voltage transformed, starting from the second voltage for biasing at least one word line connected downstream of the third circuit portion. A circuit portion with a discharge switch incorporates the discharge transistor, and further includes a pair of transistors connected in series to each other by an interconnection node. The interconnection node is connected to the body terminal of the discharge transistor.

Abstract: A semiconductor flash memory includes an erase/write control unit that, when performing an erase/write operation of read memory cells, reads and senses memory current of the read memory cells for each memory cell, and adjusts threshold voltage of each of the read memory cells to a predetermined value, and a readout control unit that, when performing a read operation, selects at least two read memory cells simultaneously from among the read memory cells to which the erase/write control unit stored the same data, and senses total memory current for the at least two read memory cells.

Abstract: The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as “program disturb.” A system is proposed for programming and/or reading non-volatile storage that reduces the effect of program disturb. In one embodiment, different verify levels are used for a particular word line (or other grouping of storage elements) during a programming process. In another embodiment, different compare levels are used for a particular word (or other grouping of storage elements) during a read process.

Abstract: An operating method of a non-volatile memory is provided. The non-volatile memory includes plural memory cells. Each memory cell includes a charge storage structure, a gate, and a source and a drain disposed in the well on the both sides of the gate. During an erasing operation, a first voltage is applied to the source of the selected memory cell, a second voltage is applied to the gate of each selected memory cell, and a third voltage is applied to the well; and the drain of the selected memory cell is floated, so that the selected memory cell is erased. In the meantime, the fourth voltage is applied to the drain of each unselected memory cell, the fifth voltage is applied to the gate of the unselected memory cell, and the source of the unselected memory cell is floated to prevent the unselected memory cell from being erased.

Abstract: The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as “program disturb.” A system is proposed for programming and/or reading non-volatile storage that reduces the effect of program disturb. In one embodiment, different verify levels are used for a particular word line (or other grouping of storage elements) during a programming process. In another embodiment, different compare levels are used for a particular word (or other grouping of storage elements) during a read process.

Abstract: A method for erasing data of a flash memory is disclosed. The flash memory includes a plurality of memory cells coupled to a word line, where each of the memory cells has a substrate, an isolated carrier storage layer, and a control gate coupled to the word line. And the method includes: coupling the substrate to a first voltage to increase a voltage level of the substrate; before erasing data, floating the control gate to make a voltage level of the control gate increase with the voltage level of the substrate; and coupling the control gate to a second voltage via the word line to discharge charges on the isolated carrier storage layer for erasing data.

Abstract: According to the present invention, there is provided a semiconductor memory comprising a memory cell which is a MOSFET formed on an SOI substrate and having a gate electrode connected to a word line, a drain region connected to a bit line, and a grounded source region, wherein an operation of reading out data written in said memory cell is performed under a biasing condition by which a relationship Vd>Vg?Vth0 holds between a gate voltage Vg to be applied to said gate electrode, a drain voltage Vd to be applied to said drain region, a threshold voltage Vth1 of said MOSFET when a predetermined amount of holes are stored in a body region of said memory cell, and a threshold voltage Vth0 of said MOSFET when holes whose amount is smaller than the predetermined amount are stored in said body region.

Abstract: In a memory cell array, a plurality of memory cells are arranged in a matrix. Each of the plurality of memory cells stores one of a plurality of threshold levels. When writing one of the plurality of threshold levels into a first memory cell of the memory cell array, a control circuit writes a threshold level a little lower than the original threshold level. When not writing a second memory cell adjacent to the first memory cell consecutively, the control circuit writes the original threshold level into the first memory cell.

Abstract: A nonvolatile semiconductor memory device comprises a memory cell array in which memory cells are arranged in a row and column direction, a circuit for applying a first voltage to a selected bit line, a circuit for applying a second voltage to unselected bit lines and word lines, a circuit for reading a current flowing in a selected memory cell, a voltage suppressor circuit for suppressing fluctuation of the second voltage with respect to each word line and bit line provided in the circuit for applying the second voltage, and a second voltage control circuit for applying the first voltage to the selected bit line and a dummy second voltage to the unselected bit lines and the word lines during the preset period and controlling the voltage suppressor circuit during a reading period so that the second voltage may fluctuate in a fluctuation direction of the first voltage.

Abstract: The invention relates to accessing contents of memory cells. Some embodiments include a memory structure that has a first cell, a second cell, and a sense amplifier. The first cell stores a first value. The first and second cells are connected to the sense amplifier by one or more bit lines. The sense amplifier receives the first value stored by the first cell by using the one or more bit lines and drives the received first value to the second cell through the one or more bit lines. The receiving and driving occur in a single clock cycle. In some embodiments, the second cell outputs the first value. The memory structure of some embodiments also includes a third cell connected to the sense amplifier by the one or more bit lines. The sense amplifier drives a second value to the third cell while the second cell outputs the first value. Other embodiments include a method for accessing data in a memory structure. The method receives a value stored by a first cell; and drives the received value to a second cell.

Abstract: A memory controller includes a first data converter for converting incoming data into a first data in which a bit width of the incoming data and a bit width of the first data corresponds to a first ratio; a second data converter for converting the incoming data into a second data where the bit width of the incoming data and a bit width of the second data corresponds to a second ratio; and a first selector, coupled to the first and second data converters, for outputting either the first data or the second data to a memory device according to a memory mode setting.

Abstract: A writing apparatus of a semiconductor memory device includes a pulse generator, a latch unit and an output latch unit. The pulse generator outputs a first pulse every rising edge of a data strobe pulse and a second pulse every falling edge of the data strobe pulse, respectively. The latch unit latches data input every rising edge of the first pulse, latches data input every rising edge of the second pulse and the latched data, respectively, and allocates the latched data to first and second data lines. The output latch unit latches data, which are firstly allocated to the first and second data lines, in response to a first control signal, and latches data, which are secondly allocated to the first and second data lines, in response to a second control signal.

Abstract: An integrated circuit memory device includes a first set of pins and a memory core. The first set of pins receive, using a clock signal, a write command and a read command. Control information is issued internally in response to the write command after a predetermined delay time transpires following receipt of the write command, the control information initiating the write operation in the memory device. A second set of pins output the read data after a first delay time transpires from when the read command is received. Each pin of the second set of pins outputs two bits of read data during a clock cycle of the clock signal. The second set of pins also receive write data after a second delay time has transpired from when the write command is received. The second delay time is based on the first delay time.

Abstract: A memory access apparatus reading data from a memory, the memory including a terminal that address information is input to, a terminal that a clock signal changing at a predetermined cycle is input to, a terminal that a read command is input to, and a terminal that outputs data stored at an address identified by the address information at a timing of the clock signal changing from one level to the other level in accordance with the read command, the memory access apparatus comprising: an address information output unit that outputs the address information and the read command at a first timing of the clock signal changing from the one level to the other level; and a read data storage unit that stores data output from the memory at a second timing after the first timing of the clock signal changing from the one level to the other level, the read data storage unit storing the data at a third timing after the second timing of the clock signal changing from the one level to the other level.

Abstract: A method for operating a memory device includes selecting a cell comprising an array of word lines, selecting a word line within said array and applying an operating voltage to said selected word line. A shielding voltage is also applied to the closest adjacent facing word line of said selected word line. This may prevent unintended, program, read, or erase of said unselected word line. The remainder of unselected word lines can be floated.

Abstract: A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.

Abstract: A reference potential generating circuit has a current mirror amplifier (CM11) supplied with an input reference potential and a feedback level, an output transistor (QP11) supplied with an output of the current mirror amplifier as an input and producing an output reference potential as an output, a monitoring portion (R11 and R12) for generating the feedback level from the output of the output transistor, a first switch (QN11) for controlling supply of a power supply potential (VSS}) to the current mirror amplifier, a second switch (QN12) for controlling supply of the power supply potential (VSS) to the monitoring portion, and an output switch (TSW12) for controlling connection of the output of the output transistor to a next stage. The first and the second switches and the output switch are simultaneously turned off. When a first predetermined period elapses after the first and the second switches and the output switch are turned off, the first and the second switches are turned on.

Abstract: A radiation hardened memory element includes at least two delay elements for maintaining radiation hardness. In an example, the memory element is an SRAM cell. Both delays are coupled together in series so that if either one of the delays fails, a delay will still be maintained within the SRAM cell. The critical areas of the delays may be positioned so that a common line of sight cannot be made between each delay and a circuit node.

Abstract: A test circuit used for determining a fault in a memory device. The test circuit includes a read circuit configured to read memory cell contents in a memory device at a first time instant and second time instant. The test circuit includes a comparator that compares the contents at the first and second time instants. If the contents are different from one another, the comparator indicates that a fault has occurred. Test methods are also used to determine if a fault has occurred in a memory cell.

Abstract: A semiconductor memory device includes first and second global bit lines; first, second, third and fourth local bit lines; first, second, third and fourth hierarchical switches for respectively connecting the first global bit line and the first local bit line to each other, the second global bit line and the second local bit line to each other, the first global bit line and the third local bit line to each other, and the second global bit line and the fourth local bit line to each other; and first and second precharge circuits for respectively precharging the first and second global bit lines. When a memory cell connected to the first local bit line is read, the third hierarchical switch is turned off, and the first precharge circuit terminates its precharge operation after the third hierarchical switch is turned off and before a selected word line connected to the memory cell to be read is activated.

Abstract: A semiconductor memory device includes a thermosensor that senses present temperatures of the device and confirms whether the temperature values are valid. The thermosensor includes a temperature sensing unit, a storage unit and an initializing unit. The temperature sensing unit senses temperatures in response to a driving signal. The storage unit stores output signals of the temperature sensing unit and outputs temperature values. The initializing unit initializes the storage unit after a predetermined time from an activation of the driving signal. A driving method includes driving the thermosensor in response to the driving signal, requesting a re-driving after a predetermined time from the activation of the driving signal, and re-driving the thermosensor in response to the driving signal input again.

Abstract: A sensing circuit for a semiconductor memory, comprising at least one detecting amplifier, said detecting amplifier comprising: a first circuital branch adapted to be electrically run through by a first current corresponding to the sum of a second current as a function of a comparison current and a cell current, said cell current being a function of a state of a memory cell to be read in a predetermined biasing condition; a second circuital branch coupled as a current mirror configuration with the first circuital branch, said second circuital branch being adapted in the operation to be run through by a third current proportional to the first current; a third circuital branch coupled to said second branch, said third circuital branch being adapted in the operation to sink a fourth current as a function of said comparison current; a fourth circuital branch coupled to said second and third circuital branches, said fourth circuital branch being adapted in the operation to be run through by a residual current equa

Abstract: A memory operable at a high speed is obtained. This memory comprises a plurality of word lines, first transistors each connected to each the plurality of word lines for entering an ON-state through selection of the corresponding word line, a plurality of memory cells including diodes having cathodes connected to the source or drain regions of the first transistors respectively and a data determination portion connected to the drain or source regions of the first transistors for determining data read from a selected memory cell.

Abstract: Circuits and method for precharging a pair of complementary bitlines in a dynamic random access memory (DRAM). Both bitlines are precharged to VDD during a precharge phase, and during a sensing phase, the voltage of one of the pair of complementary bitlines is adjusted from VDD to a reference level. The reference level is generated by coupling the one of the pair of complementary bitlines to a capacitance means located within a reference voltage circuit. The reference voltage circuit can include one capacitor element or a plurality of capacitor elements connected in parallel with each other. Any number of the plurality of capacitor elements can be selectively enabled.

Abstract: A memory system is provided. The memory system includes a volatile memory having a number of banks and a memory controller configured to control the volatile memory to engage in an auto-refresh mode or a self-refresh mode. The memory controller is further configured to direct the volatile memory to perform an auto-refresh operation on a target bank. The remaining banks are available for access while the auto-refresh operation is being performed on the target bank.

Abstract: Through setting an internal test mode, a refresh operation for a DRAM is carried out by externally inputted address signals, instead of internally generated address signals, while maintaining the same number of memory cell arrays to be activated as that of memory cell arrays which are concurrently activated in a refresh for memory cell arrays. This configuration needs no drastic addition of circuits and allows a reduction in disturb test time for a plurality of memory cell arrays.

Abstract: A semiconductor memory device is comprised of a refresh counter for sequentially generating a count value indicating one or more row addresses corresponding to one or more word lines to be refreshed when receiving a refresh request at a predetermined interval in normal operation, in which the refresh counter includes n+1 stage counters assigned to n bits included in the row address and a dummy bit not included in the row address, and a counter portion from the least significant bit to the dummy bit forms an N-ary counter, so as to control whether or not refresh is performed in response to a value of the dummy bit when receiving the refresh request.