Abstract: A signal transmission system is provided which is capable of simplifying circuits and shortening time required for automatic adjustment of pre-emphasis. A signal having a single pulse pattern is generated by a single pulse pattern generating circuit. A signal having passed through a selector is divided into two signals whose phases are inverted and which are transmitted to a receiving circuit. An eye aperture of an eye waveform in a direction of time is measured by an eye aperture judging section by using the two signals and a sampling clock output from a sampling clock controlling section. An adjustment controlling section compares the measured eye aperture with a target value for judgment and transmits the judgment result to the transmitting circuit, where pre-emphasis is adjusted based on the judgment result.

Abstract: An open drain output circuit for use as an I2C bus interface. The open drain output circuit includes an output terminal. An input unit performs a first operation causing the potential at the output node to steeply fall and a second operation for gradually raising the potential in accordance with transition of an input signal. An output transistor connected to the output node of the input unit and the output terminal is turned OFF in the first operation and turned ON in the second operation. A delay time adjustment circuit reduces the difference between a delay time from transition of the input signal until when the output transistor is turned OFF in the first operation and a delay time from transition of the input signal until when the output transistor is turned ON in the second operation.

Abstract: An output buffer circuit, which minimizes or prevents output delay of output signal and degradation of slew rate while suppressing overshoot and undershoot, is provided. In a first time period when an input signal to a gate of an N-channel output transistor changes from ‘L’ level to ‘H’ level, the gate is connected to an output terminal through a capacitor element so that the overshoot is suppressed. In addition, the output buffer circuit stores negligible electrical charge in the capacitor element prior to the first time period, which results in minimal delay in outputting a buffered signal and degradation of slew rate while suppressing undershoot when the input signal changes from ‘H’ level to ‘L’ level in the first time period.

Abstract: An output buffer for driving an AC-coupled resistively terminated transmission line comprises at least first and second drive circuits coupled to an input signal and providing respective drive signals that transition in response to respective transitions of the input signal. The buffer is arranged such that, in response to a given input signal transition, the second drive signal transitions a predetermined amount of time after the first drive signal. The first and second drive signals are summed together to provide the buffer's output signal. The drive circuits are arranged such that the output signal has a first slew rate prior to the transition of the second drive signal, and a second, faster slew rate during the transition of the second drive signal, such that the slew rates reduce ringing that might otherwise occur on the transmission line.

Abstract: A system and method for generating multiple current steered output signals at a centralized location and subsequently routing them to their respective output pads is shown and described. The system and method allow designers to variously stagger output pad configurations while maintaining low output-to-output skew and low jitter.

Abstract: A circuit and method for configuring a circuit is disclosed. In one embodiment, the circuit includes at least one pull-down path, wherein an amount of a current flowing through the pull-down path is determined by a switchable resistivity value of a switchable resistor that is included by the circuit. The invention further provides method for configuring a circuit and to a logic circuit.

Abstract: Various types of memory circuits are described. A memory circuit may include a state-storage feedback loop coupled to a clock input and to a data input. The data input is introduced into the feedback loop at multiple points, and propagated in parallel from those points to other points in the feedback loop.

Abstract: A window comparator of an A.C. input voltage, including, between two terminals of application of a voltage representative of the voltage to be measured, two first transistors of a first type, each first transistor being assembled as a current mirror on the second transistor having a first conduction terminal connected to one of the application terminals, the two second transistors having a second common conduction terminal; and two third transistors of a second type assembled as a current mirror between the common conduction terminal of the second transistors and a current source, a D.C. voltage being applied on a first terminal of the current source and an output signal being provided by a second terminal of the current source.

Abstract: An enhanced phase-locked loop (PLL) apparatus having an aligning unit and method are described. The PLL comprises an aligning unit, a phase difference detecting unit, a charge pump, a loop filter, and a voltage-controlled oscillator. The aligning unit receives a hold signal and a reference signal for shifting an edge of the hold signal to generate the gating signal. The phase difference detecting unit detects a phase difference between the reference signal and a feedback signal and outputting an UP signal and a DOWN signal for representing the phase difference. The edge of the hold signal is aligned to an edge of the reference signal. The charge pump generates a current signal based on the UP and DOWN signals. The loop filter is used to generate a control voltage based on the current signal. The voltage-controlled oscillator receives the control voltage and generates an output signal serving as the feedback signal.

Abstract: A phase-locked loop (PLL) is disclosed. One embodiment, among others, includes a PLL that provides a control signal and a square root module configured to receive state information, the state information corresponding to tuning information, the square root module further configured to multiply the control signal by a square root of the state information to provide a tuning signal.

Abstract: A delay lock clock synthesizer comprises: an adjustable delay circuit for receiving an input clock and for generating an output clock having a phase offset controlled by a control signal; a phase detector for detecting a phase difference between the input clock and the output clock and for generating a phase error signal representing the phase difference; a summing circuit for summing the phase error signal and a phase offset signal into a modified phase error signal; and a filter for filtering the modified phase error signal to generate the control signal to control the adjustable delay circuit.

Abstract: An apparatus for generating an output clock is disclosed. The apparatus comprises: N variable offset clock circuits for receiving N input clocks and for generating N intermediate clocks having N phase offsets controlled by N intermediate signals, respectively, where N>1; a clock multiplexer for selecting one of the N intermediate clocks as the output clock according to a finite-state signal having N possible states; and a finite-state-machine for receiving a control signal and the N intermediate clocks and for generating the finite-state signal and the N intermediate signals.

Abstract: The digital duty cycle correction circuit according to the present invention includes a first conversion circuit for buffering an internal clock output from a delay locked loop (DLL), converting the buffered internal clock into first and second clocks through first and second terminals, delaying the second clock according to voltage supplied to the second terminal through a capacitor, converting the delayed second clock into a first signal, and converting the first clock into a third clock, which rises at a falling edge of the first clock and falls at a rising edge of the first signal; and a second conversion circuit for converting the third clock into an output clock, which rises at a falling edge of the third clock and falls at a rising edge of the third clock.

Abstract: A start up circuit includes: a NOT gate; a capacitor coupled to an output of the NOT gate; a first switch for determining whether or not to couple an input of the NOT gate to an operating voltage source according to the output of the NOT gate; a control circuit for switching logic level of the input of the NOT gate when the input of the NOT gate is coupled to the operating voltage source over a predetermined period; and a start signal generator coupled to the NOT gate for generating at least one start up signal according to the input or the output of the NOT gate.

Abstract: A phase splitter that receives an external clock signal and that generates first and second internal clock signals having a phase difference of 180° between the first and second internal clock signals, the phase splitter including: a first buffer that buffers the external clock signal and outputs a first signal; an inverting unit that inverts the external clock signal and outputs a second signal; a second buffer that buffers the second signal and outputs a third signal; a first interpolating signal generator that inverts the external clock signal and outputs a fourth signal; and a second interpolating signal generator that inverts the second signal and outputs a fifth signal. The first signal and the fifth signal are interpolated to generate the first internal clock signal. The third signal and the fourth signal are interpolated to generate the second internal clock signal.

Abstract: Aspects of the disclosure embody methods and circuits for delaying a trigger signal. In one embodiment, a trigger delay circuit receives a trigger-in signal, delays some predetermined and programmable time delay and then outputs a trigger-out signal. The trigger delay circuit, in one embodiment, includes a programmable trigger circuit that time stamps the input trigger signal, delay for a predetermined time, and output the output trigger signal after the predetermined time.

Abstract: The invention is related to an apparatus and a method for generating an output clock. The method comprises: receiving a transmitted signal comprising at least one data signal and at least one synchronized signal; producing a reference signal according to the synchronization signal; counting the first reference signal according to a free-run clock outputted by a free-run clock generator to produce a counter signal; and generating the output clock according to the counter signal and the free-run clock.

Abstract: An offset correcting circuit includes: an amplifying unit including an offset adjusting unit that adjusts an offset of the amplifying unit; and an offset determining unit that that detects the offset of the amplifying unit outputs a signal for correcting the offset of the amplifying unit. The offset determining unit includes a comparing unit that compares an output of the amplifying unit with a reference value, and a counter that increases or decreases a count value in response to an output of the comparing unit. The offset adjusting unit adjusts the offset based on the count value and includes a bias varying portion for varying a bias of the amplifying unit based on the output of the counter.

Abstract: A voltage level shifter apparatus is provided. The voltage level shifter apparatus includes a first dynamic-bias generator, a second dynamic-bias generator, and a level supply circuit. The first dynamic-bias generator dynamically outputs a first bias signal, wherein the level of the first bias signal is determined in accordance with the received input data signal. The second dynamic-bias generator outputs a second bias signal, wherein the level of the second bias signal is determined in accordance with the received input data signal. Besides receiving the input data signal, the level supply circuit is further coupled to the first dynamic-bias generator and the second dynamic-bias generator for receiving the first bias signal and the second bias signal, and generating the output data signal in accordance with the input data signal, the first bias signal, and the second bias signal.

Abstract: In a level shift circuit, the threshold voltage of N-type high-voltage transistors, to whose gates the voltage of a low-voltage supply VDD is applied, is set low. An input signal IN powered by the low-voltage supply VDD is input to the gate of an N-type transistor by way of an inverter. Therefore, even if the potentials at nodes W3 and W4 exceed the voltage of the low-voltage supply VDD, reverse current flow from the nodes W3 and W4 via parasitic diodes within the inverters into the low-voltage supply VDD is prevented. A protection circuit, composed of N-type transistor whose respective gates are fixed to the low-voltage supply VDD, is disposed between the two N-type high-voltage transistors N5, N6 and two N-type low-voltage transistors N1, N2 for receiving the complementary signals IN and XIN, thereby preventing the breakdown of those N-type complementary-signal-receiving transistors.

Abstract: A switch includes at least two signal ports in series with a series FET connected therebetween, and a shunt path having an FET, whereby an input bias is applied to a gate on the series FET and to a drain on the shunt FET. In one embodiment, the switch includes a control signal input, an FET connected in series across the first port and the second port, the series FET having a gate coupled to the control signal input, and a shunt path provided by an FET, the shunt FET having a drain coupled to the control signal input and to the gate of the series FET, whereby a single control signal is applied to both the series FET and the shunt FET, via the control signal input, in order to turn the series FET on and simultaneously turn the shunt FET off and, conversely, in order to turn the series FET off and simultaneously turn the shunt FET on.

Abstract: A transistor cell is provided that includes transistors arranged to turn on for different voltages applied to a control terminal of the transistor cell. The transistor cell can include a first transistor having a gate, a source, and a drain, and a second transistor having a gate, a source, and a drain, wherein the source of the second transistor is coupled to the source of the first transistor, and the drain of the second transistor is coupled to the drain of the first transistor. The transistor cell can further include a first resistor coupled between the gate of the first transistor and the gate of the second transistor. A frequency mixer is also provided that includes at least one transistor cell.

Abstract: An apparatus and method for manufacturing metal-oxide semiconductor (MOS) transistors that are operable at voltages below 1.5V, which MOS transistors are area efficient, and where the drive strength and leakage current of the MOS transistors is improved. The invention uses a dynamic threshold voltage control scheme that does not require a change to the existing MOS technology process. The invention provides a technique that controls the threshold voltage of the transistor. In the OFF state, the threshold voltage of the transistor is set high, keeping the transistor leakage to a small value. In the ON state, the threshold voltage is set to a low value, resulting in increased drive strength. The invention is particularly useful in MOS technology for both bulk and silicon on insulator (SOI) CMOS.

Abstract: A method for controlling a charge pump having a plurality of switches, wherein the charge pump is for supplying a working voltage to a following stage, the method includes: adjusting the timing of a clock signal to generate an adjusted clock signal synchronized with a current consumption period of the following stage; generating a plurality of control signals according to the adjusted clock signal; and controlling the switching timings of the plurality of switches according to the plurality of control signals.

Abstract: The voltage source and current source circuits including an amplifier, a first current mirror circuit, a first PMOS transistor, a second current mirror circuit and a NMOS transistor are provided. The amplifier has a positive input terminal and a negative input terminal coupled to the source terminal of the NMOS transistor. The first current mirror circuit is coupled to a reference current and duplicates the reference current to the source terminal of the first PMOS transistor. The first PMOS transistor has a drain terminal, a gate terminal and a source terminal. The drain terminal of the NMOS transistor is coupled to the third current terminal, and the gate terminal of the NMOS transistor is coupled to the source terminal of the first PMOS transistor. The second current mirror circuit duplicates the current from the third current terminal.

Abstract: A method, system, module, apparatus, use, and computer program product are shown for determining a supply voltage level for operating an integrated circuit. To allow exact voltage level calibration, a high load condition is provided to the integrated circuit, a first voltage level of the integrated circuit is adjusted to provide a stable operation of the integrated circuit in the high load condition, a temperature of the integrated circuit in the high load condition is measured, the measured temperature in the high load condition is stored along with the adjusted first voltage level in the high load condition.

Abstract: Methods and systems for vector combining power amplification are disclosed herein. In one embodiment, a plurality of signals are individually amplified, then summed to form a desired time-varying complex envelope signal. Phase and/or frequency characteristics of one or more of the signals are controlled to provide the desired phase, frequency, and/or amplitude characteristics of the desired time-varying complex envelope signal. In another embodiment, a time-varying complex envelope signal is decomposed into a plurality of constant envelope constituent signals. The constituent signals are amplified equally or substantially equally, and then summed to construct an amplified version of the original time-varying envelope signal. Embodiments also perform frequency up-conversion.

Abstract: A DC offset canceling apparatus includes a main amplifier, a replica amplifier, a switch, and a storage unit. The replica amplifier has substantially the same structure as the main amplifier, receives an input signal having the same sign as that of a signal input to the main amplifier, and has an output connected to main amplifier with an opposite sign. The switch switches a signal input to the replica amplifier in response to a control signal. The storage unit is connected to an input terminal of the replica amplifier to maintain a DC value for a predetermined period of time when the switch is open.

Abstract: The present invention discloses a switching amplifier, comprising a modulator for converting a main input signal to a high frequency modulated switching signal and for providing voltage amplification of the main input signal. The present invention further includes a power output stage coupled with an output of the modulator for receiving the voltage amplified main input signal and for providing a current amplification of the main input signal for providing a main output signal for deriving a load. Further included is a feedback module for correction of the main output signal in relation to the main input signal.

Abstract: Methods and systems for vector combining power amplification are disclosed herein. In one embodiment, a plurality of signals are individually amplified, then summed to form a desired time-varying complex envelope signal. Phase and/or frequency characteristics of one or more of the signals are controlled to provide the desired phase, frequency, and/or amplitude characteristics of the desired time-varying complex envelope signal. In another embodiment, a time-varying complex envelope signal is decomposed into a plurality of constant envelope constituent signals. The constituent signals are amplified equally or substantially equally, and then summed to construct an amplified version of the original time-varying envelope signal. Embodiments also perform frequency up-conversion.

Abstract: Methods and systems for vector combining power amplification are disclosed herein. In one embodiment, a plurality of signals are individually amplified, then summed to form a desired time-varying complex envelope signal. Phase and/or frequency characteristics of one or more of the signals are controlled to provide the desired phase, frequency, and/or amplitude characteristics of the desired time-varying complex envelope signal. In another embodiment, a time-varying complex envelope signal is decomposed into a plurality of constant envelope constituent signals. The constituent signals are amplified equally or substantially equally, and then summed to construct an amplified version of the original time-varying envelope signal. Embodiments also perform frequency up-conversion.

Abstract: Methods and systems for vector combining power amplification are disclosed herein. In one embodiment, a plurality of signals are individually amplified, then summed to form a desired time-varying complex envelope signal. Phase and/or frequency characteristics of one or more of the signals are controlled to provide the desired phase, frequency, and/or amplitude characteristics of the desired time-varying complex envelope signal. In another embodiment, a time-varying complex envelope signal is decomposed into a plurality of constant envelope constituent signals. The constituent signals are amplified equally or substantially equally, and then summed to construct an amplified version of the original time-varying envelope signal. Embodiments also perform frequency up-conversion.

Abstract: A PWM circuit converts output data of a calculator to a pulse width modulation signal, and outputs it to a load (speaker) through a buffer amplifier and a low-pass filter. A digital low-pass filter has the same filter characteristic as a low-pass filter. An error calculator calculates the error ?(z) between the input data and the output of the filter, and outputs it to the calculator. The output of the filter becomes a digital signal having substantially the same digitalized waveform as an analog signal applied to the load, and also no distortion contains in the digital signal. Accordingly, the output data ?(z) of the error calculator becomes data corresponding to the distortion of the output signal. In the calculator, the data ?(z) is subtracted from the input data, and the subtraction result is applied to the PWM circuit to reduce the distortion.

Abstract: A sensor device includes a moveable object, at least one magnetically encoded region provided on the moveable object, at least one magnetic field detector adapted to detect a signal originating from the magnetically encoded region, and a sensor electronic adapted to perform automatic offset compensation.

Abstract: A switching circuit for power converters is presented. It includes a voltage-clipping device, a resistive device, a first transistor and a second transistor. The voltage-clipping device is coupled to an input voltage. The first transistor is connected in series with the voltage-clipping device for switching the input voltage. The second transistor is coupled to control the first transistor and the voltage-clipping device in response to a control signal. The resistive device provides a bias voltage to turn on the voltage-clipping device and the first transistor when the second transistor is turned off. Once the second transistor is turned on, the first transistor is turned off and the voltage-clipping device is negatively biased. The voltage-clipping device is developed to clamp a maximum voltage for the first transistor.

Abstract: A corrector circuit for correcting second harmonic distortions is provided. The corrector circuit includes a transconductance circuit having an input transconductance with a transresistance load for receiving a distorted voltage signal having a second harmonic component. The transconductance circuit is adapted to generate a corrected voltage signal having the second harmonic component that is reduced from the distorted voltage signal as a function of the input transconductance. The corrector circuit further includes biasing means for providing a biasing current to the transconductance circuit (with the input transconductance that depends on the biasing current). The biasing means includes means for providing a fixed component of the biasing current, means for providing a variable component of the biasing current (being a function of the distorted voltage signal according to a proportionality coefficient) and means for programming the proportionality coefficient.

Abstract: Amplifier circuitry includes an input stage having a transconductance stage including first and second input transistors and a first tail current source, gates of the first and second input transistors being coupled to first and second input signals, respectively. A bulk electrode capacitance driver includes third and fourth input transistors and first and second associated cascode transistors and a second tail current source coupled to the sources and bulk electrodes of the third and fourth input transistors and to the bulk electrodes of the first and second input transistors. The gates of the third and fourth input transistors are coupled to the first and second input voltage signals, respectively, and the gates of the first and second cascode transistors are coupled to the second and first input voltage signals, respectively.

Abstract: In some embodiments an apparatus includes an amplifier, a first inverter having an input coupled to an output of the amplifier, and a second inverter having an input coupled to an output of the first inverter and an output, where the output of the second inverter is fed back to an input of the amplifier. Other embodiments are described and claimed.

Abstract: In some embodiments an apparatus includes an amplifier, a first inverter having an input coupled to an output of the amplifier, and a second inverter having an input coupled to an output of the first inverter and an output, where the output of the second inverter is fed back to an input of the amplifier. Other embodiments are described and claimed.

Abstract: A gate leakage insensitive current mirror circuit including an input stage, an output stage, and a pair of complementary source followers. The pair of complementary source followers is connected between the input stage and the output stage. In operation, the input stage receives an input current and the pair of complementary source followers receives a first current source and a second current source. The output stage then provides an output current. The complementary source followers form a negative feedback loop and establish a bias voltage for the input stage and the output stage as a function of the input current that is independent of gate leakage between the input stage and the output stage.

Abstract: Systems are disclosed for providing a DC-bias network for a RF distributed amplifier. One embodiment may include a DC-bias network comprising a planar substrate having an input port configured to receive a DC input signal and provide a DC bias at an output port, a microstrip line mounted to the planar substrate and interconnecting the input port and the output port, and a plurality of RF resonators coupled to the microstrip line.

Abstract: An EER high frequency amplifier wherein the dynamic range of the gain can be widened by performing a predetermined control of a device in a high frequency amplifying part and thereby enhancing the isolation within the device. In an EER high frequency amplifier (1), an envelope detecting part (2) extracts an amplitude signal from an input high frequency signal, while a limiter (3) extracts a phase signal therefrom. A baseband amplifying part (4) generates a voltage in accordance with the amplitude signal and supplies it as the drain voltage of a GaAs FET (5a) of a high frequency amplifying part (5). When the drain voltage is below a predetermined first reference voltage, a gate voltage control part (6) holds an initially established gate voltage. When the drain voltage exceeds the first reference voltage, the gate voltage control part (6) so controls the gate voltage as to be proportional to the drain voltage.

Abstract: A fractional-N synthesizer system including a plurality of fractional-N synthesizers all updated to simultaneously generate an output frequency from the same reference frequency, a phase locked loop having an output signal whose frequency is a fractional multiple of the input reference frequency; the phase locked loop including a frequency divider, an interpolator responsive to an input fraction to provide to the frequency divider an output which has a fractional value equal to on average, the input fraction; and a timeout circuit responsive to the reference frequency for generating an output a predetermined time after updating to initialize the interpolator in each synthesizer to the same start conditions for locking together the phase of the frequency outputs of all of the synthesizers at the updated frequency.

Abstract: A method for operating a Phase Locked Loop (PLL) that mitigates radiation event influence on a phase signal. The method is implemented on a PLL having two loop filters. The first filter is a proportional (resistive) loop filter that is operated so that it scales and/or clips the influence out of the phase signal and produces a fine tuning signal. The second filter, on the other hand, is an integral (capacitive) loop filter that dampens the influence and produces a coarse tuning signal. A summing node may then combine the fine and coarse tuning signals and communicate the combined output signal to a VCO. Because the phase signal has been separately filtered, the VCO produces a waveform that is less prone to cause the PLL to report a loss of lock.

Abstract: Various embodiments are disclosed relating to calibration techniques for a phase-locked loop (PLL) bandwidth. According to an example embodiment, a calibration technique may include calibrating a voltage-controlled oscillator (VCO) of a phase-locked loop (PLL) circuit, and calibrating a bandwidth of the PLL circuit based on the calibrating the VCO.

Abstract: Phase-locked loop circuitry includes charge pump circuitry, loop filter circuitry, and drag current circuitry. The charge pump circuitry generates a charge pump current based on a phase of an input signal. The loop filter circuitry receives the charge pump current. The drag current circuitry generates a drag current to draw charge in the opposite direction from the charging current from a loop filter integration capacitor in the loop filter circuitry that does not include voltage sensing circuitry.

Abstract: A circuit reducing the capacitance of a switched capacitor array by mitigating switch capacitance. Reducing the effect of switch capacitance increases the frequency range of an inductor-capacitor tank containing the switched capacitor array. A pull-up circuit is coupled between a voltage source and a node. A switched capacitor and a switch are coupled to the node. The pull-up circuit biases the switch to reduce switch junction capacitance when the switch is off. In an example, a pull-up resistor is coupled between the node and a voltage source to bias the switch. In another example, a pull-up switch and pull-up resistor are coupled between the node and a voltage source to bias the switch.

Abstract: A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL.

Abstract: A modulator, comprising an input unit configured to receive a modulating signal, a control unit configured to provide a control signal on the basis of the modulating signal, an oscillating unit configured to provide a plurality of instances of at least two phase components of a carrier frequency signal, a phase selector configure to select, on the basis of the control signal, a combination of the phase component instances so that an output signal representing the information contents of the modulating signal is obtained, and a combiner configured to combine the selected phase component instances to form a modulated output signal.

Abstract: A ring oscillator for generating an output signal, comprising a plurality of serially connected main elements for selectively delaying a signal input thereto, each of the plurality of main elements having two circuit paths, a first path including at least one time-delay element for delaying a signal input thereto and a second circuit path bypassing the first circuit path; and a multiplexor (MUX) having a first input coupled to the first circuit path including the at least one time-delay element and a second input coupled to the second circuit path, the MUX selecting the first or second inputs of a plurality of inputs and outputting an output signal.