Abstract: An I/O buffer circuit including: a driver circuit containing a pull-up device in a first floating well and a pull-down device in a second floating well; a first and second biasing circuits to bias the first and second floating wells in response to voltages internal and external to the I/O buffer circuit; and a first and second tracking circuits to bias each of said pull-up and pull-down devices in response to voltages internal and external to the I/O buffer circuit in a shutdown mode.

Abstract: In a semiconductor integrated circuit, one of two signals generated from a first logic circuit is delayed in a first delay addition circuit, looped back by an input/output terminal, and then inputted to a second logic circuit. The other output of the first logic circuit is looped back by a reference input/output terminal, further delayed in a second delay addition circuit, and then inputted to the second logic circuit. By varying respective amounts of delay added by the first and second delay addition circuits from each other, AC timing specifications are satisfied and it is determined whether or not the semiconductor integrated circuit has passed a test based on whether or not the output of the second logic circuits is a desired signal relative to the input of the first logic circuit.

Abstract: A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.

Abstract: A frequency comparator is disclosed, comparing frequencies of a first clock signal and a reference clock signal, comprising a phase-frequency detector and a comparison module. The phase-frequency detector receives the first clock signal and the reference clock signal, outputting an up clock signal and a down clock signal, wherein the pulse-width difference between the up clock signal and the down clock signal corresponds to the phase difference between the first clock signal and the reference clock signal. The comparison module compares the frequencies of the first clock signal and the reference clock signal based on how many times the pulse width of the up clock signal is larger or shorter than that of the down clock signal in a predetermined period.

Abstract: A circuit switches between at least a first clock signal and a second clock signal belonging to a plurality of clock signals available in an electronic device in response to the corresponding switch command, which comprises a selection module to select at a switch instant said second clock signal in said plurality of clock signals under the control of a signal selector and provide a selected clock signal.

Abstract: There provided is a low-cost, high performance sampling rate conversion calculating apparatus which achieves both a low delay characteristic required for conversational voice data and high quality required for audio data in a concurrent manner. A first digital signal processing section outputs conversational voice data, which requires the low delay characteristic, in accordance with a sampling frequency of an output terminal (111). A second digital signal processing section outputs audio data, which requires the high quality, rather than the low density characteristic, in accordance with the sampling frequency of the output terminal (111). An adder section (107) adds the conversational voice data outputted from the first digital signal processing section and the audio data outputted from the second digital signal processing section and outputs the added data from the output terminal (111).

Abstract: The invention relates to an input buffer amplifier suitable for a system on chip (SoC) device. The input buffer amplifier has a single ended input and a differential output. The input terminal is connected to a first differential stage having two transistors and to a second differential stage having two transistors. The first and second differential stages are further connected to a first and second load, for example, current mirrors being connected so as to provide a differential output at the output terminals.

Abstract: A frequency regulator for varying a clock frequency of a power-supplied consumer operated in a clocked manner, wherein the frequency regulator is implemented to perform an overall variation of the clock frequency from an actual frequency to a set frequency, such that the overall variation is obtained by a plurality of clock changes, each with a different amount of change, wherein each of the respective amounts of change depends on a power change caused by the associated clock frequency change.

Abstract: The frequency divider includes the buffer 30, the function selector 31 and the inverter 32. The output of the function selector 31 is input to the buffer 30. The output of the buffer 30 is fed back to the function selector 31 by two paths. One path includes the inverter 32 and the other does not. The function selector 31 selects one of the paths in synchronous with input clock CK. At one timing the output of the buffer 30 is flipped by the inverter 32. At the next timing the output of the buffer 30 is held the same by the function selector 31 selecting the path not including the inverter 32.

Abstract: A specification and method for the configuration of an instance are described. Inheritable configurations/profiles from an abstract configuration model are used to define the instance dynamically. The inheritable configurations/profiles may be written in XML.

Abstract: The present invention relates to a test system (100) interposed between a clock monitor self-timed memory. In an example embodiment, the test system (100) receives an internal clock signal (104) from the clock monitor (152), an external clock signal (CL) and a control signal (CS). A multiplexer (110) of the test system provides in dependence upon the control signal (CS) the internal clock signal (104) to the internal memory block (125) during a normal mode of operation of the self-timed memory and the external clock signal (CL) to the internal memory block (125) during a test mode (108) of the self-timed memory. The test system (100) enables control of the clock cycle of the internal memory block (125) by directly applying the external clock signal (CL) during test mode. Thus, the internal memory block is stressed properly enabling the detection of small delay faults.

Abstract: A data input apparatus includes: a phase detector comparing a phase of a data strobe signal with a phase of a clock signal to output a first phase comparison signal and a second phase comparison signal. A first delay controller determines whether a first data input strobe signal is delayed to output the determined signal as a second data input strobe signal in response to the first phase comparison signal. An internal clock synchronizer synchronizes first aligned data and second aligned data with the clock signal in response to the second data input strobe signal, to output the synchronized first and second data as first internal output data and second internal output data, respectively. A second delay controller determines whether the first internal output data and the second internal output data is delayed in response to the second phase comparison signal, to output the first internal output data and the second internal output data as first output data and second output data, respectively.

Abstract: A spectrum spreader may include a signal conductor and a tunable filter. The signal conductor may be configured to receive a clock signal having a clock signal frequency. The tunable filter may be coupled to the signal conductor wherein the tunable filter is configured to spread a frequency of the clock signal responsive to a control signal to provide a spread spectrum clock signal. More particularly, a frequency of the spread spectrum clock signal may be spread relative to the clock frequency. Related communications devices and methods are also discussed.

Abstract: In one aspect of the invention, a method of reducing intersymbol interference on a signal line is disclosed. A state machine records previous bits that were transmitted over the line. If the bit on the line has been static for several clock cycles, the slew rate will be increased to facilitate correct reading of the bit for the next clock cycle. If the bit on the line has been dynamic for the previous bits, the slew rate will be a lower slew rate to avoid crosstalk between neighboring lines.

Abstract: An image sensor may be improved by using ADCs that compensate for the effect of comparator input offset on comparator decisions. Offset compensation may be implemented in an ADC by using an amplifier section between the input of the ADC and a comparator section of the ADC to amplify the signals supplied to the comparator inputs and thereby reduce the effect of comparator offset on the comparator decision. The comparator section may be an autozeroing comparator section that is capable of performing an offset reduction operation to store offset compensation values at capacitors provided at its inputs. The amplifier section may be an autozeroing amplifier section having one or more amplifier stages that are capable of performing an offset reduction operation to store offset compensation values at capacitors provided at their inputs. Offset compensation may also be implemented using an autozeroing comparator section without a preceding amplifier section.

Abstract: In one embodiment, an integrated circuit comprises resonance limiter circuits coupled to a power supply connection of the integrated circuit. The resonance limiter circuits are configured to detect oscillation on the power supply connection at a resonant frequency, and to dampen the resonant frequency oscillation responsive to detecting the oscillation. In some embodiments, the resonance limiter circuits may damp oscillation at or above the resonant frequency or approximately the resonant frequency (e.g. somewhat below the resonance frequency). The resonant frequency depends on a package of the integrated circuit. In an embodiment, a resonance limiter circuit comprises a filter and a transistor coupled in parallel with the filter between a power supply connection and a ground connection. The filter is tuned to approximately a resonant frequency (e.g. the lowest resonant frequency) that depends on a package corresponding to an integrated circuit into which the resonance limiter circuit is fabricated.

Abstract: A method and/or a system of control signal synchronization of a scannable storage circuit is disclosed. In one embodiment, a system includes a first circuit to operate based on a first voltage of a first power supply, a second circuit to operate based on a second voltage of a second power supply, a level shifter circuit between the first circuit and the second circuit to translate between the first voltage of the first power supply and the second voltage of the second power supply, and a n-channel metal-oxide semiconductor field-effect transistor (nMOSFET) having a gate input of the second voltage and serially coupled in a fall path of the level shifter circuit to increase a rate of a capacitive discharge such that the rate of a capacitive discharge charge is substantially equal to a rate of a capacitive charge (e.g., the fall delay may also increase a bit because of an extra transistor).

Abstract: A design structure comprising a voltage translator circuit and a method for operating the same. The voltage translator circuit includes (a) an input node, an output node, and a ground node; (b) a voltage divider circuit including a first and second resistors coupled in series between the input node and the ground node; (c) a start voltage circuit coupled to a first voltage and to the input node; (d) a transfer circuit coupled to the output node; and (e) a capacitive circuit having a first and second capacitive nodes. The first capacitive node is coupled to the voltage divider circuit. The second capacitive node is coupled (i) to the first voltage via the start voltage circuit, and (ii) to the output node via the transfer circuit. In response to the input node changing towards the first voltage, the start voltage circuit is capable of disconnecting the second capacitive node from the first voltage.

Abstract: A level conversion circuit includes a controlling section supplied with a first power supply voltage and a second power supply voltage different from each other, the controlling section outputting a bias voltage, detecting rising of the first power supply voltage and the second power supply voltage, and outputting a control signal corresponding to a period from the rising of a power supply voltage to stabilization of the power supply voltage, and a level converting section supplied with the control signal and the bias voltage, operation of the level converting section being set in one of a shutdown state and a normal operation state according to the control signal, and the level converting section converting level of an input signal and outputting a signal different in level from the input signal when the operation of the level converting section is set in the normal operation state.

Abstract: A protection circuit monitors the gate voltage of an insulated gate bipolar transistor (IGBT) or metal oxide semiconductor field effect transistor (MOSFET) to protect the transistor during a time when it is being turned on. In one embodiment, the circuit monitors a transient gate voltage of the transistor when it is turned on. A short or overcurrent condition is detected when the gate voltage exceeds a delayed reference signal.

Abstract: The invention provides a signal coupling circuit and method for coupling an analog input signal to a processing circuit. The signal coupling circuit includes a number of first coupling units, a second coupling unit and a first multiplexer. The first coupling units are coupled to a first input terminal of the processing circuit, for respectively receiving a plurality of input signals. The first multiplexer is coupled between the first coupling units and the processing circuit for selecting one of the input signals and transmitting the selected input signal to the processing circuit. The second coupling unit is coupled to a second input terminal of the processing circuit, for receiving a common reference signal, wherein the processing circuit uses the common reference signal as reference for processing some or all of the input signals.

Abstract: A voltage detection and sequencing circuit is provided, preferably on a single semiconductor chip, for applying a plurality of voltages to an electrical system in a predetermined sequence. The circuit includes a plurality of subsystems each adapted to detect one of a plurality of supply voltages at an input terminal and to supply the supply voltage to at least one output terminal in a predetermined sequence as controlled by a sequencing means.

Abstract: Embodiments of an oscillator circuit are described. Embodiments described herein include an oscillator circuit suitable for a resonator with relatively high motional impedance, thus requiring relatively high amplification and having relatively high sensitivity to noise. However, the embodiments described are not intended to be limited to use with any particular type of resonator. In one embodiment, alternating current (AC) coupling, or capacitive coupling, is used in part to decouple the bias voltage placed on the resonator from the operating point of the amplifier, allowing one voltage to be high relative to the other. In an embodiment, some legs, or all legs of the circuit that includes drive circuitry and a resonator include differential signaling.

Abstract: A reference circuit includes: (a) a first reference circuit having a reference signal and a ?VBE loop; and (b) a modification circuit using a first voltage to change a first current in the ?VBE loop of the first reference circuit. In one embodiment, the reference circuit is a voltage reference circuit.

Abstract: A limiter circuit includes a differential amplifier circuit having a non-inverting and an inverting inputs, the inverting input fed with an input signal to the limiter circuit, a driving circuit fed with an output of the differential amplifier, a MOS transistor having a source, a drain and a gate, one of the source and the drain of the MOS transistor connected to an output of the driving circuit, the other of the source and the drain of the MOS transistor connected to the non-inverting input of the differential amplifier, the gate of the MOS transistor applied with a predetermined voltage, and a load circuit connected to the other of the source and the drain of the MOS transistor.

Abstract: A Local Dynamic Power Controller (LDPC) generates and deliver to a load a full swing voltage supply signal and a reduced swing voltage supply signal. Both the full and reduce voltage supply signals are generated from a single power supply. The full swing voltage supply signal is supplied when the load is in full operational mode whereas the reduce voltage supply signal is provided when the load is in a sleep mode. As a consequence, power dissipated in the load is reduced.

Abstract: The present invention discloses a bus pumping compensation for a pulse modulation circuit such as class D modulators. The compensation according to the present invention provides a compensation current controlled by the output voltage, with the compensation characteristics matching the reverse current for improving circuit efficiency. Embodiments of the present invention also disclose a designable compensation circuit, comprising a linear compensation current, offering a good trade-off between circuit efficiency and ease of design. The present invention compensation circuit is preferably employed in a class D amplifier with substantial reverse current, and most preferably added into a LDO power supply in a class D amplifier circuit to prevent reverse current problem. The disclosed class D amplifier circuit is preferably used in an audio media player.

Abstract: An amplifier apparatus including differential inputs disposed to receive a first and second input signal, a primary differential amplifier having inverting and non-inverting input nodes receiving the first and second input signal through respective first and second impedance elements and providing a main output signal, feedback circuitry disposed to sample the main output signal and convey complementary current-mode negative feedback signals to the inverting and non-inverting input nodes, wherein the current-mode feedback signals are each servo feedback signals having the same low-pass characteristic, a first controllable circuitry to adjust the input offset voltage of the primary differential amplifier, and a second controllable circuitry to compensate for variations in an input offset voltage and a bias current of the differential amplifier by changes in an operating environment.

Abstract: In a balanced output circuit, an input signal inputted thereto is provided as a first output signal thereof on one hand, and on the other hand the input signal is inputted to an inverting amplification circuit and is compared with a comparison voltage before the signal is outputted as a second output signal. Based on the comparison of the first and second output signals, the comparison voltage is controlled by a charging voltage of a capacitor such that the DC voltage of the second output signal is equalized to that of the first output signal. Thus, the DC offset voltage between the first output signal (non-inverted output signal) and the second output signal (inverted output signal) can be properly annihilated by a simple circuit.

Abstract: A frequency divider, which has a cross-coupled inductor-capacitor (LC) structure or a ring structure, is inputted with a direct current (DC) control voltage from an input terminal. By doing so, the frequency divider can adjust an oscillation frequency; and further compensate the input power sensitivity, lower the power consumption and increase the division range. The frequency divider can be used in high-band/high-speed digital or analog communication systems.

Abstract: An oscillator is described. The oscillator includes segments of two-conductor transmission line being connected together by an odd number of connection means to form a closed loop. A plurality of current switches is connected to the conductors of the segments and a high impedance element, such as an inductor or transmission line, is connected to a conductor of at least one segment. The high impedance element sources current into the closed loop and the current switches sink current from one or the other of the conductors of the loop depending on the state of the switch. The switches cause a wave to be established and maintained on the loop and the wave changes the state of the switches as it oscillates. One embodiment of the switches employs npn transistors whose emitters are connected to a current source and another uses NMOS transistors.

Abstract: Devices (1) for exchanging ultra wide band signals comprise frequency translating stages (20,30) for frequency translating signals and oscillating stages (40) for supplying main inphase/quadrature oscillation signals to the frequency translating stages (20,30). By providing the oscillating stages (40) with polyphase filters (43,44) for reducing harmonics in oscillation signals, the main oscillation signals will be sufficiently clean. The oscillating stages (40) comprise mixers (46) for converting first inphase/quadrature oscillation signals and second inphase/quadrature oscillation signals into the main oscillation signals. The polyphase filters (43,44) may be located before and after the mixers (46). Frequency selectors (45) replace prior art multiplexers located after the mixers (46).

Abstract: When using micro-resonant structures which are being excited and caused to resonate by use of a charged particle beam, whether as emitters or receivers, especially in a chip or circuit board environment, it is important to prevent the charged particle beam from coupling to or affecting other structures or layers in the chip or circuit board. Shielding can be provided along the path of the charged particle beam, on top of the substrate, to prevent such coupling.

Abstract: A focal plane array electromagnetic radiation detector includes an array of micro-electromagnetic resonant detector cells. Each micro-electromagnetic resonant detector cell may include an ultra-small resonant structure for receiving an electromagnetic wave and adapted to angularly modulate a charged particle beam in response to receiving an electromagnetic wave. Each micro-electromagnetic detector cell may include a detector portion that measures the angular modulation of the charged particle beam. The ultra-small resonant structure is designed to angularly modulate the charged particle beam according to a characteristic of the received electromagnetic wave.

Abstract: Embodiments of an oscillator circuit are described. Embodiments described herein include an oscillator circuit suitable for a resonator with relatively high motional impedance, thus requiring relatively high amplification and having relatively high sensitivity to noise. However, the embodiments described are not intended to be limited to use with any particular type of resonator. In one embodiment, alternating current (AC) coupling, or capacitive coupling, is used in part to decouple the bias voltage placed on the resonator from the operating point of the amplified, allowing one voltage to be high relative to the other. In an embodiment, some legs, or all legs of the circuit that included drive circuitry and a resonator include differential signaling.

Abstract: An electronic apparatus comprises at least one quartz crystal oscillator comprised of a quartz crystal oscillating circuit having a quartz crystal resonator, an amplifier, at least one resistor, and capacitors. The quartz crystal resonator comprises a quartz crystal tuning fork resonator having a quartz crystal tuning fork base, quartz crystal tuning fork tines connected to the quartz crystal tuning fork base, and at least one groove formed in at least one of opposite main surfaces of the quartz crystal tuning fork tines. A length of the at least one groove formed in at least one of the opposite main surfaces of the quartz crystal tuning fork tines is within a range of 40% to 80% of a length of the quartz crystal tuning fork tines.

Abstract: A source coupled differential complementary Colpitts oscillator is described, which enables a differential oscillation and also can improve phase noise performance by source-coupling a complementary Colpitts oscillator using an inductor. A differential complementary Colpitts oscillator includes: a plurality of complementary Colpitts oscillators and a source coupler which couples a source node of the plurality of complementary Colpitts oscillators, enables the Colpitts oscillators to differentially oscillate.

Abstract: In one implementation, a method is provided for testing a plasma reactor multi-frequency matching network comprised of multiple matching networks, each of the multiple matching networks having an associated RF power source and being tunable within a tunespace. The method includes providing a multi-frequency dynamic dummy load having a frequency response within the tunespace of each of the multiple matching networks at an operating frequency of its associated RF power source. The method further includes characterizing a performance of the multi-frequency matching network based on a response of the multi-frequency matching network while simultaneously operating at multiple frequencies.

Abstract: A programmable gain attenuator includes a termination resistor. A first termination switch connects one side of the termination resistor to a first output. A second termination switch connects another side of the termination resistor to a second output. A first resistor ladder is arranged between a first input and the first side of the termination resistor. A first plurality of switches connect a corresponding tap from the first resistor ladder to the first output. A second resistor ladder is arranged between a second input and the second side of the termination resistor. A second plurality of switches connect a corresponding tap from the second resistor ladder to the second output. A first switch of the first plurality of switches is turned on, followed by a second switch of first plurality of switches turned off, followed by a third switch of first plurality of switches turned on.

Abstract: A method and apparatus for changing the polarization of an input signal includes propagating a polarized input signal having orthogonal E-field components by at least one surface each having a respective surface impedance and varying at least one of the surface impedances to shift the phase of one of the components independently from the other so that the polarity of said input signal is changed. Bi-directional propagation is achieved by rotating polarity in one direction but not the other.

Abstract: Two second-order bandpass filter are connected serially to obtain a dual bandpass filter. One is inductive and the other is capacitive. One has a low passband and the other has a high passband. Between them, a finite transmission zero is formed to suppress noise. The present invention achieves a passband as wide as 1 gigahertz so that it can be applied to a wireless local network, communication equipments and electronic devices.

Abstract: The present invention provides an active capacitor comprising an input terminal, a primary all-pass type 90° phase-advanced stage constituted of discrete elements, and a phase inversion amplifying stage and including a constitution in which a signal supplied to the input terminal is inputted to the primary all-pass type 90° phase-advanced stage, a 90° phase-advanced signal obtained at its output is inputted to the phase inversion amplifying stage subsequent to the primary all-pass type 90° phase-advanced stage and phase-inversion amplified thereat, and an output produced from the phase inversion amplifying stage is feedback-coupled to the input terminal.

Abstract: The present invention provides an active inductor comprising an input terminal, a primary all-pass type 90° phase-delayed stage constituted of discrete elements, and a phase inversion amplifying stage and including a constitution in which a signal supplied to the input terminal is inputted to the primary all-pass type 90° phase-delayed stage, a 90° phase-delayed signal obtained at its output is inputted to the phase inversion amplifying stage subsequent to the primary all-pass type 90° phase-delayed stage and phase-inversion amplified thereat, and an output produced from the phase inversion amplifying stage is feedback-coupled to the input terminal.

Abstract: A device and method is provided that includes a window for coupling a signal between cavities of a device or between cavities of different devices. A wall or microstructure is formed on a surface and defines a cavity. The window is formed in the wall and comprises at least a portion of the wall and is electrically conductive. The cavity can be sized to resonate at various frequencies within the terahertz portion of the electromagnetic spectrum and generate an electromagnetic wave to carry the signal. The window allows surface currents to flow without disruption on the inside surface of the cavity.

Abstract: One inventive aspect relates to a reconfigurable cavity resonator. The resonator comprises a cavity delimited by metallic walls. The resonator further comprises a coupling device for coupling an electromagnetic wave into the cavity. The resonator further comprises a tuning element for tuning a resonance frequency at which the electromagnetic wave resonates in the cavity. The tuning element comprises one or more movable micro-electromechanical elements with an associated actuation element located in their vicinity for actuating each of them between an up state and a down state. The movable micro-electromechanical elements at least partially have a conductive surface and are mounted within the cavity.

Abstract: The invention relates to electromagnetic wave guiding devices or waveguides (f<10 THz) and to processes for manufacturing these waveguides, which comprise at least one body (30) supporting at least one active wall (40). The body (30) of the waveguide is made from a volume of a ceramic selected from the following: silicon carbides, aluminum nitride, boron nitrides, and especially 3C cubic and 2H hexagonal varieties of boron nitride, diamond, beryllium oxide or assemblies of said materials. Applications: waveguides, filter cavities, reflectors and antennas for radiofrequency waves and microwaves, atomic clocks and particle accelerators.

Abstract: An electrical relay includes a magnetic system, a contact system and a slider. The magnetic system includes an armature. The contact system includes a moveable spring contact and a fixed spring contact. The moveable spring contact is moveable between an open position and a closed position. The moveable spring contact is in electrical contact with the fixed spring contact in the closed position. The slider connects the moveable spring contact to the armature. The slider transfers movement of the armature to the moveable spring contact. The slider has at least one contact opening element extending there from. The contact opening element strikes the moveable spring contact during movement of the moveable spring contact to the open position to break any existing weld between the moveable spring contact and the fixed spring contact.

Abstract: A multistage switch includes a switch push button. A magnet is disposed in a recess of the inner wall surface of the switch push button. The multistage switch further includes a magnetic sensor, and the magnetic sensor includes a substrate. Two magnetoelectric transducers are mounted on a surface of the substrate, and are disposed so as to face the magnet.

Abstract: A resin-impregnated superconducting magnet coil comprising a number of turns of superconducting wire (14) embedded within a resin (16) having an outer filler layer (18) composed of the resin, filled with filler material (20). The coil further comprises a cooling layer (22) interposed between the superconducting wire (14) and the filler layer (18).

Abstract: A magnetic flux coupling-type superconducting current limiter is capable of protecting lines more effectively by winding reactors of a primary coil and a secondary coil in series in the structure where the primary coil and the secondary coils are wound in parallel in the conventional magnetic flux-lock type current limiter to increase a linked flux generated from an iron core. An electric conducting current which rapidly increases when a fault occurs is divided into the secondary coil and a superconducting coil to decrease a load on the superconducting element and it is opened more rapidly than the existing superconducting current limiter during a quench time such that it better limits a fault current.