Abstract: Integrated circuits such as semiconductor memories, image sensors, PLA's, and the like have been formed on rigid, planar substrates such as silicon substrates. This has resulted in shapes without flexibility and limited applicabilities. Further, since multiple circuit elements are continuously formed on a flat surface, it has been impossible to produce a non-defective semiconductor memory unless all the circuit elements are fabricated without defects, making it difficult to improve a yield. It is thus devised to weave or braid linear devices into a fabric shape to prepare a planar semiconductor memory, or to bundle up linear devices to prepare a linear semiconductor memory. The integrated circuit comprising the linear devices is flexible and light-weighted, and is thus usable in various applications. It becomes possible to prepare an integrated circuit by once fabricating linear devices and selecting only non-defective ones therefrom, thereby enabling an improved production yield of integrated circuits.

Abstract: A semiconductor device of the present invention comprises a logic circuit to which a power supply voltage, a sub-power supply voltage, a ground voltage and a sub-ground voltage are supplied; a driver for generating the sub-power supply voltage and the sub-ground voltage based on the power supply voltage and the ground voltage; a first wiring layer including a sub-power supply line for supplying the sub-power supply voltage and a sub-ground line for supplying the sub-ground voltage; a second wiring layer including source/drain lines for MOS transistors; a third wiring layer including a main power supply line for supplying the power supply voltage and a main ground line for supplying the ground voltage and arranged opposite to the first wiring layer to sandwich the second wiring layer; via structures for connecting the source/drain lines of the second wiring layer to the other layers.

Abstract: A phase change random access memory PCRAM device is described suitable for use in large-scale integrated circuits. An exemplary memory device has a pipe-shaped first electrode formed from a first electrode layer on a sidewall of a sidewall support structure. A sidewall spacer insulating member is formed from a first oxide layer and a second, “L-shaped,” electrode is formed on the insulating member. An electrical contact is connected to the horizontal portion of the second electrode. A bridge of memory material extends from a top surface of the first electrode to a top surface of the second electrode across a top surface of the sidewall spacer insulating member.

Abstract: A memory device, in particular to a resistively switching memory device such as a Phase Change Random Access Memory (“PCRAM”), with a transistor is disclosed. Further, the invention relates to a method for fabricating a memory device. According one embodiment of the invention, a memory device is provided, having at least one nanowire or nanotube or nanofibre access transistor. In one embodiment, the nanowire or nanotube or nanofibre access transistor directly contacts a switching active material of the memory device. According to an additional embodiment, a memory device includes at least one nanowire or nanotube or nanofibre transistor with a vertically arranged nanowire or nanotube or nanofibre.

Abstract: A semiconductor flash memory device. The flash memory device includes a floating gate electrode disposed in a recess having slanted sides in a semiconductor substrate. A gate insulation film is interposed between the floating gate electrode and the semiconductor substrate. A control gate electrode is disposed over the floating gate electrode. The floating gate electrode includes projections adjacent to the slanted sides of the recess.

Abstract: A field-effect transistor which comprises a buffer layer and a barrier layer each of which is made of a Group III nitride compound semiconductor and has a channel at the interface inside of the buffer layer to the barrier layer, wherein the barrier layer has multiple-layer structure comprising an abruct interface providing layer which composes the lowest semiconductor layer in said barrier layer and whose composition varies rapidly at the interface of said buffer layer, and an electrode connection plane providing layer which constructs the uppermost semiconductor layer and whose upper surface is formed flat.

Abstract: An MOS type solid-state image pickup device including pixels each of which comprises a photodiode PD, a detection portion N and a transfer transistor QT for transferring the charges accumulated in the photodiode PD to the detection portion N, wherein the gate voltage of the transfer transistor QT when the charges are accumulated in the photodiode PD is set to a negative.

Abstract: The present invention is directed to novel front side illuminated, back side contact photodiodes and arrays thereof In one embodiment, the photodiode has a substrate with at least a first and a second side and a plurality of electrical contacts physically confined to the second side. The electrical contacts are in electrical communication with the first side through a doped region of a first type and a doped region of a second type, each of the regions substantially extending from the first side through to the second side. In another embodiment, the photodiode comprises a wafer with at least a first and a second side; and a plurality of electrical contacts physically confined to the second side, where the electrical contacts are in electrical communication with the first side through a diffusion of a p+ region through the wafer and a diffusion of an n+ region through the wafer.

Abstract: A CCD type solid-state imaging device includes: a photoelectric conversion element (n layer 2, p layer 3) formed in a semiconductor substrate 1; a charge transfer channel 5 that transfers electric charges generated in the photoelectric conversion element; a charge read region 6 that reads out the electric charges accumulated in the photoelectric conversion element into the charge transfer channel 5; and a charge read electrode 8 formed above the charge read region 6 with a gate insulating film 10 disposed therebetween. The charge read electrode 8 controls the reading out of the electric charges into the charge transfer channel 5. A gap is formed between the photoelectric conversion element and the charge read electrode 8 in plan view.

Abstract: This invention provides a type of solid-state image pickup device characterized by the fact that for a solid-state image pickup device with a broad dynamic range, it is possible to suppress the dark current than photoelectrons overflowing from the photodiode, as well as its driving method. Plural pixels are integrated in an array configuration on a semiconductor substrate. Each pixel has the following parts: photodiode (CPD), transfer transistor (?T), floating diffusion (CFD), accumulating capacitive element (CS), accumulating transistor (?S), and a reset transistor. During the accumulating period of photoelectric charge, voltage (?) over that applied on the semiconductor substrate, or ?0.6 V or lower than the voltage applied on the semiconductor substrate, is applied as an OFF potential on the gate electrode of at least one transfer transistor, the accumulating transistor and the reset transistor.

Abstract: An image sensor includes a reset transistor, reset gate electrodes and a potential shift circuit. The reset transistor includes a reset gate and a reset drain, and resets charges detected by a charge detection device. The reset gate electrodes control a potential of the reset gate. The potential shift circuit initializes output signals in response to a shift pulse, and outputs the output signals to the reset gate electrodes in response to a reset pulse.

Abstract: A phase change memory cell is disclosed, including a first electrode and a second electrode, and a plurality of recording layers disposed between the first and second electrodes. The phase of an active region of each of the recording layers can be changed to a crystalline state or an amorphous state by current pulse control and hence respectively has crystalline resistance or amorphous resistance. At least two of the recording layers have different dimensions such that different combinations of the crystalline and amorphous resistance result in at least three different effective resistance values between the first and second electrodes. The phase change memory cell can be realized with the same material of the recording layers and thus can be fabricated with simple and currently developed CMOS fabrication process technologies. Furthermore, the phase change memory is easy to control due to large current programming intervals.

Abstract: A semiconductor device is described that operates as an improved junction field effect transistor (JFET). A bipolar transistor with a collector region, a base region, an emitter region, a first base contact, and a second base contact insulated from the first base contact, has the base region lightly doped to about a 1E16 to 5E17 atoms/cm3 doping level. A connection is provided between the emitter region and the collector region to act as a JFET gate contact for the bipolar transistor. The semiconductor device operates as an improved JFET with the first base contact being a drain contact and the second base contact being a source contact. A method for manufacture of an improved JFET on a chip containing conventional bipolar devices is also described. The improved JFET is shown being used with a write head in a disk drive system for providing electrostatic discharge protection.

Abstract: A vertical JFET 1a according to the present invention has an n+ type drain semiconductor portion 2, an n-type drift semiconductor portion 3, a p+ type gate semiconductor portion 4, an n-type channel semiconductor portion 5, an n+ type source semiconductor portion 7, and a p+ type gate semiconductor portion 8. The n-type drift semiconductor portion 3 is placed on a principal surface of the n+ type drain semiconductor portion 2 and has first to fourth regions 3a to 3d extending in a direction intersecting with the principal surface. The p+ type gate semiconductor portion 4 is placed on the first to third regions 3a to 3c of the n-type drift semiconductor portion 3. The n-type channel semiconductor portion 5 is placed along the p+ type gate semiconductor portion 4 and is electrically connected to the fourth region 3d of the n-type drift semiconductor portion 3.

Abstract: A MOS device having a reduced LDD dopant diffusion length and a method for forming the same are provided. The MOS device includes a gate stack over a semiconductor substrate, a spacer liner on a sidewall of the gate stack and having a portion over the semiconductor substrate, and a spacer over the spacer liner. The spacer for a PMOS device preferably has a tensile stress, and the spacer for an NMOS device preferably has a compressive stress.

Abstract: There is provided a semiconductor device including: a semiconductor substrate including a supporting substrate, a first insulating film formed on the supporting substrate, and a silicon film having a first region and a second region formed on the first insulating film, and a third region at least a portion of which is disposed between the first region and the second region; a first diffusion layer formed on the first region of the silicon film and having a first conductive type; a second diffusion layer formed on the second region of the silicon film and containing impurities having a second conductive type, which has a polarity opposite to that of the first conductive type; a second insulating film formed on the third region of the silicon film; and a third insulating film formed on the second insulating film, as well as a method of fabricating the semiconductor device.

Abstract: A solid-state imaging device includes a semiconductor substrate, photodetector elements, and blocking layers. The solid-state imaging device receives light on the back surface, and photoelectrically converts light incident upon the back surface of the semiconductor substrate, thereby acquiring an image of an object to be imaged. The photodetector elements receive the signal charge generated through the photoelectric conversion. Between a region in the semiconductor substrate where the photodetector elements are provided and the back surface, the blocking layers are provided. The blocking layers suppress diffusion of the signal charge.

Abstract: To provide an amplification type solid state image pickup device enabling lower noise, higher gain, and higher sensitivity than any conventional amplification type solid state image pickup device.

Abstract: A ferroelectric capacitor including: a substrate; a first electrode formed above the substrate; a first ferroelectric layer formed above the first electrode and including a complex oxide shown by Pb(Zr,Ti)O3; a second ferroelectric layer formed above the first ferroelectric layer and including a complex oxide shown by Pb(Zr,Ti)1-xNbxO3; and a second electrode formed above the second ferroelectric layer.

Abstract: A memory cell array includes a plurality of first conductive lines running in a first direction, where the first conductive lines have a pitch Bp, a plurality of second conductive lines, and a plurality of memory cells. Each of the memory cells are at least partially formed in a semiconductor substrate and are accessible by addressing at least a corresponding one of the first conductive lines and at least a corresponding one of the second conductive lines. The memory cell array further includes a plurality of supporting lines, where the supporting lines have a pitch Mp and are disposed above the first and second conductive lines, and a plurality of supporting contacts. The first conductive lines are connected with corresponding ones of the supporting lines via the supporting contacts, and Mp is larger than Bp.

Abstract: An MRAM bit (10) includes a free magnetic region (15), a fixed magnetic region (17) comprising an antiferromagnetic material, and a tunneling barrier (16) comprising a dielectric layer positioned between the free magnetic region (15) and the fixed magnetic region (17). The MRAM bit (10) avoids a pinning layer by comprising a fixed magnetic region exhibiting a well-defined high Hflop using a combination of high Hk (uniaxial anisotropy), high Hsat (saturation field), and ideal soft magnetic properties exhibiting well-defined easy and hard axes.

Abstract: A semiconductor device comprises a plurality of gate structures formed on a substrate, a gate spacer formed on a sidewall of the gate structures, a semiconductor pattern formed on the substrate between the gate structures, a first impurity region and a second impurity region formed in the semiconductor pattern and at surface portions of the substrate, respectively, wherein the first and second impurity regions include a first conductive type impurity, and a channel doping region surrounding the first impurity region, wherein the channel doping region includes a second conductive type impurity.

Abstract: An integrated semiconductor memory includes at least one memory cell having at least one transistor which forms an inversion channel in the switched-on state. The transistor comprises a structure element having a first source/drain region, a second source/drain region, and a region arranged between the first and the second source/drain region. The structure element is insulated from a semiconductor substrate by an insulation layer, a gate dielectric is arranged on the structure element, and a word line is arranged on the gate dielectric.

Abstract: A semiconductor device includes: a semiconductor element having first and second surfaces, wherein the semiconductor element includes at least one electrode, which is disposed on one of the first and second surfaces; and first and second metallic layers, wherein the first metallic layer is disposed on the first surface of the semiconductor element, and wherein the second metallic layer is disposed on the second surface of the semiconductor element. The one electrode is electrically coupled with one of the first and second metallic layers, which is disposed on the one of the first and second surfaces. The one electrode is coupled with an external circuit through the one of the first and second metallic layers.

Abstract: An interdigitated Metal-Insulator-Metal (MIM) capacitor provides self-shielding and accurate capacitance ratios with small capacitance values. The MIM capacitor includes two terminals that extend to a plurality of interdigitated fingers separated by an insulator. Metal plates occupy layers above and below the fingers and connect to fingers of one terminal. As a result, the MIM capacitor provides self-shielding to one terminal. Additional shielding may be employed by a series of additional shielding layers that are isolated from the capacitor. The self-shielding and additional shielding may also be implemented at an array of MIM capacitors.

Abstract: A method for fabricating a contact of a semiconductor device structure includes forming a barrier layer that is entirely recessed within a contact aperture. A central region of the barrier layer may be recessed relative to at least a portion of an outer periphery of the barrier layer. Semiconductor device structures including such contacts are also disclosed. Such a contact may be part of a memory cell.

Abstract: A memory device is disclosed. A floating gate is disposed overlying a substrate. A tunneling dielectric layer is interposed between the floating gate and the substrate. An inter poly dielectric layer is disposed overlying the floating gate and the substrate. A word line is disposed overlying the floating gate, extending in a row direction. A bit line is disposed in the substrate, extending in a column direction, wherein the bit line is partially overlapped by the floating gate and the word line.

Abstract: Example embodiments are directed to a semiconductor memory device that may include a plurality of memory cells, each having a transistor of a first conductivity type with a first shape, a sub-word line driver including a transistor of the first conductivity type with a second shape and a transistor of a second conductivity type with the second shape, a sense amplifier including a transistor of the first conductivity type with the second shape and a transistor of the second conductivity type with the second shape, and a peripheral circuit including a transistor of the first conductivity type with the second shape and a transistor of the second conductivity type with the second shape in order to control inputting/outputting of data to/from the memory cells.

Abstract: A non volatile semiconductor memory device wherein it is possible to transfer Vpp without a drop in voltage of the transfer transistor Vth (threshold voltage) in a transfer circuit or decoder circuit for selectively transferring Vpp by using a usual LVP (low voltage P type transistor) to reduce step(s) of production process and costs. An LVP (low voltage P type transistor) instead of a HVP (high voltage P type transistor) for a transfer circuit is used. Two-way diodes each of which threshold value becomes about Vdd are inserted between the gate and the drain.

Abstract: A twin non-volatile memory cell on unit device and method of operating the same are disclosed. The device is formed in the n-well and compatible with CMOS processes comprising a selecting gate, two ONO spacers, a p+ source/drain, and n extended source/drain. To program the cells, two strategies can be taken. One is by a band to band hot electron injection can be carried out. The other is by channel hot hole induced hot electron injection. To read the right cell of the twin nonvolatile cells, a reverse read is taken so as to shield the left cell. In the reading process, the biased on the selecting gate and the source electrode have to make sure the tapered main channel beneath selecting gate has its narrower end through the depletion boundary to connect the second channel beneath the extended source. To erase the datum in the selected cell, two approaching can be carried out. One is by FN erase, the other is by band to band induced hot hole injection.

Abstract: An embedded memory device and method of forming MOS transistors having reduced masking requirements and defects using a single drain sided halo implant in the NMOS FLASH or EEPROM memory regions is discussed. The memory device comprises a memory region and a logic region. Logic transistors within the logic region have halos implanted at an angle underlying the channel from both drain and source region sides. Asymmetric memory cell transistors within the memory region receive a selective halo implant only from the drain side of the channel and not from the source side to form a larger halo on the drain side and leave a higher dopant concentration more deeply into the source side.

Abstract: A semiconductor device includes a p-channel MIS transistor. A p-channel MIS transistor includes; an n-type semiconductor layer formed on the substrate; first source/drain regions being formed in the n-type semiconductor layer and being separated from each other; a first gate insulating film being formed on the n-type semiconductor layer between the first source/drain regions, and containing silicon, oxygen, and nitrogen, or containing silicon and nitrogen; a first gate electrode formed above the first gate insulating film; and a first interfacial layer being formed at an interface between the first gate insulating film and the first gate electrode, and containing a 13-group element. The total number of metallic bonds in the 13-group element in the interfacial layer being larger than the total number of each of oxidized, nitrided, or oxynitrided bonds in the 13-group element in the interfacial layer.

Abstract: A semiconductor memory device according to the present invention includes a first wiring region and a second wiring region located adjacent to the first wiring region. First lines located in the first wiring region include a first portion, a first lead portion and first inclined portion. Second lines located in the second wiring region include a second portion, a second lead portion and a second inclined portion. The first and second portions are located in parallel with a same pitch, the first and second lead portions are located with a pitch which is larger than the pitch of the first and second portions, the first and second inclined portions extend the same direction at a predetermined angle.

Abstract: A nonvolatile semiconductor storage device includes a semiconductor substrate, and at least one memory cell formed on the semiconductor substrate, the at least one memory cell having a gate electrode unit in which a floating gate electrode and a control gate electrode are stacked, at least part of the control gate electrode being silicidated. The nonvolatile semiconductor storage device further includes at least one dummy transistor formed on the semiconductor substrate, the at least one dummy transistor having a first dummy electrode, and a second dummy electrode which has a current leakage path and which is stacked on the first dummy electrode.

Abstract: A non-volatile memory device has a gate dielectric film formed between a floating gate and a control gate. The gate dielectric film is formed by forming an oxide film and a ZrO2/Al2O3/ZrO2 (ZAZ) film. Accordingly, the reliability of non-volatile memory devices can be improved while securing a high coupling ratio.

Abstract: A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isolate stripe-shaped element-forming regions. Formed on the substrate area floating gate via a first gate insulating film and further a control gate via a second gate insulating film. Source and drain diffusion layers are formed in self-alignment with control gates. The second gate insulating film on the floating gate is divided and separated together with the floating gate by slits above the element isolation/insulation films into discrete portions of individual memory cells.

Abstract: An object is to provide a nonvolatile semiconductor memory device which is excellent in a writing property and a charge retention property. In addition, another object is to provide a nonvolatile semiconductor memory device capable of reducing writing voltage. A nonvolatile semiconductor memory device includes a semiconductor layer or a semiconductor substrate including a channel formation region between a pair of impurity regions that are formed apart from each other, and a first insulating layer, a plurality of layers formed of different nitride compounds, a second insulating layer, and a control gate that are formed in a position which is over the semiconductor layer or the semiconductor substrate and overlaps with the channel formation region.

Abstract: This invention is to improve data retention properties of a nonvolatile memory cell having an ONO film. A first cavity is disposed, in a position between the nitride film serving as a charge storage film and a memory gate and below an end portion of the memory gate, adjacent to the upper oxide film. A second cavity is disposed, in a position between the nitride film and a substrate and below an end portion of the memory gate, adjacent to the bottom oxide film. These cavities are closed with sidewall spacers formed over the substrate along the sidewalls of the memory gate.

Abstract: In one embodiment, a semiconductor device is formed having sub-surface charge compensation regions in proximity to channel regions of the device. The charge compensation trenches comprise at least two opposite conductivity type semiconductor layers. A channel connecting region electrically couples the channel region to one of the at least two opposite conductivity type semiconductor layers.

Abstract: A semiconductor device includes a base layer of a first conductivity type, a barrier layer of a first conductivity type formed on the base layer, a trench formed from the surface of the barrier layer to such a depth as to reach a region in the vicinity of an interface between the barrier layer and the base layer, a gate electrode formed in the trench via a gate insulating film, a contact layer of a second conductivity type selectively formed in a surface portion of the barrier layer, a source layer of the first conductivity type selectively formed in the surface portion of the barrier layer so as to contact the contact layer and a side wall of the gate insulating film in the trench, and a first main electrode formed so as to contact the contact layer and the source layer.

Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

Abstract: All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and P-N diode clamps and rectifiers and junction terminations. Since the processes eliminate the need for high temperature processing and employ “as-implanted” dopant profiles, they constitute a modular architecture which allows devices to be added or omitted to the IC without the necessity of altering the processes used to produce the remaining devices.

Abstract: A lateral DMOS structure includes a light doped p-type region beneath and near the gate at the drain side. The electric field on the surface near the gate is reduced. Thus the electric field near the gate decreases, and the SOA (safe operating area) of the lateral DMOS device increases and long time reliability improves. Moreover, the lateral DMOS of the invention can be fabricated without increasing the manufacturing cost.

Abstract: An n-conductively doped source region (2) in a deep p-conducting well (DP), a channel region (13), a drift region (14) formed by a counterdoping region (12), preferably below a gate field plate (6) insulated by a gate field oxide (8), and an n-conductively doped drain region (3) arranged in a deep n-conducting well (DN) are arranged in this order at a top side of a substrate (1). A lateral junction (11) between the deep p-conducting well (DP) and the deep n-conducting well (DN) is present in the drift path (14) in the vicinity of the drain region (3) so as to avoid a high voltage drop in the channel region (13) during the operation of the transistor and to achieve a high threshold voltage and also a high breakdown voltage between source and drain.

Abstract: This invention discloses an improved semiconductor power device includes a plurality of power transistor cells wherein each cell further includes a planar gate padded by a gate oxide layer disposed on top of a drift layer constituting an upper layer of a semiconductor substrate wherein the planar gate further constituting a split gate including a gap opened in a gate layer whereby the a total surface area of the gate is reduced. The transistor cell further includes a JFET (junction field effect transistor) diffusion region disposed in the drift layer below the gap of the gate layer wherein the JFET diffusion region having a higher dopant concentration than the drift region for reducing a channel resistance of the semiconductor power device.

Abstract: An improved dynamic memory cell using a semiconductor fin or body is described. Asymmetrical doping is used in the channel region, with more dopant under the back gate to improve retention without significantly increasing read voltage.

Abstract: In a high-voltage PMOS transistor having an insulated gate electrode (18), a p-conductive source (15) in an n-conductive well (11), a p-conductive drain (14) in a p-conductive well (12) which is arranged in the n-conductive well, and having a field oxide area (13) between the gate electrode and drain, the depth (A?-B?) of the n-conductive well underneath the drain (14) is less than underneath the source (15), and the depth (A?-B?) of the p-conductive well is greatest underneath the drain (14).

Abstract: A method is provided for forming a compound semiconductor-on-silicon (Si) wafer with a thermally soft insulator. The method forms a Si substrate, with a thermally soft insulator layer overlying the Si substrate. A silicon oxide layer is formed immediately overlying the thermally soft insulator layer, a top Si layer overlies the silicon oxide, and a lattice mismatch buffer layer overlies the top Si layer. A compound semiconductor layer is formed overlying the lattice mismatch buffer layer. The thermally soft insulator has a liquid phase temperature lower than the liquid phase temperatures of Si and the compound semiconductor. For example, the thermally soft insulator may have a flow temperature in the range of about 500° C. to 900° C., where the flow temperature is greater than the solid phase temperature and less than the liquid phase temperature.

Abstract: Process for fabricating a transistor, in which an electron-sensitive resist layer lying between at least two semiconductor fingers is formed and said resist lying between at least two wires is converted into a dielectric. For example, in one embodiment of the present disclosure an integrated circuit includes a transistor having an insulating substrate including, for example, based on silicon oxide. Transistor also includes a conducting gate region comprising, for example, TiN or polysilicon, formed on a localized zone of the upper surface of the substrate, and an isolating region, comprising, for example, silicon oxide and surrounding the conducting region. The conducting region is also bounded in the direction normal to the plane of the drawing.

Abstract: Example embodiments are directed to a method of forming a field effect transistor (FET) and a field effect transistor (FET) including a source/drain pair that is elevated with respect to the corresponding gate structure.