Abstract: A lock detecting circuit is disclosed that detects whether a PLL circuit is in a locked state based on a phase difference signal supplied from a phase comparator of the PLL circuit, the lock detecting circuit comprising a first circuit that outputs a control signal having one level when the phase difference signal does not indicate a generation of a phase difference, and the other level when the phase difference signal indicates a generation of a phase difference; a second circuit that latches the control signal; and a third circuit that outputs, for a predetermined second term, a lock detecting signal indicating that the PLL circuit is in a locked state, when the latched control signal indicates the one level for a predetermined first term.

Abstract: A voltage between both terminals of each unit battery is amplified by a differential amplifier and is then converted by a converter into a predetermined physical quantity that corresponds to the voltage between both terminals of the unit battery. The converted physical quantity is then level-shifted by a detection circuit and is converted into a voltage on a reference potential of the lowest electric potential of the battery assembly. A control unit sequentially selects the converted voltages by a multiplexer, generates serial digital signals by an A/D conversion, and then transmits the serial digital signals to a control operation unit via an isolation buffer circuit. It is, therefore, possible to provide a battery voltage measurement circuit capable of measuring a voltage of each of unit batteries constituting a battery assembly with high accuracy by using a common measurement circuit in a relatively simple and inexpensive configuration.

Abstract: A circuit component tester includes a portable casing and a circuit provided within the casing. A plurality of leads are provided to electrically connect the circuit to a gate and two terminals of a circuit component under test. A test switch provided on the casing initiates application of test voltage to at least one of the two terminals of the circuit component under test. A gate switch provided on the casing initiates application of gate voltage to the gate of the circuit component under test. At least one of the test switch and the gate switch are operable to verify functionality of the circuit component under test.

Abstract: A probe measurement system comprises a probe with a linear array of probe tips enabling a single probe to be used when probing a test structure with a differential signal.

Abstract: A magnetic detector, wherein the magnetic/electric conversion element is constituted by at least six segments symmetrically arranged in a direction in which the magnetic moving body rotates maintaining a predetermined pitch with respect to the center line of the magnet, first and second bridge circuits are constituted so as to produce outputs accompanying the rotation of the magnetic moving body, and a third bridge circuit is constituted so as to produce an output accompanying the rotation of the magnetic moving body, and wherein a comparison level of a comparator circuit that shapes the waveform of a differential output signal of the first and second bridge circuits is adjusted relying upon an output signal of the third bridge circuit.

Abstract: A sensor element for a revolution counter includes a laminated structure suitable to cause a change in magnetisation in the sensor element without a power supply, simply by the displacement of a magnetic field past the sensor element. Moreover, the laminated structure is suitable for storing a plurality of such changes. The sensor element has a spiral structure.

Abstract: The invention relates to a method of detecting surface defects on a continuously-cast crude metallic product, such as a steel slab (4). According to the invention, a sensor (10) is used to detect surface defects by means of eddy currents, said sensor consisting of a matrix comprising at least two rows (22, 24) of at least three adjoining measuring cells (21) which can be controlled by a multiplexing control unit (12). Moreover, each cell can generate eddy currents at the surface of the slab and, alternately, detect eddy currents in said surface. The inventive method comprises a step consisting in controlling a first transmitting cell and a second receiving cell from the same row, but which are separated from one another by at least one inactive cell.

Abstract: A current detection printed board includes: a board having a penetration hole that penetrates the board; and at least one wire that is formed in a coiled shape having both ends by penetrating the board along the periphery of the penetration hole and alternately connecting a front surface layer and a rear surface layer of the board, wherein, when a conductor, in which an AC current flows, is disposed to pass through the inside of the penetration hole, a current flowing in the wire is output through electromagnetic induction.

Abstract: The present invention provides a phase cycling method capable of obtaining images based on the phase cycling method in the same time as when no phase cycling method is used, and a magnetic resonance imaging apparatus therefor. In the phase cycling method, the amount of increment/decrement in the phase of each ?° pulse (i.e., RF transmission phase) is changed upon data acquisition in a positive low frequency domain on a k space and upon data acquisition in a negative low frequency domain to carry out phase cycling. The amount of increment/decrement in the RF transmission phase changes so as to differ at the start of data acquisition and the end of data acquisition. The amount of its change varies between 0 and a predetermined value. The predetermined value is set to such a degree that the amount of increment/decrement in the RF transmission phase is gradually changed, in such a manner that a steady state can be maintained on a pseudo basis.

Abstract: A method for generating a magnetic resonance images is provided. A magnetic resonance imaging excitation is applied. A plurality of magnetic resonance image signals is acquired. The plurality of image signals is combined iteratively by using a regularized decomposition algorithm. An image created from combining the plurality of image signals iteratively is displayed.

Abstract: In a method for image generation by magnetic resonance, a first MR raw data set is acquired with a first resolution in k-space, at least one further raw data set is acquired with a resolution in k-space that is reduced relative to that of the first raw data set, the acquired raw data sets are transferred into three-dimensional space for generation of image data the various image data are averaged for generation of an averaged image data set and the averaged image data set is displayed as an MR image.

Abstract: Head coil arrangement for a magnetic resonance apparatus has a housing with a number of coil elements arranged in or on the housing, and the housing has at least one movable and/or moldable housing part (2a) for adjustment to different neck shapes in the region designated for the neck of a patient.

Abstract: A method for generating a magnetic resonance images is provided. A first species signal for a first species is generated from magnetic resonance data. A second signal is generated from the magnetic resonance data. The first species signal is combined with the second signal to provide a recombined image. The recombined image may be displayed.

Abstract: There is described a magnetic resonance device incorporating at least one first component part, which when the magnetic resonance device is operating oscillates, attached by at least one local load-bearing joint to at least one second oscillation-sensitive component part of the magnetic resonance device, where the joint has at least one actuatable facility for generating counter-oscillations which damp an oscillation of the first component part, where the second component part is a cladding element, in particular a vacuum cladding, which is affixed to the magnet via the joint, whereby a gap between the cladding element and the magnet is evacuatable, and the gap is provided with a pressure-isolating acoustically soft seal, in particular in the form of bellows.

Abstract: An RF coil has at least one conductor loop and a parallel circuit provided with a first branch and a second branch is installed. The first branch has a first capacitor and the second branch has a third capacitor and a first parallel resonance circuit configured by a second capacitor and a first inductor. The first capacitor has capacity to allow the RF coil to resonate at the time of transmission/reception of the first resonance frequency signal corresponding to an element with a higher magnetic resonance frequency, and capacity of the second capacitor and a value of the first inductor are determined as an accumulated value thereof based on the first resonance frequency. The third capacitor has capacity to allow the RF coil to resonate at the time of transmission/reception of the second resonance frequency signal corresponding to an element with a lower magnetic resonance frequency.

Abstract: A method for predicting change in an operating state, e.g. state of life, for an electrical energy storage device includes establishing a plurality of values for an operating parameter, e.g. current, of the electrical energy storage device and, for each respective value, determining a corresponding change in the operating state for the energy storage device based upon the respective value. Preferably, change in the state of life is determined based upon an integration of electrical current, a depth of discharge of the energy storage device, and an operating temperature factor of the electrical energy storage device.

Abstract: A method for ascertaining operating parameters of an electrochemical storage battery, taking into account electrolyte stratification. The method including a) determining a first functional relationship between no-load voltage and state of charge as a value for the withdrawable charge in relation to nominal capacity of the storage battery, which is obtained in the state having electrolyte stratification in a discharge phase using the charge conversion since a prior no-load phase or pre-charge; b) determining a second functional relationship between no-load voltage and state of charge as a value for the withdrawable charge in relation to nominal capacity of the storage battery, obtained in the state having electrolyte stratification in a discharge phase using an accumulated charge conversion; and c) ascertaining operating parameters from the point of intersection of the first and second functional relationships and/or the slope of straight lines for describing the first and/or second functional relationships.

Abstract: In an electrochemical sensor, the potential difference applied to the electrochemical cell is raised to a measuring value at a rate determined to reduce the transient current.

Abstract: A method for testing lighting systems in tractors and trailers. To use the tester to check small trailers; connect male cord from trailer to female connection on tester. Connect 12V power supply cord to power supply, connect power supply to tester to check lighting system. To use tester to check semi-trailers: connect tester to the 7-way female connection in the front of the semi-trailer. Connect 12V power supply cord to power supply, connect power supply to tester to check lighting system or Abs. To use tester to check truck or tractor: connect supply cord from truck or tractor to 7-way female connection on tester. No power supply required. Activate tractor switch on tester. You will now be able to test each lighting system on the truck or tractor. The LED light on tester will indicate if system is working properly or not.

Abstract: An equipment monitoring device for monitoring a heating, ventilation, and air conditioning (HVAC) system configured to control an internal environment of a structure may include a current transformer configured to sense current being supplied from a power source to a first component of the HVAC system and a gauge configured to display the amount of current being supplied from the power source to the first component based on the current sensed by the current transformer.

Abstract: The invention relates to a measuring array with an earth connection point (5) for determining the insulation resistance (Riso) of an energized electrical apparatus or of an installation with a supply voltage UB with a positive pole (6) and a negative pole (7), two switches (S1, S2) or a corresponding two-way switch being provided for creating a current path between one of the two poles and said earth connection point (5) in order to determine the insulation resistance (Riso) generally obtained when one or a plurality of insulation faults occur at any potential reference, two measurements being performed one after the other for determining the insulation resistance, the first switch (S1) being closed and the second switch (S2) open during the first of these two measurements and the first switch (S1) being open and the second switch (S2) closed during the second of these measurements.

Abstract: An integrated circuit package includes at least two electronic circuits. A first of the at least two electronic circuits includes a digital input and a digital output and a test mode control line for setting the first integrated circuit chip into a determined test mode. The digital input includes at least two parallel input paths and the digital output includes at least two parallel output paths. The at least two parallel input paths and at least two parallel output paths provide a corresponding number of internal paths by which the first electronic circuit and a second electronic circuit can be tested essentially simultaneously.

Abstract: An apparatus and method to test components in a semiconductor test structure. On a semiconductor wafer, a test module implemented in one or more scribe lines between a plurality of semiconductor dies is used to test components in the semiconductor test structure. The test module may, for example, test electrical characteristics of chains of vias, transistors, and functional devices, such as oscillators. The test module contains a scan chain control coupled through a plurality of pass gates to each component to be tested. The scan chain control sequentially closes the pass gates to separately test the components in the semiconductor test structure. The test module further interfaces with an external testing device and the results of each test are compared with the expected results to identify faulty components.

Abstract: The inventions relate to methods for trimming integrated circuits. Various embodiments include providing a method to trim an integrated circuit wherein trim data is stored in an on-board memory and then sent off of the circuit to be operated on by an external device. Corresponding trim data is then sent back to the integrated circuit in order to potentially modify the function of one or more analog devices along the circuit. Other embodiments include methods for trimming integrated circuits wherein trim data is stored in an on-board memory and retrieved using an on-board sequencer. The retrieved data is used to modify a function of one or more analog devices on the integrated circuit.

Abstract: An adjustable test socket for aligning an electronic device with spring probes in a test fixture is provided having two adjustable walls or four adjustable walls.

Abstract: A plurality of calibration structures facilitate calibration of a probing system that includes a differential signal probe having a linear array of probe tips.

Abstract: There is reduced labor to directly connect two ports selected from ports of a network analyzer in order to measure transmission tracking errors. A network analyzer, to which a test set which branches four ports to nine ports (main port group: three ports, and sub port groups: three ports×2) is connected, includes transmission/reception ports, a transmission tracking error determining unit which determines transmission tracking errors of a combination of one of possible connections in the main port group and one of possible connections in the sub port groups for all the possible connections in the main port group based on signals before transmitted by the transmission/reception ports and reception signals, and a transmission tracking error deriving unit which derives other transmission tracking errors based on the transmission tracking errors determined by the transmission tracking error determining unit.

Abstract: A method and device for determining the linear response of an electrical multi-port component has an “estimation procedure” in which an estimated admittance matrix is determined by applying voltages to the ports of the component and measuring the response of the component. The estimation procedure can e.g. consist of a conventional measurement of the admittance matrix. The method further has a “measurement procedure” in which several voltage patterns are applied to the port. The voltage patterns correspond to the eigenvectors of the estimated admittance matrix. For each applied voltage pattern, the response of the component is measured. This allows to measure the linear response of the component accurately even if the .eigenvalues of the admittance matrix differ by several orders of magnitude.

Abstract: A system for monitoring the displacement of turbine blades that includes a turbine blade with a cutting tooth and one or more sensor wires, each sensor wire including a severable portion, that become severed by the cutting tooth as turbine blade displacement occurs. The sensor wires may be embedded in a honeycomb, which may be an area of abradable material attached to turbine shrouds. The sensor wires may include a plurality of radial sensor wires embedded in the honeycomb at varying predetermined radial distances from a turbine rotor. The sensor wires also may include a plurality of axial sensor wires embedded in the honeycomb at varying predetermined axial locations along the length of the honeycomb.

Abstract: A test structure including a differential gain cell and a differential signal probe include compensation for the Miller effect reducing the frequency dependent variability of the input impedance of the test structure.

Abstract: A test structure for characterizing integrated circuits on a wafer includes a differential cell outputting a differential mode signal in response to a differential mode input signal. The probe pads of the test structure are arrayed linearly enabling placement of the test structure in a saw street between dies.

Abstract: In a functional mode, the functional core logic of a die is connected to the input and output pads and the die performs its intended function. In a bypass mode, the input and output buffers of the functional core logic are disabled and pad sites of corresponding position between a first set of opposite sides and between a second set of opposite sides are electrically connected. In bypass mode the die is transformed into a simple interconnect structure between the first sides and between the second sides. The interconnect structure includes plural conductors extending substantially parallel to one another between the first sides and further plural conductors extending substantially parallel to one another between the second sides. While in bypass mode, signals from a tester apparatus can flow through the conductors between the first sides and between the second sides to access and test a selected die on a wafer.

Abstract: Products and assemblies are provided for socketably receiving elongate interconnection elements, such as spring contact elements, extending from electronic components, such as semiconductor devices. Socket substrates are provided with capture pads for receiving ends of elongate interconnection elements extending from electronic components. Various capture pad configurations are disclosed. Connections to external devices are provided via conductive traces adjacent the surface of the socket substrate. The socket substrate may be supported by a support substrate. In a particularly preferred embodiment the capture pads are formed directly on a primary substrate such as a printed circuit board.

Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consists of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.

Abstract: A method, system and apparatus for testing an integrated circuit chip. The system including: means for forming a liquid polyalphaolefine layer on a bottom surface of the integrated circuit chip, a top surface of the integrated circuit chip having and a bottom surface not having signal and power pads; means for placing a surface of a heat sink into physical contact with the bottom surface of the polyalphaolefine layer; means for electrically coupling the integrated circuit chip to a tester; means for electrically testing the integrated circuit chip; means for electrically de-coupling the integrated circuit chip from the tester; means for removing the heat sink from contact with the polyalphaolefine layer, all or a portion of the polyalphaolefine layer remaining on the bottom surface of the integrated circuit chip; and means for removing the polyalphaolefine layer from the bottom surface of the integrated circuit chip.

Abstract: A current abnormality detection system and method for shunt motors having a battery as a power source and an armature coil and a field coil controlled by an armature drive circuit and a field drive circuit formed in a controller, each drive circuit having a respective current sensor, An abnormal condition is determined when no less than a specified time has elapsed in a condition in which the difference between a current command value of the field coil with respect to the amount of current-flow in the armature coil and the current detection value of the field coil exceeds a given tolerance value.

Abstract: To strengthen tolerance to radiation. Source and back gate of P-channel transistor P1 are connected to power supply. Gate of the P-channel transistor P1 is connected to input terminal IN. Drain of P1 is connected to output terminal OUT. Source and back gate of N-channel transistor N1 are grounded. Gate of N1 is connected to IN. Drain of N1 is connected to OUT. Cathode of diode D1 is connected to power supply, anode of D1 being connected to OUT. Cathode of diode D2 is connected to OUT, anode of D2 being grounded. When seen from a direction perpendicular to a substrate on which an inverter circuit is formed, a projection plane of a region of a p+ diffusion layer 32 of D1 includes a projection plane of a region of an n+ diffusion layer 24 of N1, and a projection plane of a region of an n+ diffusion layer 41 of the diode D2 includes a projection plane of a region of a p+ diffusion layer 14 of P1.

Abstract: It is disclosed a combinatorial logic circuit comprising a first logic block (B1) coupled to a supply terminal (VDD) via a first resistor means (RI) and via a second resistor means (R2) for receiving respective first and second supply currents (111, 112). The circuit further comprises a second logic block (B2) coupled to the supply terminal (VDD) via the first resistor means (R1) and via the second resistor means (R2) for receiving respective third and fourth supply currents (122, 121). A first output terminal (Q?) coupled to the first block (B1) and to the first resistor means (R1). A second output terminal (Q+) coupled to the second logic block (B2) and to the second resistor means (R2). A first current source (I0) coupled to at least one of the first output terminal (Q?) and/or second output terminal (Q+) for providing a first supply current (I1) through the first resistor means (R1), which is substantially equal to a second supply current (I2) through the second resistor means (R2).

Abstract: Configurable voltage mode transmitter architectures are based on combinations of drive cells and parallel termination cells connected in parallel across an external load to provide configurable output characteristics. Each drive cell and parallel termination can be individually enabled, various configurations of enabled cells providing the output characteristics configurability. In some embodiments, dedicated or configured pre-emphasis drive cells with individual enablement capability are added. In some embodiments, pull-down and pull-up cells with individual enablement capability are added to provide additional configurability options. When present, the pre-emphasis, pull-down and pull-up cells are connected in parallel across the external load to provide pre-emphasis features to the output.

Abstract: A system including a plurality of transmission lines, a transmitter outputting respective signals to each of the plurality of transmission lines, a receiver receiving each of the plurality of signals via respective transmission lines, the receiver including a connection path connected to a termination voltage, a plurality of termination circuits distributed along the connection path, each termination circuit receiving a unique termination voltage from the connection path, receiving a respective signal and outputting a terminated input signal, a reference voltage generator including multiple reference voltage generator units connected to a common voltage, each reference voltage generator unit uniquely receiving at least one unique termination voltage and outputting a reference voltage, and a plurality of data input buffers receiving respective signals and an appropriate reference voltage of the multiple reference voltages output from the reference voltage generator.

Abstract: Integrated circuit chips with on-chip supply regulators with programmability and initialization. In one embodiment, an integrated circuit, includes: an initialization circuit to assert an initialization signal during powering up of the integrated circuit; a control circuit coupled to the initialization circuit; and a power supply regulator coupled to the control circuit, the power supply regulator to provide a first voltage to the control circuit when the initialization signal is asserted, the power supply regulator to provide a second voltage to the control circuit according to a control signal from the control circuit when the initialization signal is not asserted. In one embodiment, the integrated circuit includes a digital television demodulator.

Abstract: Methods and systems provide for a semiconductor die that is compatible with a wide variety of industry standard sockets, where each type of socket is identified by a different pin map. In one embodiment, the die has a plurality of signal lines, one or more surface contacts and one or more signal selectors coupled to the signal lines and the surface contacts. Each signal selector electrically connects one of the signal lines to one of the surface contacts based on a programming signal. In a particularl embodiment, each signal selector includes a multiplexer and a fuse element, where the multiplexer routes one of its input ports to its output port based on a programming value of the fuse element. The programming value can be set by the programming signal.

Abstract: Some embodiments of the invention provide a configurable IC that includes several configurable computational tiles and several memory tiles. These tiles are arranged in a particular tile arrangement. Each computational tile has a set of configurable logic circuits for configurably performing a plurality of computations and a set of configurable routing circuits. The routing circuits of the tiles configurably route signals between configurable logic circuits. The configurable IC also has several memory arrays for storing data on which the logic circuit perform computation. The memory arrays are embedded in the tile arrangement between two sets of memory tiles, where each set of memory tiles includes a set of routing circuits. In this IC, at least a first memory tile has the same set of configurable routing circuits as at least a second computational tile.

Abstract: Some embodiments provide a first interconnect circuit for accessing stored data in a reconfigurable IC. The reconfigurable IC has at least one reconfigurable circuit and a set of storage elements for storing several data sets for the particular reconfigurable circuit. The first interconnect circuit includes second, third, and fourth interconnect circuits, where the fourth interconnect circuit connects to outputs of the second and third interconnect circuits. The second and third interconnect circuits connect to the storage element sets to provide data sets to the fourth interconnect circuit, which, in turn, provides the received data to the particular reconfigurable circuit. The fourth interconnect circuit operates at a different rate than the second and third interconnect circuits. In some embodiments, the stored data sets are configuration data sets for configuring the particular reconfigurable circuit.

Abstract: A turning structure for routing channels in a field programmable gate array, comprising a first plurality of routing channels having a first direction and a second plurality of routing channels having a second direction. The first plurality of routing channels intersects the second plurality of routing channels to form a plurality of matrices of intersecting interconnect conductors in the routing channels. A first number of reprogrammable elements is disposed at intersections in at least one of the plurality of matrices, a second number of reprogrammable elements disposed at intersections in at least one of the plurality of matrices. The second number of reprogrammable elements is greater than the first number of reprogrammable elements, and a third number of reprogrammable elements disposed at intersections in at least one of the plurality of matrices. The third number of reprogrammable elements is greater than the second number of reprogrammable elements.

Abstract: A programmable array logic circuit whose temporary memory circuitry employs single bit non-volatile ferromagnetic memory cells. The ferromagnetic memory cells or bits store data even when there is no power provided to the circuitry, thus saving power during operation of the programmable logic circuitry, and ensuring that there is no loss of the data should there be a temporary power shut down. Additionally, the ferromagnetic cells provide for indefinite number of switching actions on the data without degradation to the capacity to store data therein. The invention provides an integrated circuit, comprising a programmable logic circuit array having product lines and input lines therein, and a storage register circuit. The storage register circuit has a ferromagnetic bit and sensor coupled to store a remnant control signal and an output transistor, coupled to be responsive to the remnant control signal on its gate, and coupled between an input and product line.

Abstract: A technique for terminating a differential signal line substantially matches the output impedances of a first node and a second node of a differential node. The power dissipation is substantially less than twice the power delivered to a load impedance coupled to the differential signal line. The technique provides a peak-to-peak, single-ended output voltage on the differential output node that is substantially independent of integrated circuit manufacturing process tolerances. An apparatus includes a differential node coupled to provide a differential signal. The differential node includes a first node and a second node. A first single-ended termination circuit is coupled to the first node and responsive to a first reference voltage. The apparatus includes a second single-ended termination circuit coupled to the second node and responsive to a second reference voltage.

Abstract: An exemplary signal transmitting circuit includes a drive circuit, a receiving circuit, and a filter circuit coupled between the drive circuit and the receiving circuit. The filter circuit includes a first photocoupler having a first luminous element and a first optical receiving block, an anode of the first luminous element is coupled to a power source, a cathode of the first luminous element is coupled to the drive circuit, an anode of the first optical receiving block is coupled to the power source and the receiving circuit, and a cathode of the first optical receiving block is coupled to ground.

Abstract: A floating driving circuit according to the present invention comprises an input circuit to receive an input signal. A latch circuit receives a trigger signal for generating a latch signal. The latch signal is used to turn on/off a switch. A coupling capacitor is connected between the input circuit and the latch circuit to generate the trigger signal in response to the input signal. A diode is connected from a voltage source to a floating supply terminal of the latch circuit for charging a capacitor. The capacitor is coupled between the floating supply terminal and a floating ground terminal of the latch circuit to provide a supply voltage to the latch circuit. The latch circuit is controlled by the input signal via the coupling capacitor.

Abstract: A sense amplifier-based flip-flop includes a first latch, a second latch, a floating reduction unit, an input signal applying unit, a ground switch and a delay reduction unit. The first latch outputs a signal to a first output terminal pair, and outputs an evaluation signal pair corresponding to an input single pair to the first output terminal pair. The second latch latches the evaluation signal pair and outputs the evaluation signal pair to a second output terminal pair. The floating reduction unit is controlled by signals of the first output terminal pair and is operationally connected between current passing nodes of the first latch to prevent the first output terminal pair from floating. The input signal applying unit is disposed between the current passing nodes and a ground terminal, and receives the input signal pair. The ground switch is disposed between the input signal applying unit and the ground terminal, and is controlled by the clock signal.