Abstract: A fast locking phase locked loop includes a first phase frequency detector (PFD), a second PFD, a lock detector, an up-signal output unit, a down-signal output unit, a selective charge pump, a loop filter, and a voltage-controlled oscillator (VCO). The first PFD outputs a first up-signal and a first down-signal. The second PFD outputs a second up-signal and a second down-signal. The lock detector outputs an inverted lock signal. The selective charge pump outputs a pumping current. The loop filter generates a control voltage in response to the pumping current. The VCO generates the external clock signal having a frequency determined in accordance with the control voltage. The PLL has a faster locking time because the PFDs included in the PLL are capable of detecting a phase difference in a missing edge.

Abstract: A driver circuit for providing an output signal for switching an electrical load on and off has a field-effect transistor having a gate terminal and an output for providing the output signal to the electrical load, a buffer circuit connected to the gate terminal of the field-effect transistor to impress a charge change current on the gate terminal of the field-effect transistor based on a drive signal, and a comparator having a first input for receiving the gate voltage and a second input for receiving the output signal to determine whether the gate voltage and the output voltage fulfill a predetermined relationship with respect to each other, and to provide the drive signal to the buffer circuit so that the charge change current is changed in magnitude when the predetermined relationship is fulfilled as compared to the charge change current when the predetermined relationship is not fulfilled.

Abstract: An inverting input buffer that uses the best features of an AC input buffer (low delay, high speed, high input voltage swing range) and a DC input buffer (stability, reliability, ‘automatic’ high and low data setup, input VIL and VIH “Voltage Input Low” and “Voltage Input High” margins). The delay though the buffer with a nominal load is very small. Optionally, a voltage tolerant input circuit is coupled to the DC input, which enables the DC input buffer to tolerate higher voltage swings, thus allowing a single buffer to switch both high (e.g. 2.5 volts-5 volts in a 1.2 volt system) and low input voltages (e.g. below 2.5 volts in a 1.2 volt system).

Abstract: In accordance with the invention, a driver circuit is described that permits a single thin gate oxide process to be utilized where a dual oxide process may normally be necessary. Circuits employing only thin gate oxide devices are used as the design basis for a single product with a single set of tooling and manufacturing process to operate within the same timing specifications for a core voltage output drive as well as for a higher system drive.

Abstract: A load control device includes a triangular wave generation portion which generates a triangular wave signal by charging/discharging a capacitor based on a constant current supplied from a constant current source, a load control portion which controls a load based on the triangular wave signal, and a temperature compensation element whose characteristic changes with a rise in temperature, which is provided to the constant current source.

Abstract: A system and method for power control for ASIC device is disclosed. According to an embodiment, the present invention provides a system for adjusting power consumption of an ASIC device. The system includes a first buffer. The first buffer is configured to receive and store data. The system also includes a controller that is configured to generate a control signal. The controller is coupled to the first buffer. The system additionally includes a processing unit coupled to the first buffer. The processing unit includes a first power source and a second power source. The first power source is different from the second power source. The processing unit is configured to receive the control signal from the controller. Additionally, the system includes a second buffer coupled to the processing unit. The second buffer is configured to receive and store processed data.

Abstract: A Delay Locked Loop (DLL) and method for generating multiple equally spaced phases over a wide frequency range is disclosed. The DLL includes a delay line, and a control module. The delay line receives a reference clock signal and outputs a final delay clock signal in response to the reference clock signal. The delay line includes a plurality of delay cells connected in series. The plurality of delay cells generate a plurality of delay clock signals having equally spaced phases. The control module generates a phase control signal based on counting a number of pulses of the reference clock signal that are input to the delay line before occurrence of a first corresponding pulse of the final delay clock signal.

Abstract: An amplifier circuit is configured to correct the duty ratio of a differential clock signal to a desired value of 50% via a differential amplifier including a MOS transistor pair. The clock signal to be corrected is applied to a respective gate terminal of the MOS transistor pair of the amplifier circuit, a differential analog duty ratio correction signal is generated by in each case integrating the true and complementary clock signal delivered by each MOS transistor at a source/drain terminal. The differential duty ratio correction signal is in each case applied to the electrically separated substrate terminals of the MOS transistor pair so that the substrate voltages, and thus the turn-on voltages of the MOS transistors of the transistor pair are in each case conversely influenced.

Abstract: Object To provide a highly accurate and stable pulse width modulation (PWM) pulse signal generation device compatible with high resolution images without increasing a basic frequency of an external oscillation circuit. Solving Means A PWM pulse signal generation device includes a first PLL control circuit 410, a ring oscillator 420 in which a plurality of basic delay elements are serially connected, and a delayed pulse generation circuit constituted by a delay ratio adjusting circuit 330 and a delay circuit 350. The delay circuit 350 is formed by setting one adjustment delay element having a delay ratio R that is adjusted by the delay ratio adjusting circuit 330 at a first stage and a plurality of serially connecting basic delay elements.

Abstract: A start up circuit of power converters is presented. It includes a first transistor, a resistive device, a second transistor, a third transistor and a diode. The first transistor is coupled to a voltage source. The third transistor is connected in serial with the first transistor to output a supply voltage to a control circuit of the power converter in response to the voltage source. The diode is connected from a transformer winding of the power converter to supply a further supply voltage to the control circuit of the power converter. The second transistor is coupled to control the first transistor and the third transistor in response to a control signal. The resistive device provides a bias voltage to turn on the first transistor and the third transistor when the second transistor is turned off. Once the second transistor is turned on, the third transistor is turned off and the first transistor is negative biased.

Abstract: A voltage supply apparatus includes a power noise sensing unit, a voltage selecting unit, a first power voltage supply unit and a second power voltage supply unit. The power noise sensing unit senses noise from first and second powers and outputs a power noise sensing signal. The voltage selecting unit outputs first and second driving signals in response to a voltage-supply-enable-signal and the power noise sensing signal. The first power voltage supply unit applies a voltage of the first power in response to the first and second driving signals. The second power voltage supply unit applies a voltage of the second power in response to the first and second driving signals.

Abstract: A redundant transition device between a waveguide (1) and at least two redundant processing circuits (2, 3) includes two uncoupled coplanar lines (5, 6) formed one on either side of a single substrate plate (4) and extending, in part at least, into the waveguide (1). Each coplanar line (5) has a longitudinal end (17) for connection to one (2) of the processing circuits, and a longitudinal transfer end (16), adapted to channel an electromagnetic wave between the waveguide and the slots (21, 22) of the coplanar line. Each coplanar line (5, 6) is provided with a phase shifting element (25, 26), for inverting the phase of an electric field on one side of the central transmission strip (7, 10) of the coplanar line.

Abstract: A delay line including a sequence of identical delay cells with improved gain and in built duty cycle distortion control and a method thereof is disclosed. Each delay cell of the sequence includes a current source, four transistors, and a load capacitor. A gate of the current source receives a voltage bias that controls a delay of the delay cell. A drain of the first transistor is connected to the drain of the current source. The first and second transistor gates receive an input clock signal. The second transistor drain is connected to the source of the current source. The third transistor gate and the load capacitor are also connected to the drain of the current source. The fourth transistor drain is connected to the third transistor drain. The fourth transistor gate is coupled to an output of a second consecutive delay cell for duty cycle distortion control.

Abstract: Delay circuitry is described that includes clock mixing circuitry to provide a selectable propagation time. Output signals from the mixing circuitry are selectively coupled through a variable delay line to synchronize two clock signals.

Abstract: In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of ?9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.

Abstract: A level conversion circuit includes an input section configured to receive a first signal of a first signal level and a correction signal and generates a second signal of a second signal level from the first signal and the correction signal. A level converting section converts the second signal into an output signal of a third signal level, and a duty correcting section generates the correction signal corresponding to a duty ratio of the output signal and outputs the correction signal to the input section.

Abstract: The switching element of the present invention is of a configuration that includes: an ion conduction layer (40) that includes an oxide, a first electrode (21) and a second electrode (31) that are provided in contact with the ion conduction layer (40) and that are connected by the precipitate of metal that is supplied from the outside or for which electrical properties change due to the dissolution of precipitated metal, and a third electrode (35) provided in contact with the ion conduction layer (40) and that can supply metal ions. The use of this configuration allows the switching voltage to be set higher than in the related art.

Abstract: A switch circuit device with improved insertion loss characteristics and isolation characteristics is provided. The switch circuit of the present invention includes a plurality of n-ch MOSFETs whose gates are connected together and whose drains and sources are connected in series, a p-ch MOSFET whose gate is connected to the gates of the plurality of n-ch MOSFETs and whose drain is connected to the source and drain of at least one pair of adjacent n-ch MOSFETs, and a voltage changing circuit for applying a low voltage to the source of the p-ch MOSFET while a high-level control voltage is applied to the gate of the p-ch MOSFET, and a high voltage to the source of the p-ch MOSFET while a low-level control voltage is applied to the gate of the p-ch MOSFET.

Abstract: A method and system for providing an output voltage greater than a voltage provided by a voltage supply in a semiconductor device are disclosed. The method and system include providing a plurality of clock signals, providing a first stage and providing a second stage. The first stage includes at least a first pumping node, a pumping capacitor and a device coupled with the pumping node, and an auxiliary capacitor pair for providing an undershoot for the device for value(s) of the clock. The auxiliary and pumping capacitors receive a first portion of the clock signals. The second stage includes at least a second pumping node. The first and second portions of the clock signals are provided to the first and second stages, respectively. The first stage and the second stage are configured to alternately charge and fully discharge based on the clock signals.

Abstract: A power supply circuit includes a first power supply configured to output a first voltage; a second power supply provided separately from the first power supply to output a second voltage; and a boosting circuit configured to use the first voltage as an input voltage to boost the input voltage toward a target voltage. The target voltage has a voltage width, and when an output voltage of the boosting circuit exceeds an upper limit of the target voltage, the input voltage is switched the first voltage of the first power supply to the second voltage of the second power supply.

Abstract: A power supply voltage controlling circuit that controls an output voltage at an output terminal to a desired set voltage, has a voltage regulator circuit that is connected to a first power supply and a second power supply that outputs a higher voltage than said first power supply, supplies a current to said output terminal from at least any of said first power supply and said second power supply, and compares the output voltage at said output terminal with a first reference voltage to adjust said output voltage to approach said first reference voltage; and a controller circuit that supplies said first reference voltage to said voltage regulator circuit and controls said voltage regulator circuit by outputting, to said voltage regulator circuit, at least any of a first enable signal for enabling said first power supply to supply a current to said output terminal and a second enable signal for enabling said second power supply to supply a current to said output terminal.

Abstract: A semiconductor device includes a current mirror circuit having a plurality of transistors; a current source configured to supply a constant reference current to the current mirror circuit through a node; and a compensating circuit configured to supply a compensation current to the node to compensate for at least a part of gate leakage currents of the plurality of transistors. The compensating circuit may supply the compensation current equal to a summation of the gate leakage currents.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A discrimination circuit of the present invention checks whether a received signal is noise or a signal that is repeated with interposed rest time periods, and is provided with a low-pass filter that has a cut-off frequency that is lower than the frequency of the noise but higher than the reciprocal of a total period of one frame of the signal that is repeated with interposed rest time periods and the rest time period, and a judgment circuit that judges, according to an output of the low-pass filter, whether the received signal is noise or a signal that is repeated with interposed rest time periods. With this configuration, it is possible to discriminate between noise and a signal that is repeated with interposed rest time periods, and achieve miniaturization.

Abstract: Methods are provided for solid-state implementation of a vacuum tube replacement device that supplements the functional performance of the target replacement device, i.e., a traditional glass vacuum tube. Example functions may include OEM or user adjustable parameters such as gain and/or frequency response (e.g. transfer function), current and/or voltage saturation thresholds, bias condition, input and/or output impedance, linear-to-non-linear transfer function(s) (e.g. soft clipping parameters), power dissipation, communication protocols, and audio/visual indication parameters such as signal limiting detection, safety, stress, or wear-out conditions, and tube emulation model type to name a few. The methods presented for the vacuum tube replacement device system(s) are equally useful for non-vacuum tube systems such as audio amplifier circuits.

Abstract: The invention relates to the distribution of a radio-frequency signal to various modules (20, 30, 40) on a printed circuit board (10). The radio-frequency signal supplied via an antenna plug (11) is led over a multi-section (12, 13, 14, 15) line, a respective decoupler (32) being inserted between two sections (13, 14). In addition, between two sections (13, 14) an amplifier (33) may optionally be provided for compensating for signal losses, and/or a switch (34) for separating non-active modules.

Abstract: The present invention provides an amplifier unit including a carrier amplifier biased for Class A or Class AB operation; a peak amplifier biased for Class B or Class C operation, wherein an input signal is input to the carrier amplifier and the peak amplifier, and wherein output signals from the carrier amplifier and the peak amplifier are synthesized to output therefrom; a comparator configured to compare a gate bias voltage of a transistor device in the peak amplifier with a predetermined threshold voltage and output a first output signal; and a failure detection circuit configured to output a second output signal indicating presence or absence of failure, based on the first output signal received from the comparator.

Abstract: A level-shifting amplifier is provided for level-shifting an input signal with a voltage magnitude that exceeds a supply voltage of the amplifier. In operation, the amplifier has an input impedance of greater than 100 MOhms.

Abstract: Provided are input-gain control apparatus and method of an audio amplifier. A gain of an acoustic signal is automatically attenuated based on a pre-set limited level to minimize distortion of the acoustic signal caused by clipping of the acoustic signal, and thereby limit an over-input of the acoustic signal to input the acoustic signal within a dynamic range if the acoustic signal is not input within the dynamic range in an audio apparatus including an acoustic amplifier and a switching amplifier. Thus, only a gain of an over-input signal on a specific level or more can be attenuated while an original form of the over-input signal is maintained to minimize distortion of an output waveform caused by clipping of the output waveform. Also, a harmonic distortion and a stepped high frequency noise occurring during clipping can be simultaneously removed.

Abstract: A method and apparatus for amplifying a signal modulated in amplitude using amplifiers having a given dynamic range corresponding to a limited conduction angle, comprising separating the signal in a first signal and in a second signal depending on the dynamic range of the amplifiers, wherein each of the first signal and the second signal has a corresponding phase assigned based on an amplitude of the signal, amplifying each of the first signal and the second signal using the amplifiers and combining the amplified signals.

Abstract: A predistortion method for CMOS Low-Noise-Amplifiers (LNAs) to be used in Broadband Wireless applications is presented. The method is based on the nulling of the third order Intermodulation distortion (IMD3) of the main amplifier by a highly nonlinear predistortion branch. Maximum third order product cancellation is ensured by a transformer feedback method. The technique improves linearity in a wide range of input power without significant gain and Noise Figure. (NF) degradation. Simulation results on a 1-V LNA indicate a 10.3 dB improvement in the Input Third-Order Intercept Point (IIP3) with a reduction of only 1 dB and 0.44dB in amplifier gain and NF respectively.

Abstract: An efficient method of amplifying a digital signal with reduced electromagnetic interference is disclosed. The invention applies an average amplitude detector to the input signal to control the clock frequency of a pseudo-random number generator so that the clock signal decreases when the average amplitude of the signal increases. The input signal and the pseudo-random number generator are compared to generate a control signal for a switching power amplifier followed by a low-pass filter. When the average amplitude of the input signal falls below a pre-determine threshold, the switching amplifier is placed in a sleep mode.

Abstract: A disclosed operational amplifier includes: a pair of differential stages; a cascode amplifier stage; and an output stage. A threshold voltage of an output transistor constituting the output stage is higher than a threshold voltage of other transistors.

Abstract: There is provided a device including a PMOS differential amplifier and an NMOS differential amplifier. The NMOS differential amplifier is coupled to the PMOS differential amplifier. The device is configured to operate as an inverter when a supply voltage is below a predetermined threshold.

Abstract: A fully differential sensing apparatus and an input common mode feedback circuit are provided. The input common mode feedback circuit includes a common mode error amplifier and a plurality of adaptive conductance elements. Each adaptive conductance element behaves with a low impedance characteristic when its anode voltage is greater than its cathode voltage by a positive threshold voltage or, on the contrary, when the anode voltage of such an adaptive conductance element is lower than its cathode voltage by a negative threshold voltage, the adaptive element also behaves with a low impedance characteristic; otherwise the aforementioned adaptive conductance element behaves with a high impedance characteristic. The common mode error amplifier and a plurality of such adaptive conductance elements form a negative feedback loop to effectively maintain the input common voltage of a fully differential input amplifier, which can be used for a fully differential sensing apparatus.

Abstract: It is an object of the present invention to provide an amplifier circuit that supplies a differential output signal (Voutp-Voutn) with a stable common mode potential (½×(Voutp+Voutn)) and a stable amplification characteristic. An essential feature of the invention is a control path (24, 26, 30, 28, 36, 38, 34, 32) feeding back into a control stage of the amplifier circuit for the combined control of the quiescent currents that flow through the output transistors (T1-T4), and of the common mode potential of the differential output signal. By means of this combination of two control functions in one and the same control path (24, 26, 30, 28, 36, 38, 34, 32) any coupling between separate control loops is avoided.

Abstract: An RF power amplifier includes first and second field effect transistors having a gate, a source, and a drain, having an output power rating of at least 200 watts, and operating with a drain-to-source voltage that is greater than 50 VDC. The transistors are configured as a push-pull amplifier. The amplifier further includes an RF signal input. A input transformer is connected to the RF signal input. The input transformer has respective balanced outputs connected to the gates of the transistors. A broadband output transformer has a first balanced input connected to the drain of one the transistors, and a second balanced input connected to the drain of the other transistor. The broadband output transformer has an input to output impedance ratio of 1:4.

Abstract: A transmitter of the invention, according to a first aspect, has first and second driving circuits with reverse-current prevention elements connected between output terminals and power supply terminals, and a control circuit which controls the outputs of the first and second driving circuits, the control circuit controlling the first and second driving circuits, during a transition from a first state in which the first and second driving circuits output a first or a second logic level to a second state in which the first and second driving circuits output an intermediate level between the first and second logic levels, to induce a third state in which a through current flows in the first and second driving circuits via the reverse-current prevention elements.

Abstract: A low cost, robust method and apparatus for controlling the gain of a power amplifier to compensate for changes that are gradual with time. The bias circuit of a power amplifier is sent one of three signals in response to a measurement of the average output power level of the power amplifier. If the average output power lever is less than a desired value, a signal to increment the bias current by a set amount is sent, so that the output power increases. If the average output power lever is more than the desired value, a signal to decrement the bias current by a set amount is sent. A third signal may be sent that causes the bias circuit to reset to a default value. The three signals may be sent as a two bit digital signal.

Abstract: A CMOS current mirror is provided that includes a current input, an input transistor, whose conductivity path is located between the current input and a reference potential terminal, a current output, an output transistor, whose conductivity path is connected to the reference potential terminal and which supplies the current output with an output current, a gate node common for both transistors, and a supply potential terminal. The current mirror further includes a first additional transistor, whose conductivity path is located between the supply potential terminal and the gate node and whose gate terminal is connected to the current input, and a second additional transistor, whose conductivity path is located between the gate node and the reference potential terminal and whose gate terminal is connected to the gate node.

Abstract: RF amplifier bias system for TDMA application. A bias circuit (200) is coupled to an RF power amplifier (201) circuit. The bias circuit includes a charge pump/sink circuit (215), a voltage reference circuit (204) and voltage scaling circuit (208, 210, 214). The bias system provides fast response time when transitioning between various bias voltages applied to an FET RF transistor (244).

Abstract: A frequency compensating circuit having a current-mode active capacitor is disclosed. The frequency compensating circuit includes a first transconductance amplifier and a current-mode active capacitor. The first transconductance amplifier amplifies a feedback voltage signal in a current mode to provide the amplified voltage to a first node. The current-mode active capacitor is coupled to the first node. Accordingly, the frequency compensating circuit may occupy a small area in the semiconductor integrated circuit because the frequency compensating circuit uses a capacitor having a small capacitance.

Abstract: A high-frequency circuit is provided. In the high-frequency circuit, a first PIN diode is provided in a signal line and a second PIN diode is provided between the signal line and ground so that an attenuating circuit is formed. A power supply is applied to one end of a series circuit composed of two resistors. The other end of the series circuit is connected to ground via a drain-source path of an FET. An AGC voltage is applied to a gate of the FET. A bias voltage in accordance with the AGC voltage is applied to a base voltage of a low-noise amplifier via the first and second PIN diodes so as t control attenuation of the first PIN diode and an operating current of the low-noise amplifier.

Abstract: Provided is a power amplifier which fits to a deep-submicron technology in radio frequency wireless communication. The power amplifier includes a cascode including a first transistor which receives and amplifies an input signal, and a second transistor which is connected to the first transistor in series and operated by a DC bias voltage; a third transistor which is connected between the cascode and an output end, operated by a dynamic gate bias and outputting a signal; and a voltage divider which includes first and second capacitors that are connected between the output end, i.e. a drain of the third transistor, and a ground in series, and provides the dynamic bias to a gate of the third transistor.

Abstract: A phase-slipping phase-locked loop which generates an output signal whose frequency is a non-integer multiple of a reference frequency. The PLL has a first input for receiving a first binary value i which specifies an integer portion of the frequency multiplier, and a second input for receiving a second binary value f which specifies a fractional portion of the frequency multiplier. A multi-phase VCO has a plurality v of outputs on equal phase shifted spacing. The phase slipping is applied every i cycles, and the second binary value f specifies a phase slip stride, such that the frequency multiplier equals i+f/v.

Abstract: The invention relates to a phase locked loop or “PLL” (12) and a method of operating a PLL (12), wherein a controllable oscillator (DCO) generates an output signal (CKout) and it is possible to switch between a first clock (CKin1 or CKin2) and a second clock (CKin2 or CKin1) for use as a PLL (12) input clock. In accordance with the invention, for the clock (CKin1 or CKin2) currently being used to generate the output signal (CKout) a phase difference is determined between this clock and a preset phase-shifted version (CK<1:8>) of the output signal (CKout) and is used to control the oscillator (DCO), whereas for the clock (CKin2 or CKin1) not currently being used to generate the output signal (CKout), the phase shift is adjusted.

Abstract: The invention concerns a phase locked loop or “PLL” (12) as well as a method for the operation of a PLL, in which a controllable oscillator (DCO) generates an output signal (CKout) of the phase locked loop, and a phase detector (PD) determines a phase difference between a clock signal (CKin) used as an input clock signal of the PLL (12), and the PLL output signal (CKout), and provides a phase detector output signal (PD_OUT) synchronising the oscillator (DCO) with the clock signal (CKin) used.

Abstract: Provided is a grid-type high-speed clock signal distribution network capable of reducing a difference in amplitude of a standing wave on a transmission line and of supplying a signal from any position. The network for transmitting the clock signal is such that ends of the differential signal transmission line are connected via an inductor, a low-amplitude segment is eliminated by a phase shift in the inductor and a standing wave of substantially uniform phase and amplitude is produced, wherein the number of lines connected to the grid point is made the same for entire grid points.

Abstract: A voltage control oscillator includes a first current source for providing a coarse tune current; a second current source for providing a fine tune current; and a delay line, coupled to the first current source and the second current source, comprising: a first delay cell, coupled to the first current source, for delaying a input clock according to the coarse tune current and outputting a delay clock; and a second delay cell, coupled to the second current source, for delaying the delay clock according to the fine tune current and outputting a output clock; wherein the coarse tune current is used to control the oscillating frequency of the voltage control oscillator close to a target frequency and the fine tune current is used to adjust oscillating frequency of the voltage control oscillator arrive the target frequency.

Abstract: Provided is a multi-mode open-loop type clock extraction apparatus. In the apparatus, a power divider block divides an input data signal into two data signals. A first band-pass filter block and a second band-pass filter block extract a first clock frequency component or a second clock frequency component contained in the data signal output from the power divider. A first amplifier block and a second amplifier block amplify the first clock frequency component and the second clock frequency component respectively. Accordingly, it is possible to extract the respective clock signals corresponding to N data rates from the N data signals with various data rates using a single clock extraction apparatus.