Patents Issued in December 27, 2007
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Publication number: 20070296448Abstract: Provided is an apparatus for sorting burn-in tested packaged chips, including a DC test unit performing a DC test on packaged chips, a DC failure/loading head moving in a first direction to load packaged chips onto the DC test unit, and an inserting head moving in a second direction perpendicular to the first direction to transfer DC test-passed packaged chips from the DC test unit to a burn-in board, wherein the DC test unit is moved in the second direction, close to the DC failure/loading head when loading the packaged chips onto the DC test unit and close to the inserting head when transferring the packaged chips to the burn-in board, to sort burn-in tested packaged chips. The structure in which the DC test unit is movable toward the DC failure/loading head and the inserting head makes it possible to reduce the distance which the heads have to travel and to prevent the DC failure/loading head and the inserting head from interfering with each other.Type: ApplicationFiled: June 12, 2007Publication date: December 27, 2007Inventor: Byoung Woo Kim
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Publication number: 20070296449Abstract: Access to integrated circuits of a wafer for concurrently performing two or more types of testing, is provided by bringing a wafer and an edge-extended wafer translator into an attached state. The edge-extended wafer translator having wafer-side contact terminals and inquiry-side contact terminals disposed thereon, a first set of wafer-side contact terminals being electrically coupled to a first set of inquiry-side contact terminals, and a second set of wafer-side contact terminals being electrically coupled to a second set of inquiry-side contact terminals. The edge-extended wafer translator having a central portion generally coextensive with the attached wafer, and an edge-extended portion extending beyond the boundary generally defined by the outer circumferential edge of the wafer.Type: ApplicationFiled: June 5, 2007Publication date: December 27, 2007Inventor: Morgan T. Johnson
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Publication number: 20070296450Abstract: A testing device for performing a white balance test on a display device of an electronic equipment is disclosed. The testing device includes a supporting body, a testing member, a position-adjusting member and a clipping member. The testing member is disposed on the supporting body and used to mask the display device and perform the white balance test on the display device. The testing member has a testing opening. The position-adjusting member is disposed on the supporting body for adjusting a position where the testing member is disposed on the supporting body. The clipping member presses the display device against the testing member when the position-adjusting member makes the testing member aligned with the display device such that the display device can be closely contacted with the testing member. Thus, the white balance test can be performed on the display device through the testing member.Type: ApplicationFiled: December 1, 2006Publication date: December 27, 2007Applicant: INVENTEC CORPORATIONInventors: Guan-Yu Huang, Chang-Long Pan, Shih-Tung Chan, Lei Ye, Michael Yang, Leo Yue
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Publication number: 20070296451Abstract: An LCD test device and a test process thereof are disclosed, in which a defect of an LCD panel is exactly identified through exact electrical connection between an LCD panel and a probe unit. The LCD test device includes a work table on which an LCD panel is mounted, a clamping unit on the work table, clamping a top surface of an edge of the LCD panel mounted on the work table, a probe unit electrically connected with a pad of the LCD panel fixed to the work table by the clamping unit, and a back light unit supplying light to the LCD panel fixed to the work table. Accordingly, since the defect of the LCD panel can be tested exactly, reliability of the test is improved, and it is possible to prevent yield and the cost from being reduced in advance.Type: ApplicationFiled: December 26, 2006Publication date: December 27, 2007Inventors: Dong Woo Kang, Soung Yeoul Eom, Ki Soul Yang
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Publication number: 20070296452Abstract: The present invention provides methods and systems for testing and inspection of a display panel. The methods involve the application of voltages to rollers or testing conductive films. By applying a potential difference to the appropriate rollers or testing conductive films, different optical states of a display panel can be displayed for inspection.Type: ApplicationFiled: May 22, 2007Publication date: December 27, 2007Inventors: Gary Kang, John Liu, Wanheng Wang, Yi-Shung Chaug
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Publication number: 20070296453Abstract: An inspection circuit is constructed by first inspection TFTs provided to one end sides of signal lines, and second inspection TFTs provided to the other end sides of the signal lines. By using both the first inspection TFTs and the second inspection TFTs, the driving capability can be secured while miniaturizing the first inspection TFTs and the second inspection TFTs. Therefore, the signal lines can be reliably inspected while saving the space for the inspection circuit.Type: ApplicationFiled: May 16, 2007Publication date: December 27, 2007Inventors: Hiroshi Ootaguro, Yoshio Iwai, Tetsuya Ohtomo
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Publication number: 20070296454Abstract: A power supply assembly that can be miniaturized even though an applied voltage to a load is rendered variable, and a semiconductor testing system using the same are put into practice. With an improvement of the power supply assembly for finding an error against a set voltage by feeding back an applied voltage applied to a load, and applying a predetermined voltage to the load by causing an output amplifier to increase and decrease amperage to be fed to the load on the basis of the error, it is characterized in provided a voltage converter causing a voltage level of a power supply voltage of the output amplifier to follow up a voltage level of the set voltage.Type: ApplicationFiled: May 21, 2007Publication date: December 27, 2007Applicant: YOKOGAWA ELECTRIC CORPORATIONInventor: Isamu Koura
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Publication number: 20070296455Abstract: Provided is a disconnection and short detecting circuit capable of detecting disconnection and short of a signal line transmitting a differential clock signal. A differential buffer part DB1 has a first comparator to compare a non-inverting clock signal inputted from a PADI and an inverting clock signal inputted from a PADR; a second comparator to compare a non-inverting clock signal and a reference potential Vref; and a third comparator to compare an inverting clock signal and the reference potential Vref. Their respective outputs are defined as Y, YI and YR, respectively. If the signal line of either a non-inverting clock signal or an inverting clock signal is disconnected, or short-circuited to a grounding potential VSS of a logical value Low, the logical values outputted from the second and the third comparators are equal for a long period of time in one cycle of the non-inverting clock signal or the inverting clock signal.Type: ApplicationFiled: April 5, 2007Publication date: December 27, 2007Applicant: RENESAS TECHNOLOGY CORP.Inventors: Atsuhiko Ishibashi, Yasuhiro Fujino
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Publication number: 20070296456Abstract: An electrical circuit comprising a line driver for providing Ethernet signals is disclosed. The line driver comprises a voltage mode line driver for producing 1000BT and 100BT Ethernet signals and an active output impedance line driver arranged parallel to the voltage mode line driver. The line driver is capable of producing 1000BT or 100BT or 10BT Ethernet signals, wherein either the voltage mode line driver or the active impedance line driver is active.Type: ApplicationFiled: May 11, 2007Publication date: December 27, 2007Inventors: Frank van der GOES, Christopher Ward, Jan Mulder, Ovidiu Bajdechi
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Publication number: 20070296457Abstract: Disclosed is a programmable logic circuit control apparatus capable of managing data with various bit widths and data lengths, generated by various processes to be executed by a programmable logic circuit, with a simple structure. A module address memory section (4) stores data indicating addresses of modules or conditions for branching processes and jump distances page by page. A write address and a read address of an internal data memory (2) are also stored in a page where the address of a module is stored. A circuit control section (5) reads data of each page from the module address memory section (4), and, according to the read data, reads a module, reconfigures a programmable logic circuit and reads data of a next page, or performs jump. When the programmable logic circuit is to be reconfigured, the circuit control section (5) performs an operation of supplying a write address and a read address to the internal data memory (2).Type: ApplicationFiled: February 21, 2005Publication date: December 27, 2007Applicant: TOKYO ELECTRON LIMITEDInventor: Syuichi Kikuchi
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Publication number: 20070296458Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function.Type: ApplicationFiled: June 21, 2006Publication date: December 27, 2007Applicant: Element CXI, LLCInventors: Steven Hennick Kelem, Jaime C. Cummins, John L. Watson, Robert Plunkett, Stephen L. Wasson, Brian A. Box, Enno Wein, Charles A. Furciniti
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Publication number: 20070296459Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function.Type: ApplicationFiled: June 21, 2006Publication date: December 27, 2007Applicant: Element CXI, LLCInventors: Steven Hennick Kelem, Jaime C. Cummins, John L. Watson, Robert Plunkett, Stephen L. Wasson, Brian A. Box, Enno Wein, Charles A. Furciniti
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Publication number: 20070296460Abstract: A semiconductor apparatus of the present invention includes a first to a fourth external terminals and a decoding circuit. The semiconductor apparatus in a first mode inputs a first encoded data from the first external terminal, decodes a second encoded data by the decoding circuit to generate a first decoded data, outputs the first decoded data from the fourth external terminal, and the semiconductor apparatus in a second mode, inputs the second encoded data from the first external terminal, outputs the second encoded data input from the first external terminal from the second external terminal, inputs the second encoded data output from the second external terminal from the third external terminal, decodes the second encoded data input from the third external terminal by the decoding circuit to generate a second decoded data and outputs the second decoded data from the fourth external terminal.Type: ApplicationFiled: September 28, 2006Publication date: December 27, 2007Applicant: NEC ELECTRONICS CORPORATIONInventors: Kazuhisa Takigawa, Kengo Okada
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Publication number: 20070296461Abstract: The present invention is directed to a system, method, and apparatus to transmit/receive TMDS signals using general purpose differential transmitter and receivers. In an embodiment, the general purpose differential transmitter and receivers are designed to operate with differential signaling schemes such as LVDS and LVPECL. In one aspect, embodiments according to the present invention enable the re-configuration of existing and fully-characterized LVDS/LVPECL transmitter/receiver cells to support TMDS (using minimal sets of external components). This provides considerable cost and development time savings, thereby allowing the development of products much more expediently. In another aspect, embodiments according to the present invention provide interfacing methods and systems between differential signaling schemes such as LVDS/LVPECL and TMDS.Type: ApplicationFiled: November 16, 2006Publication date: December 27, 2007Applicant: Radiospire Networks, Inc.Inventors: Wayne Wong, Mark Sankey, Samuel J. MacMullan, Steven S. Fastert, Jeff Winston, Tandhoni S. Rao
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Publication number: 20070296462Abstract: A logic circuit for high-side gate driver includes a p-MOSFET array connected to a first voltage source, an n-MOSFET array connected to a second voltage source, and a resistor arranged between the p-MOSFET array and the n-MOSFET array, wherein a first node between the resistor and at least one of the p-MOSFETs in the p-MOSFET array is connected to a first output terminal, and a second node between the resistor and at least one of the n-MOSFETs in the n-MOSFET array is connected to a second output terminal.Type: ApplicationFiled: May 4, 2007Publication date: December 27, 2007Inventors: Jong-Tae Hwang, Moon-Sang Jung, Jin-Sung Kim, Dong-Hwan Kim
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Publication number: 20070296463Abstract: A driver circuit with variable output voltage and current. A source input terminal of the driver circuit may receive a source control signal. A voltage control circuit may drive one of the terminals of a first switch to a source voltage. If the source input terminal receives an asserted source control signal, the first switch is turned on and the voltage control circuit drives an output terminal of the driver circuit to the source voltage. A source current mirror may regulate a source current provided to the output terminal of the driver circuit. A sink input terminal of the driver circuit may receive a sink control signal. If the sink input terminal receives an asserted sink control signal, a second switch is turned on and the output terminal is driven to a sink voltage. A sink current mirror may regulate a sink current provided to output terminal of the driver circuit.Type: ApplicationFiled: June 21, 2006Publication date: December 27, 2007Inventors: Paul F. Illegems, Srinivas Pulijala
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Publication number: 20070296464Abstract: Apparatus and methods for processing a clock input signal with a clock regeneration circuit to provide a clock output signal for coupling to a cascaded device. The clock output signal has a period substantially equal to the period of the clock input signal and a duty cycle independent of the duty cycle of the clock input signal. In one embodiment, the clock regeneration circuit includes a one-shot and a buffer. Also described are apparatus and methods for aligning a data output signal of a cascaded device to non-clock-triggering edges of a selected one of the clock input signal and the clock output signal.Type: ApplicationFiled: June 27, 2006Publication date: December 27, 2007Inventor: ZACHARY D. LEWKO
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Publication number: 20070296465Abstract: A domino logic test circuit includes a dynamic node, a precharge device for charging the dynamic node, and an output inverter for inverting an output of the dynamic node. A logic network is coupled to the dynamic node for discharging the dynamic node in accordance with logic. A footer device enables and disables the logic network. A keeper device is coupled to the dynamic node for retaining a charge state of the dynamic node while awaiting the logic network to operate in accordance with the logic. A test mode selection device is coupled to the dynamic node and is configured to enable a latch in the test mode. A phase selection device is configured to receive at least a wait signal and to enable selection of at least a precharge phase for charging the dynamic node to a voltage level, a write phase for generating a value to the latch based on the logic and the voltage level of the dynamic node, and a wait phase for enabling reading the value. The selection is based, at least partially, on the wait signal state.Type: ApplicationFiled: June 23, 2006Publication date: December 27, 2007Inventors: Waleed K. Al-Assadi, Pavankumar Chandrasekhar
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Publication number: 20070296466Abstract: A method for comparing phases of two signals including placing a first output node in a floating state, detecting a first edge of a first signal on a first input node after placing the first output node in the floating state, coupling the first edge of the first signal to the first output node and resetting the first output node to the floating state after coupling the first edge of the first signal to the first output node. A system for comparing phases of two signals can also be included.Type: ApplicationFiled: June 9, 2006Publication date: December 27, 2007Inventor: Francisco Fernandez
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Publication number: 20070296467Abstract: A method to detect a missing a clock pulse is provided. The method begins by providing a clock signal and a delayed clock signal. The delayed clock signal is then sampled to generate a sample of the delayed clock signal. A missing clock pulse may be detected if the sample of the delayed clock signal does not equal an expected value of the delayed clock signal.Type: ApplicationFiled: June 23, 2006Publication date: December 27, 2007Inventor: Mark L. Neidengard
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Publication number: 20070296468Abstract: A load drive device for driving an electrical load includes high-side and low-side transistors, and a switch. When the load is driven, each of the high-side and low-side transistors operates in a first mode where each of the high-side and low-side transistors is fully tuned on or in a second mode where each of the high-side and low-side transistors is controlled so that a load current flowing through the load is constant. When the load is driven, there is a first state where the high-side transistor operates in the second mode and the low-side transistor operates in the first mode and a second state where the high-side transistor operates in the first mode and the low-side transistor operates in the second mode. The switch switches between the first and second states to distribute heat generation between the high-side and low-side transistors.Type: ApplicationFiled: May 31, 2007Publication date: December 27, 2007Applicant: DENSO CORPORATIONInventor: Shouichi Okuda
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Publication number: 20070296469Abstract: A data receiving circuit is capable of properly receiving current modulated signals having a wide range of frequencies. According to an exemplary embodiment, the data receiving circuit includes a current mirror operative to receive a current modulated signal from an external device and to convert the current modulated signal to a voltage signal. A data slicer is operative to generate digital data responsive to the voltage signal.Type: ApplicationFiled: October 26, 2005Publication date: December 27, 2007Inventor: John Fitzpatrick
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Publication number: 20070296470Abstract: The present invention provides a semiconductor integrated circuit that can perform impedance control and slew rate control independently of each other and simplify the structure of a control circuit. An output circuit comprising plural output MOSFETs connected in parallel is used, from among the plural output MOSFETs, the number of output MOSFETS to be turned on is selected by a first control means to control output impedance, and slew rate is controlled by a second control means controlling a drive signal of the output MOSFETs to be turned on.Type: ApplicationFiled: August 9, 2007Publication date: December 27, 2007Inventors: Atsuhiro Hayashi, Takemi Negishi, Hiroshi Toyoshima
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Publication number: 20070296471Abstract: A semiconductor integrated circuit device includes a semiconductor substrate having a first area. A first counter is provided in the first area, cyclically counts and outputs a first counter signal as a result of counting. A global reset circuit is provided on the semiconductor substrate and outputs a global reset signal. A first local reset circuit is provided in the first area and outputs a first local reset signal upon receiving the first counter signal of a set value after supplied with the global reset signal. A first circuit is provided in the first area and supplied with the first local reset signal.Type: ApplicationFiled: August 15, 2005Publication date: December 27, 2007Inventor: Takeshi Ishigaki
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Publication number: 20070296472Abstract: Methods, circuits, devices, and systems are provided, including embodiments with local coarse delay units. One embodiment includes generating a first delayed signal, a second delayed signal, and a third delayed signal by delaying a clock reference signal with various time delays of a coarse delay line and local coarse delay units. This method embodiment also includes generating a clock output signal based on the first delayed signal, the second delayed signal, or the third delayed signal, depending on a phase difference between the clock reference signal and the clock output signal.Type: ApplicationFiled: June 9, 2006Publication date: December 27, 2007Inventors: Tyler J. Gomm, Kang Y. Kim
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Publication number: 20070296473Abstract: A semiconductor integrated circuit includes a delay line of a delay locked loop. The delay line of the delay locked loop includes a delay variation detecting unit that outputs a detection signal according to a variation in delay time using a reference clock signal, and a plurality of delay units that change a delay time according to the detection signal and delay the output of an input signal by the changed delay time.Type: ApplicationFiled: December 29, 2006Publication date: December 27, 2007Applicant: Hynix Semiconductor Inc.Inventor: Young-Hoon Oh
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Publication number: 20070296474Abstract: DLL circuit operating more stably at reset. Voltage comparator circuit 21 outputs comparison result signal to hold circuit 22 at first level when power supply voltage VAA is not higher than reference voltage REF and at second level when power supply voltage VAA exceeds reference voltage REF. Hold circuit 22 outputs reset signal RST that it has received to DLL circuit 23 as it is when comparison result signal indicates first level and at second level, hold circuit 22 holds reset signal RST until comparison result signal becomes first level and then outputs it to DLL circuit 23.Type: ApplicationFiled: May 29, 2007Publication date: December 27, 2007Inventor: Kei Sugimoto
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Publication number: 20070296475Abstract: A semiconductor integrated circuit including a first power supply region supplied with a first power supply voltage, and having a first clock distribution network, a second power supply region supplied with a second power supply voltage, and having a second clock distribution network, a first phase synchronizer which provides a first output signal obtained by making a phase of a reference clock signal for controlling a data input/output coincident with a phase of a clock signal at a first point of the first clock distribution network, to a second point of the first clock distribution network, and a second phase synchronizer which provides a second output signal obtained by making the phase of the reference clock signal coincident with a phase of a clock signal at a first point of the second clock distribution network, to a second point of the second clock distribution network.Type: ApplicationFiled: July 17, 2007Publication date: December 27, 2007Inventor: Kohei OIKAWA
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Publication number: 20070296476Abstract: A testing circuit includes a signal generator operative to provide a control signal in response to a reference clock signal. The control signal may include both alignment and timing information operative to synchronize the timing and output of the signal generator with a device under test. A clock recovery instrument is electrically coupled to the signal generator. The clock recovery instrument generates the reference clock signal in response to a clock signal from the device under test. The reference clock signal is synchronized with the clock signal from the device under test such that signal generator operation is synchronized with the device under test independent of the behavior of the device under test.Type: ApplicationFiled: May 9, 2007Publication date: December 27, 2007Inventor: Bent Hessen-Schmidt
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Publication number: 20070296477Abstract: A delay locked loop includes a storage element coupled to a data bus and produces a data synchronization signal. A phase detector receives a data clock signal and the data synchronization signal and produces a delay control signal. A first delay circuit produces a signal which is delayed relative to the data clock signal according to the delay control signal. A second delay circuit receiving the delayed signal produces a control signal coupled to a control input of the storage element by delaying the delayed signal an amount which causes the control signal to have a predetermined duty cycle.Type: ApplicationFiled: June 23, 2006Publication date: December 27, 2007Inventor: Robert L. White
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Publication number: 20070296478Abstract: An integrated circuit package includes a processing core for operating on a set of instructions to carry out predefined processes. A plurality of comparators perform compare operations within the integrated circuit package. At least one control register is associated with each of the plurality of comparators. The plurality of comparators are programmable to operate in a plurality of operating modes responsive to control bits established in the at least one control register by the processing core.Type: ApplicationFiled: March 30, 2007Publication date: December 27, 2007Applicant: SILICON LABS CP INC.Inventors: DONALD ALFANO, DANNY ALLRED, DOUGLAS PIASECKI, KENNETH FERNALD, KA LEUNG, BRIAN CALOWAY, ALVIN STORVIK, PAUL HIGHLEY, DOUGLAS HOLBERG
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Publication number: 20070296479Abstract: A delay circuit includes a delay time setting circuit to set a delay time of an output signal with respect to an input signal, a first transistor connected to an input terminal of the delay time setting circuit and configured to set a first voltage to the input terminal of the delay time setting circuit and a second transistor connected to an output terminal of the delay time setting circuit and configured to reset the output terminal of the delay time setting circuit to a second voltage and clear the reset of the output terminal of the delay time setting circuit after the first voltage is set.Type: ApplicationFiled: June 7, 2007Publication date: December 27, 2007Applicant: NEC ELECRONICS CORPORATIONInventor: Hiroyuki Takahashi
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Publication number: 20070296480Abstract: A clock circuit for an integrated circuit having at least one MOS transistor. The clock circuit includes a first circuit for inducing a degradation of the transistor as a function of time and means for measuring a parameter of the transistor that reflects a lowering of the performance of the transistor resulting from the degradation. This also includes a method of generating a counting value of clock circuit by inducing continuous degradation of an MOS transistor. The method could include measuring a parameter of transistor, reflecting a lowering of performance of transistor resulting from said degradation. The method could also include measuring the temperature and calculating the counting value of the clock from the value of said parameter, from the measured temperature and from a law of variation of the parameter as a function of time and temperature.Type: ApplicationFiled: April 26, 2007Publication date: December 27, 2007Applicant: STMicroelectronics (Crolles 2) SASInventor: Michael Denais
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Publication number: 20070296481Abstract: An offset adjusting apparatus adjusting an offset of an output signal output from an output terminal of an operational amplifier including one input terminal to which an input signal is to be input via a first resistor and the other input terminal to which a reference voltage is to be applied, the operational amplifier being connected between the one input terminal and the other output terminal, the offset adjusting apparatus comprising: an adjustment resistor configured to be capable of adjusting a resistance value, the adjustment resistor including one end to which an adjustment voltage for adjusting the offset is to be applied and the other end connected to the one input terminal of the operational amplifier; and a controlling unit configured to control the adjustment voltage applied to the adjustment resistor based on a DC level of the output signal to remove the offset.Type: ApplicationFiled: June 21, 2007Publication date: December 27, 2007Applicant: Sanyo Electric Co., Ltd.Inventor: Yasumasa Hayakawa
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Publication number: 20070296482Abstract: An independent control signal is transmitted to each of a driver control unit and an output transistor, so as to prevent the driver control unit and the output transistor from being made to operate at the same time and reduce through-current flows. Since the transistor ratio can be selected easily, the degree of designing flexibility increases and the speed enhancement is achieved.Type: ApplicationFiled: September 6, 2007Publication date: December 27, 2007Applicant: ELPIDA MEMORY, INC.Inventor: Kyoichi NAGATA
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Publication number: 20070296483Abstract: In one embodiment, a current sense circuit is formed with a pair of series connected switches that are used to steer a load current and form a current sense signal.Type: ApplicationFiled: September 9, 2005Publication date: December 27, 2007Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, L.L.C.Inventor: Hubert Grandry
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Publication number: 20070296484Abstract: A time limiter protects a light emitting diode coupled to an output of a current driver by preventing the light emitting diode from working overtime under a high current and from being overheated and burnt down, no matter whether a pulse width of an input pulse is larger or shorter than a delay time of the time limiter. The input pulse may be a periodic continuous input pulse, or a continuously-enabled pulse generated from a run-time error of software or hardware. The time limiter should be coupled with a discharging circuit for discharging the capacitor in the RC circuit while a periodic continuous input pulse was inputted, to keep the precise original pulse period and pulse width of the enabling signal to be outputted, and to prevent the time limiter from malfunctioning.Type: ApplicationFiled: September 17, 2006Publication date: December 27, 2007Inventor: Wen-Nan Hsia
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Publication number: 20070296485Abstract: A semiconductor device, has a main transistor that is a first-conductivity-type MOS transistor and has the drain connected to a first potential; a first switch circuit that is connected between the source of said main transistor and a second potential; a dummy transistor that is a first-conductivity-type MOS transistor whose source serves also as the source of said main transistor; and a second switch circuit that is connected between the drain of said dummy transistor and said first potential or said second potential.Type: ApplicationFiled: June 5, 2007Publication date: December 27, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Mitsuyuki ASHIDA, Mototsugu Hamada
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Publication number: 20070296486Abstract: A voltage generator circuit provides an output voltage that is higher than an input voltage. The voltage generator circuit includes an input terminal receiving the input voltage, and an output terminal providing the output voltage. A pre-charge element is coupled between the input terminal and the output terminal, and a capacitance circuit is coupled to the input terminal and to the output terminal.Type: ApplicationFiled: June 23, 2006Publication date: December 27, 2007Inventors: Luca de Ambroggi, Giacomo Curatolo
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Publication number: 20070296487Abstract: A voltage generation circuit may include a static current circuit and/or a current mirror. The static current circuit may include a first resistor. The current mirror may include a second resistor, a third resistor, and/or an output terminal.Type: ApplicationFiled: June 21, 2007Publication date: December 27, 2007Inventor: Masao Kuriyama
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Publication number: 20070296488Abstract: A semiconductor integrated circuit includes a logic circuit, a first and second switching device and an equalizer. The logic circuit includes a first circuit connected between a power supply voltage and a ground voltage supply line, and a second circuit connected between a power supply voltage supply line and a ground voltage. The first and second switching devices are connected between the power supply voltage and the power supply voltage supply line and between the ground voltage and the ground voltage supply line, respectively. The equalizer is connected between the power supply voltage supply line and the ground voltage supply line, and configured to adjust voltages of the power supply voltage supply line and the ground voltage supply line to be the same during a standby operation.Type: ApplicationFiled: June 21, 2007Publication date: December 27, 2007Inventor: Nam-Jong Kim
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Publication number: 20070296489Abstract: A digital audio system to store and reproduce a digital PWM signal and a method of processing an audio signal. The method includes; converting an audio source signal into a digital pulse width modulation (PWM) signal through a series of signal processing processes and storing the PWM signal in a separate storage medium, when an audio signal is reproduced, reading the digital PWM signal stored in the storage medium and decoding the signal into an analog PWM signal, and performing a power switching operation with the decoded analog PWM signal and extracting an audio signal.Type: ApplicationFiled: January 9, 2007Publication date: December 27, 2007Applicant: Samsung Electronics Co., Ltd.Inventors: Byoung-min Mun, Hae-kwang Park
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Publication number: 20070296490Abstract: A dB-linear variable gain amplifier, a method for creation, and a system includes an amplifier; a pair of resistor arrays operatively connected to the amplifier, wherein each resistor array comprises MOS transistor resistive switches; a differential ramp-generator circuit operatively connected to the pair of resistor arrays; and voltage control lines generated by the differential ramp-generator circuit, wherein the voltage control lines are operatively connected to each of the MOS transistor resistive switches in the pair of resistor arrays. The number of the voltage control lines that are operatively connected to the each of the MOS transistor resistive switches is equal to the number of resistors in a particular resistor array. The differential ramp-generator circuit is preferably operable to take an automatic gain control voltage and generate a series of differential ramp voltages and apply the series of differential ramp voltages to one of the MOS transistor resistive switches.Type: ApplicationFiled: June 21, 2006Publication date: December 27, 2007Applicant: Newport Media, Inc.Inventors: Hassan Elwan, Amr Fahim, Aly Ismail, Edward Youssoufian
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Publication number: 20070296491Abstract: A generalized amplifier architecture is described which employs noise-shaping feedback, and for which the output waveform closely resembles the input waveform.Type: ApplicationFiled: September 7, 2007Publication date: December 27, 2007Applicant: CIRRUS LOGIC, INC.Inventors: Babak Mazda, Farzad Sahandiesfanjani, Adya Tripathi
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Publication number: 20070296492Abstract: A balanced voltage amplifier is disclosed as comprising a single stage containing three pairs of vacuum tube triodes configured to amplify two input signals (+INPUT, ?INPUT) and to generate two output signals (+OUTPUT, ?OUTPUT). The balanced voltage amplifier offers high voltage gain, wide bandwidth and low output impedance. Local feedback may be applied between the outputs and the second pair of triodes. Overall feedback may be applied between the outputs and the first pair of triodes. If local or overall feedback is used, it will further broaden the bandwidth, lower the output impedance and improve the overall balancing.Type: ApplicationFiled: May 15, 2007Publication date: December 27, 2007Inventor: Chi Ming John LAM
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Publication number: 20070296493Abstract: In one embodiment of the present invention, a weight vector is generated based on a pre-distorted input signal and an output signal of an amplifier using a computation reduction technique. The computation reduction technique decomposes a number of multiplication operations between complex numbers such that a number of multiplications and a number of additions to generate the weight vector is reduced as compared to if the number of multiplication operations between complex numbers was not decomposed. An input signal for input to an amplifier is pre-distorted based on the generated weight vector.Type: ApplicationFiled: June 27, 2006Publication date: December 27, 2007Inventor: Robert Chuenlin Wang
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Publication number: 20070296494Abstract: A predistorter for correcting distortion caused by a memory effect in amplifying a signal by an amplifier is provided. In the memory PD 2 provided to the predistorter, the level detection means 21 detects the level of the signal, the coefficient output means 22 outputs the coefficient corresponding to the detected level, the delay means 23 delays the output coefficient, the difference detection means 24 detects the difference between the output coefficient and the delayed coefficient, the multiplication means 25 multiplies the detected difference with the signal, and the combination means 26 combines the result of the multiplication and the signal. Thus, the result of the combination is output to the amplifier.Type: ApplicationFiled: December 5, 2005Publication date: December 27, 2007Inventor: Naoki Hongo
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Publication number: 20070296495Abstract: The number of times of referring to of a storing unit in a distortion compensating apparatus is averaged and temporary degradation of the distortion property is avoided. The distortion compensating apparatus include a pre-distorting unit that applies a distortion compensating process to a transmission signal using a distortion compensation coefficient, a distortion compensation calculating unit that calculates a distortion compensation coefficient based on the transmission signal before the distortion compensation and a feedback fed back from an output of a distortion device, an address generating circuit that produces an address corresponding to the transmission signal, and a storing unit that updates the calculated distortion compensation coefficient to the produced address and that stores the produced address.Type: ApplicationFiled: August 22, 2007Publication date: December 27, 2007Applicant: FUJITSU LIMITEDInventors: Hideharu SHAKO, Yasuhito FUNYU, Takeshi OHBA
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Publication number: 20070296496Abstract: An apparatus for reducing offset voltage drifts in a charge amplifier circuit is disclosed. The apparatus includes a charge amplifier circuit and a bias current compensation circuit. The bias current compensation circuit supplies bias current to lower any offset voltage drift at the output of the charge amplifier.Type: ApplicationFiled: June 22, 2006Publication date: December 27, 2007Inventors: Arthur Russell Blumen, Kenneth R. Knowles
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Publication number: 20070296497Abstract: Embodiments of the present invention provide differential pair amplifier circuits including cross-coupled cascode transistors. Other embodiments may be described and claimed.Type: ApplicationFiled: June 27, 2006Publication date: December 27, 2007Inventor: Alexandra Kern