Abstract: A magnetic resonance diagnosing apparatus includes a generating unit which generates a plurality of slice images of a object for an imaging region, a determining unit which determines a plurality of slice regions for spectroscopy within the imaging region, and a measurement unit which measures a magnetic resonance spectrum of the object for each of voxels set on the plurality of determined slice regions.

Abstract: A device is disclosed for calibrating a magnetic resonance apparatus having a PET function. In at least one embodiment, the device includes at least one marker that is visible through magnetic resonance imaging and fixed with reference to the device; at least one holder, fixed with reference to the marker, for a receptacle for holding a PET tracer generating a PET signal during PET imaging; and at least one receptacle for holding a PET tracer.

Abstract: The present invention concerns a method and an apparatus for phase-calibrating an MRI pulse sequence which is used to calculate a linear phase and a constant phase to perform phase calibration on the scanned data, wherein a corresponding pre-scan without a phase encoding gradient is performed before a diagnostic scan. A reference echo is selected from the echoes obtained in the pre-scan. On the basis of the reference echo the constant phase is calculated to be used in performing the phase calibration in the scan. The constant phase that is obtained is correct and not affected by phase jumping. A further image reconstruction performed on the phase-calibrated data produces clear and artifact-free images.

Abstract: A method for improving the precision of time domain low field H-NMR analysis, the method comprising rotating a sample within a RF coil and acquiring multiple time domain signals for the sample at multiple orientations within the RF coil.

Abstract: The use of a superconducting resonator with continuous-wave (CW) excitation allows low-noise quadrupole resonance (QR) detection without the need for a lock-in amplifier. This allows detection times to be greatly reduced. Hence, for the first time, a CW QR spectrometer using a superconducting resonator can be used in a portable device, such as a hand-held wand for detecting explosives.

Abstract: A magnetic resonance imaging magnet includes a ferromagnetic frame. A pair of generally toroidal superconducting coil units overlie interfaces of side walls incorporated in the frame. Each coil unit may include a vessel having hollow support extensions extending into recesses in the side walls. The coil units may further include elongated, low-thermal conductance supports disposed within the support extensions. The frame may include pole stems projecting inwardly from the side walls, and the coils may be disposed in close proximity to the pole stems. Cryocoolers may be mounted to the frame so that the cryocoolers are substantially mechanically isolated from the coils of the coil units, but are in thermal communication therewith. The cryocooler mountings may be arranged for convenient servicing and installation of the cryocoolers.

Abstract: A probe adapted for characterization of a semiconductor wafer having a surface. In one embodiment, the probe includes a source of modulated light; an optical fiber in optical communication with the source of modulated light, the optical fiber having a face and comprises a fiber core; and a transparent conductive layer coating the face of the optical fiber. Light from the source of modulated light is directed along the fiber core of the optical fiber through the face of the optical fiber to the surface of the semiconductor wafer. The optically transparent conductive layer detects charges from the surface of the semiconductor wafer.

Abstract: An electric circuit for triggering a piezoelectric element, a fuel injection system of a motor vehicle in particular, is described. A first measuring shunt connected in series to the piezoelectric element is provided. Provided are two transistors connected in series whose shared connecting point is connected to the piezoelectric element. A second measuring shunt is also provided. The two transistors and the second measuring shunt are connected in series.

Abstract: A method of testing live AC circuits for neutral-ground, neutral-isolated ground, and isolated ground-ground faults, involves measuring impedances of circuit portions, including hot-neutral, neutral-ground, neutral-ground and isolated ground loops. In general either a test current generating a driving voltage is used, or in the case of hot-neutral, a load current generating a load voltage, and the voltage without current are use to measure voltage drop. These voltages are proportionate to the impedances of the circuits, which are expressed as ratios indicating the presence of faults. The method is reliable, despite much variation in circuit characteristics, including oversized neutral, shared neutral same phase, shared neutral opposed phase, supply line impedance, and high impedance grounds, it is easily able to detect faults across conductors and shared neutral loads.

Abstract: An appliance fault monitor for protecting electrical appliances against fault currents flowing. The alternating current to an appliance load controlled by a phase angle conduction controlled switching device is monitored. The intended non-conduction angle is determined and any current flowing in that angle is indicative of a fault. Repeated indications cause a circuit breaker to disconnect the load.

Abstract: An apparatus and associated method are disclosed for facilitating the testing of device connections, including functional shock and vibration testing of peripheral card slots or any other desired connector interface. In part, a power supply located on the peripheral device, or some other external power source, is used to power fault detection circuitry. In this way, faults can be identified, such as through visual fault indicators, without the necessity of powering the system. In addition, simulated peripheral cards are provided that include adjustable weights so that the weight distribution of an actual card can be simulated without the necessity of having a functional peripheral in hand.

Abstract: A method and apparatus for radio frequency vector calibration of s-parameter measurements to the tips of the wafer probe needles of an automatic test equipment production tester. The method involves a modified Line-Reflect-Line (LRL) calibration routine that uses a Thru-Reflect-Line to LRL shift to eliminate the need for a precisely characterized reflect standard used during a conventional LRL calibration. The method further involves de-embedding the non-ideal effects of the non-zero length thru standard used during the calibration routine to improve measurement accuracy of the tester. The apparatus may involve the use of RF relays to allow multiple wafer probe needles to share RF test ports.

Abstract: A nonlinear distortion is compensated based upon a characteristic relating to a characteristic of a device under test. An inverse characteristic measuring device measures an output signal output from the device under test as a result of supplying the device under test with an input signal generated by a signal source. Further, the inverse characteristic measuring device acquires an ideal signal output from the device under test based upon the input signal if the device under test is ideal. Moreover, the inverse characteristic measuring device acquires an inverse characteristic which is a relation of the ideal signal with respect to the output signal. This inverse characteristic is applied to a distortion compensator. The distortion compensator supplies the device under test with the input signal converted based upon the inverse characteristic. As a result, a signal output from the device under test is an ideal signal whose distortion caused by the device under test is compensated.

Abstract: A method for direct electrical detection of proteins, peptides and the like, and their interactions includes an electrode arrangement, a current/voltage provider, and a circuit analyzer. The electrode arrangement has an interdigitated electrode pair including a first electrode and a second electrode. Coupled to the electrode arrangement is a signal generator adapted to provide a signal (e.g., an alternating current or voltage) having a selected range of frequencies. The analyzer is coupled to the electrode arrangement and is operative to analyze an electrical parameter of the circuit as the signal is applied. An analytic method includes measuring changes in one or more parameters of the circuit over the range of frequencies. By such measurement, the device can determine whether a target moiety has been bound by a probe attached to the electrode(s). The device can also specifically identify the intermolecular system detected, i.e.

Abstract: Embodiments according to the present invention provide an Impedance-based Arc-Fault Determination Device (IADD) and method that, when attached to an electrical node on the power system and through observations on voltage, current and phase shift with a step load change, determine the effective Thevenin equivalent circuit or Norton equivalent circuit at the point of test. The device and method determine the expected bolted fault current at the test location of interest, which enables calculation of incident energy and the assignment of a flash-hazard risk category.

Abstract: An apparatus and method for measuring a capacitance on the sensor element using two charge rates. The two charge rates may be two charging rates, or alternatively, two discharging rates for discharging the sensor element. Alternatively, both the two charging and discharging rates may be used to measure the capacitance. The method may be performed by charging a sensor element of a sensing device for a fixed time at the first charging rate, and charging the sensor element at the second charging rate to reach a threshold voltage after charging the sensor element for the fixed time. The method may also be performed by discharging the sensor element for a fixed time at the first discharging rate, and discharging the sensor element at the second discharging rate to reach a threshold voltage after discharging the sensor element for the fixed time.

Abstract: A transmitter electrode for a capacitive sensing device comprises a conductive sheet material, said conductive sheet material comprising a first connecting point for connecting the electrode to an electronic sensing unit. According to the invention the conductive sheet material comprises at least one second connecting point for connecting the electrode to an electronic sensing unit, said second connecting point being arranged at a certain distance from said first connecting point so that said conductive sheet material forms a conductive path between said first and second connecting point. The first and second connecting point, which in use are both connected to the electronic sensing unit, enable to check the integrity of the transmitter electrode and the connection lines used to connect the transmitter electrode to the electronic sensing unit.

Abstract: A bioelectric impedance measuring circuit for applying a current to an organism and measuring a bioelectric impedance of the organism is disclosed that includes a pseudo-sine wave generating circuit for generating a pseudo-sine wave based on an input square wave, a voltage/current converting circuit for outputting current to the organism in correspondence with the pseudo-sine wave generated by the pseudo-sine wave generating circuit, and a processing circuit for generating the square wave and supplying the square wave to the pseudo-sine wave generating circuit and measuring the bioelectric impedance based on a voltage output from the voltage/current converting circuit. The pseudo-sine wave generating circuit is included in a semiconductor integrated circuit.

Abstract: A method of diagnosing corrosion risk of a buried pipe due to DC stray currents and/or AC voltages induced in soil employs a metal probe including a first, exposed part having a first specific resistivity, and a second, sealed reference part having a second specific resistivity. The probe is buried in the soil, and the AC current and voltage between the pipe and the probe are measured, from which the spread resistance is determined. The resistances of the first and second probe parts are determined by respectively passing first and second excitation currents through the first and second probe parts and measuring the voltages across them. The resistance measurements are stored, and the steps are repeated periodically. The corrosion of the first probe part is determined from the measurements according to an algorithm, and the pipe corrosion risk is diagnosed from an empirical combination of the corrosion of the first probe part, the spread resistance, and the AC voltage measured.

Abstract: Techniques for on-chip detection of integrated circuit power supply noise are disclosed. By way of example, a technique for monitoring a power supply line in an integrated circuit includes the following steps/operations. A first signal and a second signal are preconditioned. The first signal is representative of a voltage of the power supply line being monitored. The second signal is representative of a voltage of a reference power supply line. Preconditioning includes shifting respective levels of the voltages such that the voltages are within an input voltage range of comparator circuitry. Then, the preconditioned first signal and the preconditioned second signal are compared in accordance with the comparator circuitry. Comparison includes detecting when a difference exists between the voltage level of the preconditioned first signal and the voltage level of the preconditioned second signal.

Abstract: A micromechanical device may include one or more piezoresistive elements whose electrical resistance changes in response to externally or internally induced strain. The present invention leverages the piezoresistive properties of such devices to sense the positional state of the device. A sensing circuit may be integrated into the device that senses an electrical resistance of at least a portion of the micromechanical device and provides information regarding the positional state of the micromechanical device. The micromechanical device may be a compliant device that includes relatively flexible members such as mechanical beams or ribbons. The positional states may be continuous positional states (such as the position of an actuator) or discreet positional states (such as the positional state of a bistable memory device). In certain embodiments, the micromechanical device is a threshold detector that latches to a particular stable configuration when an applied force exceeds a selected value.

Abstract: In accordance with an increase in speed, a wiring structure has rapidly become more microscopic and thinner and a wiring layer has become extremely thin, and therefore, giving a contact load to a probe for the inspection as has been conventionally done causes damage to a wiring layer and an insulation layer because the probe penetrates not only the oxide film but also the wiring layer or because of a concentration stress from the probe. On the other hand, decreasing the contact load causes unstable continuity between the probe and an electrode pad. It is an object of the present invention to surely and stably inspect an object to be inspected by breaking an oxide film with a low stylus pressure.

Abstract: A probe card assembly can comprise a support structure to which a plurality of probes can be directly or indirectly attached. The probes can be disposed to contact an electronic device to be tested. The probe card assembly can further comprise actuators, which can be configured to change selectively an attitude of the support structure with respect to a reference structure. The probe card assembly can also comprise a plurality of lockable compliant structures. While unlocked, the lockable compliant structures can allow the support structure to move with respect to the reference structure. While locked, however, the compliant structures can provide mechanical resistance to movement of the support structure with respect to the reference structure.

Abstract: A circuit board with vias that are suitable for use as test pads can be made according to a method whereby a first end of a via is blocked prior to heating solder paste that covers the opposite end of the via. As a result, air is trapped in the via when the solder paste is heated, which prevents melted solder paste from flowing in. Instead, the solder paste forms a dome shaped test pad over the via, which facilitates contact with the test probe. When applied to OSP circuit boards, the result is an OSP board with at least via that has a blocking material at one end and a solder dome over the opposite end.

Abstract: A carrier tray for use with a prober is arranged to allow the prober to measure or test not only semiconductor wafers but also semiconductor packages and accurately position each of different-shaped semiconductor packages. A carrier tray 1 includes a lowermost tray 10 and an uppermost tray 20 interposing therebetween an intermediate tray 30. The lowermost and uppermost trays 10 and 20 are each of a circular shape having a diameter D1. A diameter D3 of the intermediate tray 30 is smaller than the diameter D1. The intermediate tray 30 is centrally formed with a screw hole portion 32 in which a locking spacer screw 22 is screwed. A semiconductor package 40 is to be placed in a package holding pocket 11. With the locking spacer screw 22, the intermediate 30 is slidable in an X and Y directions, so that the X and Y coordinates of the semiconductor package 40 are determined uniquely relative to the carrier tray 1.

Abstract: A probe card for testing a flip chip device is provided. In one embodiment, the probe card comprises a printed circuit board having a first surface and a second surface, the first surface configured to face the flip chip device; a frame for securing the printed circuit board in place; a plurality of probe pins extending from the first surface in a manner which causes free ends of the pins to contact a plurality of bumps on the flip chip device; and a support member attached substantially flush with the frame above the second surface of the printed circuit board.

Abstract: Disclosed herein are a test probe and a method of manufacturing the test probe. The invention has a simple structure, thus affording ease of manufacture, and eliminates contact resistance during a test, thus enhancing the reliability of the test. The test probe includes a probe part which is provided on the upper portion of the probe and contacts a contact terminal of an object to be tested. A spring part, providing elastic force, extends integrally from the lower portion of the probe part, so that current flows from the object to the lower portion of the spring part. According to this invention, the spring part is integrally provided on the lower portion of the probe part, thus having a simple structure and affording ease of manufacture, and measuring current is transmitted directly from the probe part to the spring part, thus eliminating contact resistance and shortening the signal path, therefore enhancing the reliability of a test.

Abstract: The present invention provides a semiconductor wafer characterized by including: a silicon substrate which includes chip regions and scribe regions; multiple-layered films formed on the silicon substrate; and a reference mark formed in at least one film constituting the multiple-layered films. In addition, the semiconductor wafer is also characterized in that the reference mark is located at least one of the vertices of a virtual rectangle covering the plurality of chip regions, and in that the reference mark is longer than one side of each of the chip regions.

Abstract: Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

Abstract: An integrated circuit is provided with latency detecting circuitry for detecting signal generation latency within one or more functional circuits and in response thereto to generate a wearout response. The wearout response can take a variety of different forms such as reducing the operating frequency, increasing the operating voltage, operating task allocation within a multiprocessor system, manufacturing test binning and other wearout responses.

Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function.

Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function.

Abstract: A semiconductor IC device includes at least one IO port, a core logic, and at least one fail-safe IO circuit, the fail-safe IO circuit being coupled between the core logic and the IO port, wherein the fail-safe IO circuit is configured to receive a predetermined control signal and to maintain the IO port at a predetermined impedance with respect to the predetermined control signal.

Abstract: Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may each receive a data segment to transmit and a plurality of data segments that other drivers will transmit. A driver controller may adjust the time at which the data segment is transmitted in response to the plurality of data segments that the other drivers will transmit. The adjustment may compensate for simultaneous switching noise and cross-talk by, for example, delaying the transmission of a data segment or changing the slew rate of the signal carrying the data segment.

Abstract: A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory devices. The branches are arranged in several layers of hierarchy, with the transmission lines in branches having the same hierarchy having the same length. Each transmission line preferably has a characteristic impedance that is half the characteristic impedance of any pair of downstream transmission lines to which it is coupled to provide impedance matching. A dedicated transmission line is used to couple an additional memory device, which may or may not be an error checking memory device, to the register.

Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element controller, an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. The element controller controls the execution of data operations by the circuit element. Function assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.

Abstract: Some embodiments provide a reconfigurable IC that includes at least two sections, each with several configurable circuits. Each configurable circuit configurably performs a set of operations. Each section stores multiple configuration data sets for each configurable circuit. Each configuration data set for a particular configurable circuit specifies the operation that the particular configurable circuit has to perform from the circuit's set of operations, where the configurable circuits of different sections iterate through different numbers of configuration data sets.

Abstract: An input circuit is provided that can identify three states of an external signal without complicated voltage adjustment and that can reduce the power consumption in a standby state.

Abstract: A current mode logic (CML)-CMOS converter comprises an input stage that is turned on/off by receiving an input voltage from the outside; a voltage control unit that outputs a constant voltage; a first switching unit that is connected to the input stage and the voltage control unit and is turned on/off by the constant voltage applied from the voltage control unit; and a second switching unit that is connected to the input stage and is turned on/off by a signal applied from the input stage.

Abstract: A logic gate includes a first driver to receive an input signal, and to control a connection between a first power source and a first node in correspondence with the input signal, a second driver coupled to the first node and a second power source, and to control a voltage of the first node, a third driver to control a connection between an output terminal and the first power source in correspondence with the voltage of the first node, a control transistor to control a connection between the third driver and the second power source, a fourth driver to control a connection between a gate electrode of the control transistor and the second power source, and a second capacitor between a first electrode of the control transistor and the gate electrode of the control transistor, wherein the transistors are a same type of MOS transistor.

Abstract: A logic circuit includes a first flip-flop configured to include a first input terminal introducing a clock, a first output terminal supplying the clock and a first internal wiring connecting the first input terminal and the first output terminal, and a second flip-flop configured to be adjacent to the first flip-flop and be supplied with the clock from the first output terminal.

Abstract: An address transition detector circuit includes an input node, an output node, a bandgap reference node, and Pbias and Nbias nodes having voltages derived from the bandgap reference node. First through fifth cascaded inverters are each powered by a p-channel and n-channel MOS bias transistors having their gates coupled respectively to the Pbias node and the Nbias node. The input of the first inverter is coupled to the input node. First and second capacitors are coupled respectively to ground from the outputs of the first and fourth cascaded inverters. A NAND gate has a first input coupled to the input node, a second input coupled the output of the fifth cascaded inverter, and an output coupled to the output node.

Abstract: An analog delay element for delaying an input clock signal to produce an output clock signal. The analog delay element includes a delay circuit for receiving the input clock signal and for providing an intermediate clock signal in response to a first bias voltage. A current mirror amplifier generates a first current in a first current branch in response to the intermediate clock signal, and generates a second current in a second current branch in response to the first current and a second bias voltage. The second current branch has an output node for providing the output clock signal having a logic level corresponding to the delayed intermediate clock signal logic level.

Abstract: A non-inverting dynamic register includes a domino stage, a mux, and an output stage. The domino stage evaluates a logic function based on at least one input data signal and a pulsed clock signal, and opens an evaluation window when the pulsed clock signal goes high, and pulls a pre-charged node low if it evaluates, and keeps the pre-charged node high if it fails to evaluate. The mux pulls a feedback node low if the pre-charged node goes low during the evaluation window, and pulls the feedback node high if the pre-charged node is high during the evaluation window. The output stage is coupled to the pre-charged node and the feedback node. The output stage provides an output signal based on states of the pre-charged and the feedback nodes.

Abstract: A non-inverting dynamic register includes a domino stage, a mux, and an output stage. The domino stage evaluates a logic function based on at least one input data signal and a pulsed clock signal, and opens an evaluation window when the pulsed clock signal goes low, and pulls a pre-discharged node high if it evaluates, and keeps the pre-discharged node low if it fails to evaluate. The mux pulls a feedback node high if the pre-discharged node goes high during the evaluation window, and pulls the feedback node low if the pre-discharged node is low during the evaluation window. The output stage is coupled to the pre-discharged node and the feedback node. The output stage provides an output signal based on states of the pre-discharged and the feedback nodes.

Abstract: An IC solution utilizing mixed FPGA and MLC arrays is proposed. The process technology is based on the Schottky CMOS devices comprising of CMOS transistors, low barrier Schottky barrier diode (SBD), and multi-level cell (MLC) flash transistors. Circuit architectures are based on the pulsed Schottky CMOS Logic (SCL) gate arrays, wherein a variable threshold NMOS transistor may replace the regular switching transistor. During initialization windows, existing FPGA programming techniques can selectively adjust the VT of the switching transistor, re-configure the intra-connections of the simple SCL gates, complete all global interconnections of various units. Embedded hardware arrays, hardwired blocks, soft macro constructs in one chip, and protocols implementations are parsed. A wide range of circuit applications involving generic IO and logic function generation, ESD and latch up protections, and hot well biasing schemes are presented. The variable threshold transistors thus serve 3 distinctive functions.

Abstract: Power switching systems often benefit from controlling the instant at which the power devices change state so as to minimize dissipation in these devices. Such systems often require fairly tight tolerances on reactive components and a relatively narrow frequency operating range to be certain these switching times occur as intended. This invention defines a system that can adapt the required switching instant over very wide changes in the reactive components.

Abstract: A semiconductor integrated circuit device reduces resources of an external memory and an amount of data of test patterns. A semiconductor integrated circuit device comprises: a terminal BSIN to input serial data from a boundary scan register circuit of the former stage, a terminal BSOUT to output the serial data to a boundary scan register circuit of the latter stage, a flip-flop circuit 21 as a first register to store data for a boundary scan and connected to the terminal BSIN, flip-flop circuits 24a and 24b as a second register to store configuration data for an IO circuit and connected to the terminal BSIN, and a selector 27 to select data output from the first register and the second register and output the data to the terminal BSOUT.

Abstract: A frequency switching method is used to make switching among a plurality of frequency signal sources each providing a specific frequency range covering multiple bands. The method includes steps of providing a target frequency data; selecting one of the frequency signal sources to output a first clock signal; generating a first frequency data according to the clock signal of the first frequency to compare with the target frequency data; outputting a second clock signal with the highest band of another one of the frequency signal sources possessing a frequency range higher than that of the selected frequency signal source when the target frequency data is greater than the first frequency data; and outputting the second clock signal with the lowest band of the selected frequency signal source when the target frequency data is smaller than the first frequency data.

Abstract: For dormant periods in which in data is not transmitted to a differential signal reception circuit, an amount of a constant current provided to output buffers of a differential signal transmission circuit is reduced. Consequently, power consumption in the differential signal transmission circuit and the differential signal reception circuit is reduced.