Patents Issued in February 14, 2008
  • Publication number: 20080036508
    Abstract: The switching element of the present invention includes: an ion conduction layer (4) in which metal ions can move freely; a first electrode (1) that contacts the ion conduction layer (4); and a second electrode (2) that contacts the ion conduction layer (4), that is formed such that the ion conduction layer (4) is interposed between the first electrode (1) and the second electrode (2), and that supplies metal ions to the ion conduction layer (4) or that receives metal ions from the ion conduction layer (4) to cause precipitation of the metal that corresponds to the metal ions. An introduction path (5) composed of the metal and of a prescribed width is further provided on the ion conduction layer (4) for electrically connecting the first electrode (1) and the second electrode (2).
    Type: Application
    Filed: December 22, 2005
    Publication date: February 14, 2008
    Applicant: NEC CORPORATION
    Inventors: Toshitsugu Sakamoto, Hisao Kawaura
  • Publication number: 20080036509
    Abstract: Phase correction circuits and methods for reducing phase skew between multiphase clock signals and a semiconductor device including the circuit are provided. The semiconductor device includes a phase correction circuit and an output buffer. The phase correction circuit corrects phase skew between multiphase clock signals and generates skew-corrected clock signals. The output buffer outputs data in synchronization with the skew-corrected clock signals. The phase correction circuit includes a phase corrector, a replication output buffer, a phase detector, and a controller. The phase corrector corrects a duty cycle of a first clock signal, a duty cycle of a second clock signal, and phase skew between the first and second clock signals and generates skew-corrected first and second clock signals. The replication output buffer has the same structure as a data output buffer and outputs replication data in synchronization with the skew-corrected first and second clock signals.
    Type: Application
    Filed: April 24, 2007
    Publication date: February 14, 2008
    Inventor: Young-Chan Jang
  • Publication number: 20080036510
    Abstract: A signal generating apparatus that is capable of accurately measuring a trip point of a power-up signal without installing a separate measuring instrument is described. An apparatus for generating a signal includes a power-up signal generating unit that generates a power-up signal using an external voltage and a measuring unit that outputs, when the power-up signal is enabled, the comparison result between a voltage generated on the basis of the external voltage and a reference voltage as a trip point.
    Type: Application
    Filed: June 29, 2007
    Publication date: February 14, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventor: Dong Kyun Kim
  • Publication number: 20080036511
    Abstract: This invention relates to line frequency synchronisation for use in diagnostics for alternating current electrical circuits. The invention provides a method of synchronising measurement system frequency with an alternating current line frequency comprising the steps of: adjusting the frequency of the measurement system frequency using a frequency locked loop until the measurement system frequency is within a predetermined range of said alternating current line frequency; and when the measurement system frequency is within a predetermined range of said alternating current line frequency adjusting the phase and the frequency of the measurement system frequency using a phase and frequency locked loop.
    Type: Application
    Filed: March 21, 2007
    Publication date: February 14, 2008
    Applicant: ICS Triplex Technology Ltd.
    Inventors: Thomas Meagher, Kenneth Murphy, Linda Murphy
  • Publication number: 20080036512
    Abstract: A signal delay circuit includes: a first inverter circuit; a second inverter circuit connected to an output terminal of the first inverter; and a feedback circuit extending from an output terminal of the second inverter to its input terminal. A delay time of the first inverter circuit is adjusted by controlling the amount of feedback through the feedback circuit. Here, the feedback circuit is formed by MOS transistors and the delay time is adjusted by controlling the gate voltages of the MOS transistors. The feedback amount is adjusted in relation to a variation in a power supply voltage and a variation in the delay time of the signal delay circuit is suppressed.
    Type: Application
    Filed: August 7, 2007
    Publication date: February 14, 2008
    Inventors: Keiichi Yamamoto, Norio Chujo
  • Publication number: 20080036513
    Abstract: To a frequency divider having a reset function, a second clock of a frequency N×Y times higher than that of a first clock is inputted. Upon receipt of a signal indicating that the stop of the input clock is detected by a start/stop detection circuit, the frequency divider having a reset function resets the dividing of a frequency. Then, upon receipt of a signal indicating that the resumption of the input clock is detected by the start/stop detection circuit, the frequency divider generates and inputs a third clock to a phase comparator by starting the dividing of a frequency.
    Type: Application
    Filed: February 1, 2007
    Publication date: February 14, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Yoshito Koyama, Koji Nakamuta
  • Publication number: 20080036514
    Abstract: A delay-locked loop (DLL) circuit with mutual-interpolating architecture that provides multiple-phase clock generation is presented. Each delay-cell in the DLL circuit delay chain is effectively an interpolator that combines two input clock signals: one input clock signal is received from the output clock of previous stage in the delay chain, and the other input clock signal is fed back from a following stage. Each delay cell supports the concurrent functions of delay and interpolation. The architecture imposes a set of N simultaneous equations, where N is the total number of delay clock signals, to control the clock waveforms. These simultaneous equations obtain a unique solution when the DLL enters a lock state, and the generated delay clock signals inherently have a clock duty cycle of 50%. The delay chain can be implemented using either odd or even number of delay cells.
    Type: Application
    Filed: August 8, 2006
    Publication date: February 14, 2008
    Applicant: Micrel, Incorporated
    Inventor: Gwo-Chung Tai
  • Publication number: 20080036515
    Abstract: A delay adjusting circuit including a delay part in which delay elements of n+1 (n?2) stages are connected to each other in series, a first phase comparator for detecting whether a first edge that is a transition edge of a signal of an n?1-th stage of the delay part from a first logic level to a second logic level advances from a first reference signal edge that is a transition edge of a first reference signal from the first logic level to the second logic level, a second phase comparator for detecting whether a second edge that is a transition edge of a signal of an n+1-th stage of the delay part from the first logic level to the second logic level delays from the first reference signal edge, and a delay element adjusting part that corrects a second reference signal so that the first edge advances from the first reference signal edge in the first phase comparator and the second edge delays from the first reference signal edge in the second phase comparator, and that outputs a reference bias signal for adjust
    Type: Application
    Filed: August 6, 2007
    Publication date: February 14, 2008
    Inventor: Shigetaka Asano
  • Publication number: 20080036516
    Abstract: An apparatus and method for improving memory cell reliability is disclosed. The slew rate is reduced in an applied voltage signal used to program a memory cell when Fowler-Nordheim (FN) tunneling injection is detected. The applied programming signal is provided by a charge pump that is preferably a regulated charge pump. The charge pump is selectively controlled by a slew rate control circuit when FN tunneling injection is detected by a voltage level detection circuit at a predetermined threshold voltage level.
    Type: Application
    Filed: August 9, 2006
    Publication date: February 14, 2008
    Applicant: Atmel Corporation
    Inventors: Jimmy Fort, Jean-Michel Daga
  • Publication number: 20080036517
    Abstract: A duty cycle correction circuit comprises a tuned circuit, a delay circuit and a phase-locked loop; wherein the tuned circuit receives an input clock, generates a periodic pulse according to the input clock, tunes the periodic pulse depending on a reference voltage, and outputs an output clock; a delay circuit receives the output clock, and generates a complementary signal; a phase lock loop receives the complementary signal, measures the periods of time of the high level state and the low level state of the complementary signal, generates the reference voltage and feeds back to the tuned circuit. By using the technique of the present invention, it is able to track the delay time between the input clock and the output clock, and the drift of the output clock is reduced.
    Type: Application
    Filed: August 14, 2006
    Publication date: February 14, 2008
    Inventors: Hsien-Sheng Huang, Chun Shiah
  • Publication number: 20080036518
    Abstract: An apparatus for generating a reference clock for a DLL circuit includes a buffering unit configured to buffer an external clock so as to generate a first reference clock and a second reference clock, and to invert the second reference clock so as to generate a negative second reference clock. A duty cycle compensating unit generates a reference clock from the first reference clock and the negative second reference clock.
    Type: Application
    Filed: June 26, 2007
    Publication date: February 14, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventor: Nam Pyo Hong
  • Publication number: 20080036519
    Abstract: An apparatus for controlling a voltage includes a reference voltage generator that generates reference voltage, and a bulk bias voltage generator that generates a bulk bias voltage using the reference voltage supplied by the reference voltage generator, and supplies the bulk bias voltage to the reference voltage generator to control the reference voltage.
    Type: Application
    Filed: June 26, 2007
    Publication date: February 14, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventor: Dong Keum Kang
  • Publication number: 20080036520
    Abstract: A power circuit includes: a frequency dividing circuit dividing frequency of a first signal to which level shift processing has been applied; a boosting circuit boosting voltage according to an output signal from the frequency dividing circuit or a second signal having lower frequency than that of the first signal as a boosting pulse; a level shifter; and a switching unit. The switching unit obtains boosted voltage output from the boosting circuit after boosting operation performed by the boosting circuit having received the second signal, inputs the boosted voltage output to the level shifter such that the level shifter can execute level conversion of the first signal, and stops the boosting operation performed according to the second signal, thereafter inputting the level-shifted first signal to the boosting circuit via the frequency dividing circuit to obtain final boosted voltage.
    Type: Application
    Filed: August 1, 2007
    Publication date: February 14, 2008
    Applicant: Sony Corporation
    Inventors: Yusuke Takahashi, Takayuki Nakanishi
  • Publication number: 20080036521
    Abstract: An interface circuit is provided for use in a semiconductor device which transmits and receives a signal to and from the outside. The interface circuit includes a signal input/output terminal for receiving a signal from the outside in a signal input mode and a signal from the semiconductor device in a signal output mode, an input buffer gate circuit having an input terminal connected to the signal input/output terminal and for outputting a signal received at the input terminal to the semiconductor device, and an input level control circuit for fixing a potential level at the input terminal of the input buffer gate circuit to a predetermined level in a signal no-supply mode and removing the fixation of the potential level in the signal output mode and in the signal input mode.
    Type: Application
    Filed: August 1, 2007
    Publication date: February 14, 2008
    Inventors: Toshiya Kogishi, Koji Yamada
  • Publication number: 20080036522
    Abstract: A level-shifting circuit includes a level shifter and a middle voltage generating unit. The level shifter generates a middle voltage signal by level-shifting a first signal. The middle voltage signal swings between a level of a ground voltage and a level of a middle voltage, and the first signal swings between the level of the ground voltage and a level of a first voltage. In addition, the level shifter generates a second signal by level-shifting the middle voltage signal. The second signal swings between the level of the ground voltage and a level of a second voltage. The middle voltage generating unit generates the middle voltage by receiving the second voltage and the ground voltage. Therefore, the level-shifting circuit increases an operating margin of an input voltage.
    Type: Application
    Filed: August 10, 2007
    Publication date: February 14, 2008
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dae-Young Chung, Sang-Kyu Kim
  • Publication number: 20080036523
    Abstract: A current mode multiplier circuit is provided based on the square root; voltage-current relationship of an MOS transistor. The circuit includes first, second and third MOS transistors with a common aspect ratio, and first and second current sources that respectively provide first and second input currents that represent first and second factors to be multiplied. The first and second MOS transistors produce first and second voltages as a function of the first and second input currents, and the third MOS transistor produces a third current as a function of the first and second voltages. In response to the third current, the circuit produces a product signal that represents a product of the first and second factors.
    Type: Application
    Filed: April 22, 2005
    Publication date: February 14, 2008
    Applicant: National Semiconductor Corporation
    Inventor: Manjo Nijrolder
  • Publication number: 20080036524
    Abstract: An apparatus for compensating temperature changes in a temperature associated with a compensated device includes: (a) An input circuit having a first input locus for receiving a temperature-indicating signal and a second input locus for receiving a sign-indicating signal. The temperature-indicating signal indicates magnitude of the temperature. The sign-indicating signal indicates a first sign when a control signal is greater than a predetermined value and indicates a second sign when the control signal is less than the predetermined value.
    Type: Application
    Filed: August 10, 2006
    Publication date: February 14, 2008
    Inventor: Ralph Oberhuber
  • Publication number: 20080036525
    Abstract: A temperature detecting circuit includes a temperature detecting unit that generates a first temperature detecting signal according to a temperature. A temperature information control unit generates a control signal by the first temperature detecting signal, supplies the control signal to the temperature detecting unit, and generates a second temperature detecting signal by the control signal and the first temperature detecting signal. A temperature information output unit generates a temperature information signal in accordance with the second temperature detecting signal and the control signal.
    Type: Application
    Filed: June 29, 2007
    Publication date: February 14, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventor: Dong Kyun Kim
  • Publication number: 20080036526
    Abstract: A control circuit for use in controlling a phase of a multi-phase voltage converter in accordance with an embodiment of the present invention includes a driver operable to provide a first control signal to a high side switch of a half-bridge of the phase and a second control signal to a low side switch of the half bridge, such that a desired output voltage is provided by the phase, current sensing circuitry operable to detect the output current of the phase, a comparator operable to compare the output current to a threshold current value and a disabling device operable to provide an enable/disable signal to disable the driver when the output current is below the threshold current value.
    Type: Application
    Filed: August 8, 2007
    Publication date: February 14, 2008
    Inventors: Wenkai Wu, George Schuellein
  • Publication number: 20080036527
    Abstract: The invention provides an electrical fuse device comprising: a plurality of fuse cores, each having an electrical fuse element and a switching element serially connected to the electrical fuse element; a program control circuit generating a program shift signal by sequentially shifting a program control transmission signal in synchronization with an effective program clock signal and subsequently generating a program signal to be sent to each of the switching elements in the plurality of fuse cores based on program data and the program shift signal; and a program clock control circuit controlling the conducting and non-conducting states of a program clock signal in accordance with a program clock enable signal and, when the program clock signal is in a conducting state, transmitting the program clock signal to the program control circuit as the effective program clock signal.
    Type: Application
    Filed: August 8, 2007
    Publication date: February 14, 2008
    Inventors: Ryuji Nishihara, Yasuhiro Agata, Toshiaki Kawasaki, Shinichi Sumi
  • Publication number: 20080036528
    Abstract: A charge pump circuit including a plurality of controlled charge pumps (CPs), a plurality of uncontrolled CPs, a plurality of control units, and an output unit is provided. Each controlled CP determines whether to provide charges to a node by a control signal, and each uncontrolled CP constantly provides charges to the node. The higher the node voltage at the node is, the more the controlled CPs not providing charge to the node are, so as to suppress the voltage of the node. In addition, the output unit regulates and outputs an output voltage according to the node voltage by the negative feedback.
    Type: Application
    Filed: August 10, 2006
    Publication date: February 14, 2008
    Applicant: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventors: Chung-Zen Chen, Chung-Shan Kuo, Yang-Chieh Lin
  • Publication number: 20080036529
    Abstract: A power supply circuit which boosts a given voltage to generate one or more power supply voltages includes a charge-pump control circuit including switching elements for generating a boost voltage by a charge-pump operation using charge stored in a flying capacitor, a soft-start circuit which prevents a rush current toward the flying capacitor, and a power supply generation circuit which is connected with a stabilization capacitor and generates a power supply voltage using the boost voltage as a power supply. After the power supply generation circuit has been turned ON in a state in which the charge-pump control circuit generates the boost voltage by the charge-pump operation, the switching elements are turned OFF, and the soft-start circuit generates the boost voltage by a charge-pump operation.
    Type: Application
    Filed: August 1, 2007
    Publication date: February 14, 2008
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Hisanobu Ishiyama
  • Publication number: 20080036530
    Abstract: A circuit for providing a reference voltage includes a bandgap reference circuit, the bandgap reference circuit providing a first reference voltage and a data storage. The data storage stores a digital value corresponding to the first reference voltage. A digital to analog converter is coupled to the data storage for providing a second reference voltage corresponding to the digital value. The circuit also includes an output switch circuit responsive to at least one control signal, the output switch circuit providing either the first reference voltage or the second reference voltage to an output node responsive to the control signal.
    Type: Application
    Filed: August 9, 2006
    Publication date: February 14, 2008
    Applicant: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventor: Chien-Yi Chang
  • Publication number: 20080036531
    Abstract: A charge pump circuit employs an oscillator powered by a variable positive supply voltage, storage and switching circuitry controlled by an oscillator signal from the oscillator, and a regulator that maintains a negative supply voltage generated by the storage and switching circuitry at a target value through control of the variable positive supply voltage. The charge pump can be used in a power stage employing normally on switching transistors (such as silicon carbide junction FETs or SiC JFETs) that require a negative voltage to be turned completely off. Such power stages are in turn useful in applications including military aerospace applications having harsh electromagnetic interference (EMI) conditions, where they may be controlled by optical control signals conveyed by optical fibers from a more benign operating environment within the body of an aircraft.
    Type: Application
    Filed: August 3, 2006
    Publication date: February 14, 2008
    Applicant: HR Textron Inc.
    Inventor: Ronald Scott Boe
  • Publication number: 20080036532
    Abstract: A method to reduce transmitted output power and the battery consumption is provided. This involves first determining the required output level. The amplitude of the input signal provided to a PA driver may be based on the required output power level. This amplitude may be set by a PGA. A number of cascode bias signals are also provided to the PA driver. These cascode bias signals are based on the required output power level as well. Reducing the cascode bias signals by enabling/disabling circuits within the PA driver allows power consumption of the wireless device to be reduced.
    Type: Application
    Filed: August 11, 2006
    Publication date: February 14, 2008
    Applicant: Broadcom Corporation, a California Corporation
    Inventor: Meng-An (Michael) Pan
  • Publication number: 20080036533
    Abstract: Embodiments of the present invention may provide a Doherty amplifier that includes a first amplifying path and at least one second amplifying path. The first amplifying path may include a carrier amplifier to amplify an input signal in a Class 1 mode. The second amplifying path may include a supplementary input matching circuit to input-match the input signal, a phase shifter to phase-shift an output from the supplementary input matching circuit, and a peak amplifier to amplify an output from the phase shifter in a Class 2 mode. The second amplifying path may further include a supplementary output matching circuit to output-match an output from the peak amplifier. The second amplifying path may provide an equivalent amplified output equivalent to the first amplifying path by cooperation of the supplementary input matching circuit and the supplementary output matching circuit.
    Type: Application
    Filed: July 19, 2007
    Publication date: February 14, 2008
    Inventor: Jun Youl Lim
  • Publication number: 20080036534
    Abstract: The present invention discloses an adjustable gain power amplifier circuit. The adjustable gain power amplifier circuit includes a power amplifying unit for receiving and amplifying an input signal to generate an output signal; a power detecting unit for detecting power of the input signal to generate a detecting signal; and a biasing control unit for generating a biasing signal according to the detecting signal and to output the biasing signal.
    Type: Application
    Filed: August 6, 2007
    Publication date: February 14, 2008
    Inventor: Ren-Chieh Liu
  • Publication number: 20080036535
    Abstract: An amplifying circuit of a semiconductor integrated circuit includes a data amplifier that outputs an up-signal and a down-signal amplified according to a comparison result between an up-data signal and a down-data signal in response to a control signal. The data amplifier repeats an operation of amplifying the up-signal and the down-signal according to the comparison result between the up-signal and the down-signal to be fed back to the data amplifier.
    Type: Application
    Filed: June 28, 2007
    Publication date: February 14, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventor: Sung-Joo Ha
  • Publication number: 20080036536
    Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. The filters incorporate a gain stage that provides improved dynamic range through the use of cross coupled auxiliary differential pair CMOS amplifiers to cancel distortion in a main linearized differential pair amplifier. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically.
    Type: Application
    Filed: August 17, 2007
    Publication date: February 14, 2008
    Applicant: Broadcom Corporation
    Inventor: Haideh Khorramabadi
  • Publication number: 20080036537
    Abstract: A CMOS low-noise wide-band amplifier (LNA) 211 is provided. The LNA can include a Gm doubler 410, a source follower 420, and a coupling circuit (430/440) that couples a differential input to the Gm doubler with the source follower for achieving high linearity over a wide frequency range at a low supply voltage. The coupling circuit can capacitively couple (434/444) a differential input to a gate of the source follower. The gate can be biased to a supply voltage through variable resistors (436/446). A cross coupler (480) can be included in a push-pull buffer (450) for additional gain and for allowing the source follower to drive a low impedance load at low power.
    Type: Application
    Filed: August 11, 2006
    Publication date: February 14, 2008
    Applicant: MOTOROLA, INC.
    Inventor: Shafiullah Syed
  • Publication number: 20080036538
    Abstract: A rail-to-rail class AB amplifier includes an input circuit for converting a voltage difference between a first input signal and a second input signal into respective currents, a first current adder circuit for adding a drain current of a first input NMOS transistor and a drain current of a second input NMOS transistor, a second current adder circuit for adding a drain current of a first input PMOS transistor and a drain current of a second input PMOS transistor, a floating current source for controlling a bias current of the first current adder circuit and the second current adder circuit, a control circuit for controlling a voltage level of the drain terminal of a second cascode PMOS transistor and a second cascode NMOS transistor, and an output circuit coupled to the drain terminals of the second cascode PMOS transistor and the second NMOS transistor.
    Type: Application
    Filed: July 11, 2007
    Publication date: February 14, 2008
    Inventor: Myung-Jin Lee
  • Publication number: 20080036539
    Abstract: Power amplifier circuit outputs an output voltage corresponding to an input voltage supplied, and includes positive and negative-side output units including a positive or negative-side output resistor and a positive or negative-side transistor having its source terminal connected to one end of the positive or negative-side output resistor to make a current corresponding to a voltage supplied to its gate terminal flow to the positive or negative-side output resistor, positive and negative-side bias generating units which generate a positive or negative-side bias voltage corresponding to the input voltage, and positive and negative-side control units which control the voltage to be applied to the gate terminal of the positive or negative-side transistor such that the positive or negative-side bias voltage and source voltage of the positive or negative-side transistor become generally equal, and the voltage at connection node between the positive and negative-side output units is output as the output voltage.
    Type: Application
    Filed: July 13, 2007
    Publication date: February 14, 2008
    Applicant: ADVANTEST CORPORATION
    Inventor: SATOSHI KODERA
  • Publication number: 20080036540
    Abstract: An amplifier arrangement and a method for amplifying a signal. A transistor (1) is used to amplify an input signal (inp) and to provide an intermediate signal (out1). The intermediate signal is amplified to form an output signal (out) which is fed back to the transistor (1).
    Type: Application
    Filed: June 19, 2007
    Publication date: February 14, 2008
    Applicant: austriamicrosystems AG
    Inventors: Thomas Frohlich, Nicole Heule
  • Publication number: 20080036541
    Abstract: To improve operation during cutback power mode by reducing gain expansion, sections of a multi-section amplifier are selectively biased. During cutback power condition, fewer than all sections of the multi-section amplifier are biased. Selective biasing reduces power consumption and obtains desired output power. To reduce gain expansion, a bias resistor is provided between one or more sections to establish a small or leakage bias current into non-enabled or non-biased sections. This leakage bias current weakly biases the non-enabled sections allowing small signal amplification by the non-enabled sections. The combined amplification of the enabled section and the weakly biased section provide greater initial gain at lower power input signal levels thereby reducing gain expansion.
    Type: Application
    Filed: August 8, 2006
    Publication date: February 14, 2008
    Inventor: Philip Howard Thompson
  • Publication number: 20080036542
    Abstract: A power supply device for driving an amplifier includes a first power generator, a second power generator, a charge pump and a control unit. The first power generator is used for providing a first voltage for a first power reception end of the amplifier. The second power generator is used for providing a second voltage. The charge pump is coupled between the second power generator and a second power reception end of the amplifier and is used for generating a third voltage for the amplifier according to the second voltage. The control unit is coupled to the second power generator and is used for controlling the second power generator, so as to adjust the second voltage to make the third voltage equal to a multiple of the first voltage.
    Type: Application
    Filed: December 13, 2006
    Publication date: February 14, 2008
    Inventors: Fu-Yuan Chen, Chung-An Hsieh, Yueh-Ping Yu
  • Publication number: 20080036543
    Abstract: In a circuit having a runaway detector coupled to a phase-locked loop (PLL), the PLL may include a loop filter to receive a control voltage within the PLL and provide a filtered control voltage and a voltage-controlled oscillator to receive the filtered control voltage and provide an output clock signal. The runaway detector may provide a control signal for adjusting the filtered control voltage in response to a predetermined PLL condition. The runaway detector may include a comparator to receive a first and second input voltages, where the second input voltage is based on the output clock signal. When the predetermined PLL condition exists, the runaway detector may be active to adjust the filtered control voltage k thereby enabling the PLL to return to a lock condition.
    Type: Application
    Filed: May 2, 2007
    Publication date: February 14, 2008
    Inventor: Mel Bazes
  • Publication number: 20080036544
    Abstract: A frequency synthesizer is disclosed. The frequency synthesizer includes a phase-locked loop (PLL) provided with an oscillator, a switching unit for switching the PLL to either an open loop status or a closed loop status, and a setting device for adjusting an oscillator frequency of the oscillator according to a reference clock and an oscillator signal generated from the oscillator when the PLL is in the open loop status, wherein a control signal of the oscillator is substantially constant when the PLL is in the open loop status.
    Type: Application
    Filed: July 24, 2007
    Publication date: February 14, 2008
    Inventor: Fucheng Wang
  • Publication number: 20080036545
    Abstract: A frequency-shift modulation device includes an oscillating circuit, a phase-locked loop and a digital frequency modulation circuit. The oscillating circuit is connected to the phase-locked loop in order to produce a fixed-frequency clock signal. This clock signal is used for timing the frequency modulation circuit. A standard model crystal oscillator can be used in the oscillating circuit, given that the RF frequency of a wireless transmission signal which is produced by the modulation device is determined digitally.
    Type: Application
    Filed: August 8, 2007
    Publication date: February 14, 2008
    Applicant: STMicroelectronics S.A.
    Inventor: Pascal Mellot
  • Publication number: 20080036546
    Abstract: Sensor circuits including an oscillator circuit.
    Type: Application
    Filed: August 29, 2007
    Publication date: February 14, 2008
    Inventors: G. Taylor, Steven Beard
  • Publication number: 20080036547
    Abstract: A voltage controlled oscillator 100 comprises an inductor circuit including inductors 101, 102; a variable capacitance circuit 110 which includes variable capacitance elements 111, 112 for changing a capacitance value in accordance with a voltage difference between both of two terminals thereof and capacitive elements 113, 114 for cutting a DC component, and which is connected in parallel to the inductor circuit; a negative resistance circuit including cross-coupled oscillating transistors 103, 104; and a time-switched level shift circuit 108 for shifting a reference voltage to be output to two or more levels in accordance with time. A connection point A of the variable capacitance elements is supplied with a control voltage Vt for controlling an oscillation frequency, and connection points B, C of the variable capacitance elements and the capacitive elements are supplied with a reference voltage Vref output from the time-switched level shift circuit 108 via resistors 115, 116.
    Type: Application
    Filed: August 7, 2007
    Publication date: February 14, 2008
    Inventor: Takayuki Tsukizawa
  • Publication number: 20080036548
    Abstract: An LC resonator for a voltage controlled oscillator comprises an inductive transmission line, input and output ports connected to the transmission line, and a capacitor interconnected in the transmission line, wherein the transmission line is grounded in at least one end portion thereof. The inductive transmission line comprises a plurality of connection ports that are capable of being connected to each other or to ground in order to tune the resonance frequency of the LC resonator from one frequency band to another, and the capacitor is a trimming capacitor in order to tune the resonance frequency of the LC resonator. Preferably, the LC resonator is formed as a microstrip or strip line structure in essentially a C or S shape on a laminate substrate.
    Type: Application
    Filed: May 31, 2007
    Publication date: February 14, 2008
    Inventors: Reza Bagger, Richard Wallace, Tobias Hahn, Dante Palima
  • Publication number: 20080036549
    Abstract: A microwave generator has at least one resonator with two mutually opposite resonator electrodes which are separated by a spark gap. The spark gap breaks down when a high-voltage is applied. The resonator electrodes are designed in the area of the spark gap such that they result in a two-dimensional or three-dimensional section with a substantially constant, minimum electrode separation.
    Type: Application
    Filed: September 26, 2007
    Publication date: February 14, 2008
    Applicant: DIEHL BGT DEFENCE GMBH & CO. KG
    Inventors: Robert Stark, Jurgen Urban
  • Publication number: 20080036550
    Abstract: A voltage-controlled oscillator (VCO) for a multi-band receiver, and a radio-frequency (RF) communication apparatus having the same. The VCO includes at least two fine tune branches, that is, a main fine tune branch and an auxiliary fine tune branch. The main fine tune branch includes at least one variable capacitor whose capacitance varies according to a tuning voltage. The auxiliary fine tune branch includes at least one varactor that operates either as a variable capacitor whose capacitance varies according to the tuning voltage or a fixed capacitor regardless of the tuning voltage, based on an operating frequency band. Accordingly, it is possible to prevent phase noise from increasing by varying the gain of the VCO according to the frequency band of an oscillation signal from the VCO.
    Type: Application
    Filed: April 18, 2007
    Publication date: February 14, 2008
    Inventor: Jin-Hyuck Yu
  • Publication number: 20080036551
    Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal oscillating at a frequency in response to a first control signal and a second control signal. The second circuit may be configured to generate the second control signal in response to (i) an input voltage and (ii) the output signal. The second circuit (i) generates the second control signal by comparing a peak voltage of the output signal to the input voltage and (ii) adjusts an amplitude of the control signal in response to the comparison.
    Type: Application
    Filed: July 30, 2007
    Publication date: February 14, 2008
    Inventor: Heung Kim
  • Publication number: 20080036552
    Abstract: The invention introduces a method for the production of an output signal having a predefined average size from a relatively larger input signal by pulse-width modulated connection of the input signal, wherein the pulse-width modulation has a predefined number of discrete, adjustable pulse widths within a pulse width and each pulse width corresponds to a specific average output-signal size. A super frame consisting of at least two successive pulses is chosen in order to produce an output signal which has an average size and which does not correspond to one of the discretely adjustable pulse widths. At least two pulses inside the super frame have a different pulse width such that the average output signal size corresponds to the predefined size.
    Type: Application
    Filed: July 14, 2005
    Publication date: February 14, 2008
    Inventors: Uli Joos, Josef Schnell
  • Publication number: 20080036553
    Abstract: In a multi-pole, double-throw switch, three multi-terminal device connectors are coupled to a printed circuit board, along with two header connectors and a movable array. A pcb trace electrically couples each terminal of each device connector to one or more corresponding contacts at the header connectors. The movable is movable between a first throw position in which a first header connector is engaged, and a second throw position in which a second header connector is engaged. In the first throw position, each terminal of a first of the three device connectors is electrically connected to a corresponding terminal of a second of the three device connectors. In the second throw position, each terminal of the first of the three device connectors is electrically connected to a corresponding terminal of a third of the three device connectors.
    Type: Application
    Filed: August 14, 2006
    Publication date: February 14, 2008
    Applicant: eAcceleration Corporation
    Inventor: Clinton L. Ballard
  • Publication number: 20080036554
    Abstract: An HF plasma process excitation configuration includes an HF generator that is connected to a plasma load through a directional coupler. The directional coupler includes a transmission line, a first coupling line for detecting reflected power from the plasma load, and a second coupling line for detecting forward power from the HF generator, is the first coupling line is spaced apart from the transmission line and is terminated at least at one end with a termination resistance. The second coupling line is spaced apart from the transmission line and is terminated at least at one end with a termination resistance. Each coupling line has a predetermined and adjusted characteristic impedance, and the termination resistances each have a resistance value that corresponds within a tolerance to the characteristic impedance of the associated coupling line with a tolerance.
    Type: Application
    Filed: March 21, 2007
    Publication date: February 14, 2008
    Applicant: HUETTINGER ELEKTRONIK GMBH + CO. KG
    Inventors: Daniel Krausse, Christoph Gerhardt, Peter Riessle, Thomas Kirchmeier, Erich Pivit
  • Publication number: 20080036555
    Abstract: A multilayer filter has a capacitor element body, at least two signal terminal electrodes, at least one grounding terminal electrode, and at least one connection conductor. The capacitor element body has a plurality of laminated insulator layers, a first signal internal electrode and a grounding internal electrode arranged so as to be opposed to each other with at least one insulator layer out of the plurality of insulator layers in between, and a second signal internal electrode arranged so as to be opposed to either one internal electrode of the first signal internal electrode and the grounding internal electrode with at least one insulator layer out of the plurality of insulator layers in between. The first signal internal electrode is connected to the at least one connection conductor. The second signal internal electrode is connected to the at least two signal terminal electrodes and to the at least one connection conductor.
    Type: Application
    Filed: July 6, 2007
    Publication date: February 14, 2008
    Applicant: TDK CORPORATION
    Inventor: Masaaki Togashi
  • Publication number: 20080036556
    Abstract: A method of installing a filter into an electronic circuit board is provided. The method includes inserting a second section of the filter into an aperture defined in the electronic circuit board, such that a first section of the filter is secure against an electronic circuit board first surface and a first lead of the filter extends to a solder pad on the electronic circuit board first surface. The method also includes coupling a second lead to a second contact of the filter such that the second lead extends to a solder pad on an electronic circuit board second surface. The method also includes reflowing the circuit board such that the first lead is soldered to the electronic circuit board first surface, and the second lead is soldered to the electronic circuit board second surface.
    Type: Application
    Filed: August 10, 2006
    Publication date: February 14, 2008
    Inventor: James B. Harrington
  • Publication number: 20080036557
    Abstract: A bandpass filter includes a plurality of resonators. An input pin is connected to a first resonator of the plurality of resonators. An output pin is connected to a second resonator of the plurality of resonators. The first and second resonators are magnetically coupled to each other. The first and second resonators are coupled to other resonators using mixed coupling. The other resonators are coupled to each other using electric coupling.
    Type: Application
    Filed: August 20, 2007
    Publication date: February 14, 2008
    Applicant: Broadcom Corporation
    Inventors: Sung-Hsien Chang, Ramon Gomez, Lawrence Burns, Carl Pobanz