Patents Issued in February 26, 2008
-
Patent number: 7335968Abstract: A transmission line circuit provides a structure for improved transmission line operation on integrated circuits. The transmission line circuit includes a first layer of electrically conductive material on a substrate. A first layer of insulating material is formed on the first layer of the electrically conductive material. A number of high permeability metal lines are formed on the first layer of insulating material. The number of high permeability metal lines includes composite hexaferrite films. A number of transmission lines is formed on the first layer of insulating material and between and parallel with the number of high permeability metal lines. A second layer of insulating material is formed on the transmission lines and the high permeability metal lines. The transmission line circuit includes forming a second layer of electrically conductive material on the second layer of insulating material.Type: GrantFiled: August 9, 2004Date of Patent: February 26, 2008Assignee: Micron Technology, Inc.Inventors: Leonard Forbes, Kie Y. Ahn, Salman Akram
-
Patent number: 7335969Abstract: A method for monitoring a nitridation process, including: (a) providing a semiconductor substrate; (b) forming a first dielectric layer on a top surface of the substrate; (c) introducing a quantity of interfacial species into the substrate; (d) removing the first dielectric layer; (e) forming a second dielectric layer on the top surface of the substrate; (f) measuring the density of interface traps between the substrate and the second dielectric layer; (g) providing a predetermined relationship between the quantity of the interfacial species and the density of the interface traps; and (h) determining the quantity of the interfacial species introduced based on the relationship.Type: GrantFiled: March 9, 2005Date of Patent: February 26, 2008Assignee: International Business Machines CorporationInventors: Lance Genicola, Mark J. Hurley, Jeremy J. Kempisty, Paul D. Kirsch, Ravikumar Ramachandran, Suri Hedge
-
Patent number: 7335970Abstract: Disclosed are a semiconductor device, a method for manufacturing the same, and a method for mounting the same.Type: GrantFiled: January 23, 2004Date of Patent: February 26, 2008Assignee: Oki Electric Industry Co., Ltd.Inventors: Yoshikazu Takahashi, Masami Suzuki, Masaru Kimura
-
Patent number: 7335971Abstract: A method of protecting a micro-mechanical sensor structure embedded in a micro-mechanical sensor chip, in which the micro-mechanical sensor structure is fabricated with a protective membrane, the micro-mechanical sensor chip is arranged so that a surface of the protective membrane faces toward a second chip, and the micro-mechanical sensor chip is secured to the second chip.Type: GrantFiled: March 31, 2003Date of Patent: February 26, 2008Assignee: Robert Bosch GmbHInventor: Karsten Funk
-
Patent number: 7335972Abstract: A microsystem-on-a-chip comprises a bottom wafer of normal thickness and a series of thinned wafers can be stacked on the bottom wafer, glued and electrically interconnected. The interconnection layer comprises a compliant dielectric material, an interconnect structure, and can include embedded passives. The stacked wafer technology provides a heterogeneously integrated, ultra-miniaturized, higher performing, robust and cost-effective microsystem package. The highly integrated microsystem package, comprising electronics, sensors, optics, and MEMS, can be miniaturized both in volume and footprint to the size of a bottle-cap or less.Type: GrantFiled: November 13, 2003Date of Patent: February 26, 2008Assignee: Sandia CorporationInventor: Rajen Chanchani
-
Patent number: 7335973Abstract: A package includes a flexible substrate with a first region and a second region, an encapsulated die supported by the first region, and a conformable fold adhesive introduced between the encapsulated die and the flexible substrate. The second region of the flexible substrate is folded over the surface of the encapsulated die.Type: GrantFiled: February 21, 2006Date of Patent: February 26, 2008Assignee: Intel CorporationInventors: Rahul N. Manepalli, Karen Y. Paghasian, Shinobu Kourakata, Ruel D R Aranda
-
Patent number: 7335974Abstract: A multi stack packaging chip and a method of manufacturing the chip are provided. The method includes forming at least one second circuit element on a first wafer; forming a second wafer having a cavity and a one third circuit element formed opposite to the cavity; forming a solder on the second wafer; and combining the second wafer with the first wafer so that the second circuit element and the cavity correspond. The chip includes a flip-chip packaged chip in which a first circuit element is packaged using a first wafer; a second circuit element formed on the first wafer; a second wafer having a cavity and combined with the first wafer so that the cavity and the second circuit element correspond; a third circuit element formed on the second wafer; and a solder formed on the second wafer, the solder electrically coupling the second wafer to a packaging substrate.Type: GrantFiled: March 29, 2006Date of Patent: February 26, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-sik Hwang, Woon-bae Kim, Chang-youl Moon, Moon-chul Lee, Kyu-dong Jung
-
Patent number: 7335975Abstract: The present invention stacks packaged integrated circuits into modules that conserve PWB or other board surface area. The invention provides techniques and structures for aggregating chip scale-packaged integrated circuits (CSPs) or leaded packages with other CSPs or with monolithic or stacked leaded packages into modules that conserve PWB or other board surface area. The present invention can be used to advantage with packages of a variety of sizes and configurations ranging from larger packaged base elements having many dozens of contacts to smaller packages such as, for example, die-sized packages such as DSBGA. In a preferred embodiment devised in accordance with the present invention, a base element CSP and a support element CSP are aggregated through a flex circuit having at least two conductive layers that are patterned to selectively connect the two CSP elements.Type: GrantFiled: October 5, 2004Date of Patent: February 26, 2008Assignee: Staktek Group L.P.Inventors: James W. Cady, James Wilder, David L. Roper, Russell Rapport, James Douglas Wehrly, Jr., Jeffrey Alan Buchle
-
Patent number: 7335976Abstract: An electrical device includes a plurality of interconnects passing through a plane. The interconnects have a longitudinal axis substantially perpendicular to the plane and including an arrangement pattern which reduces or eliminates cross-talk between nearest neighboring interconnects, wherein the interconnects include a first differentially driven signal conductor pair and at least one other signal conductor, and the arrangement includes the at least one other signal conductor disposed at a substantially same distance from each conductor of the first differentially driven signal conductor pair.Type: GrantFiled: May 25, 2005Date of Patent: February 26, 2008Assignee: International Business Machines CorporationInventors: Zhaoqing Chen, Christian Schuster
-
Patent number: 7335977Abstract: Disclosed is a device which comprises a substrate, a plurality of signal output terminal electrodes provided on the substrate, a plurality of signal input terminal electrodes provided on the substrate, and a display driver IC having input terminals thereof connected to the signal input terminal electrodes and output terminals thereof connected to the signal output terminal electrodes. A plurality of output terminals (first, third, fifth, . . . (i+1)th, and (n?1)th) are included on a first side of the display driver IC facing the signal input terminal electrodes. A second side on an opposite side of the first side faces the signal input terminal electrodes. Input terminals 22 are included in at least one segment of the second side, and output terminals (second, fourth, sixth, ith, jth, (j+2)th, (n?2)th, and nth) are included in at least one portion of the remaining segment of the second side.Type: GrantFiled: July 7, 2005Date of Patent: February 26, 2008Assignee: NEC Electronics CorporationInventor: Masaharu Tsukiji
-
Patent number: 7335978Abstract: A semiconductor component includes a stiffener, a circuit decal attached to the stiffener, and a semiconductor die attached to the stiffener. The circuit decal includes conductors which function as an internal signal transmission system for the component, and a mask layer which functions as a solder mask and an outer insulating layer for the component. An adhesive layer in physical contact with the conductors attaches the circuit decal to the stiffener, and electrically insulates the conductors from the stiffener. The component also includes an area array of terminal contacts on the conductors electrically isolated by the mask layer. A method for fabricating the component includes the steps of attaching the circuit decal to the stiffener, attaching the die to the stiffener, interconnecting the die and the circuit decal, encapsulating the die, and forming the terminal contacts.Type: GrantFiled: May 15, 2006Date of Patent: February 26, 2008Assignee: Micron Technology, Inc.Inventor: Stephen F. Moxham
-
Patent number: 7335979Abstract: An article of manufacture and system, as well as fabrication methods therefore, may include a plurality of lands disposed on a surface of a substrate wherein the lands are oriented at an angle to the surface of the substrate and further wherein the substrate is formed of conductive layers that are formed such that a non-conductive layer does not interpose between the conductive layers and their coupling.Type: GrantFiled: June 28, 2004Date of Patent: February 26, 2008Assignee: Intel CorporationInventor: Michael J. Walk
-
Patent number: 7335980Abstract: The present invention provides a hardmask that is located on a surface of a low k dielectric material having at least one conductive feature embedded therein. The hardmask includes a lower region of a hermetic oxide material located adjacent to the low k dielectric material and an upper region comprising atoms of Si, C and H located above the hermetic oxide material. The present invention also provides a method of fabricating the inventive hardmask as well as a method to form an interconnect structure containing the same.Type: GrantFiled: November 4, 2004Date of Patent: February 26, 2008Assignee: International Business Machines CorporationInventors: Son Van Nguyen, Michael Lane, Stephen M. Gates, Xiao H. Liu, Vincent J. McGahay, Sanjay C. Mehta, Thomas M. Shaw
-
Patent number: 7335981Abstract: Methods are provided for creating lined vias in semiconductor substrates. Using electrophoretic deposition techniques, micelles of a lining material are deposited on the wall of the via, reacting with the surface of the wall until the entire wall is covered by the lining material. The lining material is then fixed in place to form a layer lining the via. The lined via may then be filled with a desired material. For example, a via lined with an insulative material may be filled with a material such as copper to create an insulated conductive via through the substrate.Type: GrantFiled: September 6, 2006Date of Patent: February 26, 2008Assignee: Micron Technology, Inc.Inventors: Warren M. Farnworth, Dale W. Collins, Steven M. McDonald
-
Patent number: 7335982Abstract: A chip packaging process is provided. First, a cavity is formed on a heat sink. A first encapsulant is formed on the bottom of the cavity. A circuit substrate is disposed over the heat sink. The circuit substrate has an opening that corresponds in position to the cavity. Thereafter, a chip is disposed on the first encapsulant and the chip is electrically connected to the circuit substrate. Finally, a compound is deposited over the first encapsulant and the chip to form a chip package. The chip package is warp resistant and the chip packaging process increases overall production yield.Type: GrantFiled: March 30, 2005Date of Patent: February 26, 2008Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Chin-Li Kao, Yi-Shao Lai, Jeng-Da Wu, Tong-Hong Wang
-
Patent number: 7335983Abstract: A method, apparatus and system with a semiconductor package including a microchimney or thermosiphon using carbon nanotubes to modify the effective thermal conductivity of an integrated circuit die.Type: GrantFiled: December 16, 2005Date of Patent: February 26, 2008Assignee: Intel CorporationInventors: James G. Maveety, Gregory M. Chrysler, Unnikrishnan Vadakkanmaruveedu
-
Patent number: 7335984Abstract: Microfluidics chips and methods of use are described, comprising a pair of wafers, at least one having a patterned surface, and two polymeric barrier films between the wafers conforming to the patterned surface. The polymeric barrier films allow the wafers of the inventive microfluidics chips to be reused without cleaning.Type: GrantFiled: July 31, 2003Date of Patent: February 26, 2008Assignees: Agency For Science, Technology and Research, National University of SingaporeInventors: Victor Samper, Lin Cong, Hongmiao Ji
-
Patent number: 7335985Abstract: A chip and a chip package can transmit information to each other by using a set of converters capable of communicating with each other through the emission and reception of electromagnetic signals. Both the chip and the chip package have at least one such converter physically disposed on them. Each converter is able to (1) convert received electromagnetic signals into electronic signals, which it then may relay to leads on the device on which it is disposed; and (2) receive electronic signals from leads on the device on which it is disposed and convert them into corresponding electromagnetic signals, which it may transmit to a corresponding converter on the other device. Not having a direct physical connection between the chip and the chip package decreases the inductive and capacitive effects commonly experienced with physical bonds.Type: GrantFiled: August 29, 2003Date of Patent: February 26, 2008Assignee: Micron Technology, Inc.Inventors: Tim Murphy, Lee Gotcher
-
Patent number: 7335986Abstract: Disclosed is a wafer level chip scale package and a method for manufacturing the same. The wafer level chip scale package includes a semiconductor die having a first coating layer formed thereon; a redistribution layer formed on the first coating layer and connected to the bond pad; an electronic device placed on the first coating layer; a connection member for electrically connecting the electronic device and the redistribution layer; a conductive post formed on the redistribution layer with a predetermined thickness; a second coating layer for enclosing the first coating layer, the redistribution layer, the electronic device, the connection member, and the conductive post; and a solder ball thermally bonded to the conductive post while protruding to the exterior of the second coating layer. This construction makes it easy to manufacture stacked packages and chip scale packages in a wafer level.Type: GrantFiled: September 14, 2005Date of Patent: February 26, 2008Assignee: Amkor Technology, Inc.Inventors: Jong Sik Paek, Sung Su Park, Ho Cheol Jang, Jung Gi Jin
-
Patent number: 7335987Abstract: A semiconductor package includes a semiconductor chip, a first substrate layer and a second substrate layer. The semiconductor chip has an active surface and a plurality of pads disposed on the active surface. The first substrate layer is formed on the active surface of the semiconductor chip and has a plurality of first contacts electrically connected to the pads of the semiconductor chip. The second substrate layer is substantially smaller than the first substrate layer, is formed on the first substrate layer, and has a plurality of second contacts electrically connected to the first contacts of the first substrate layer.Type: GrantFiled: February 4, 2005Date of Patent: February 26, 2008Assignee: Advanced Semiconductor Engineering Inc.Inventor: Yao Ting Huang
-
Patent number: 7335988Abstract: An apparatus and a method for forming a substrate having a palladium metal layer over at least one contact point of the substrate and having a flexible conductive polymer bump, preferably a two-stage epoxy, on the palladium plated contact point, are provided. The present invention also relates to assemblies comprising one or more of these substrates.Type: GrantFiled: June 6, 2005Date of Patent: February 26, 2008Assignee: Micron Technology, Inc.Inventors: Warren M. Farnworth, Salman Akram
-
Patent number: 7335989Abstract: A semiconductor device provided with: a first interconnection layer provided on a semiconductor substrate; an interlevel insulation film provided over the first interconnection layer; a barrier layer provided between the first interconnection layer and the interlevel insulation film; and a second interconnection layer of gold provided as an uppermost interconnection layer on the interlevel insulation film. The barrier layer is formed in a region of the first interconnection layer including an interlevel connection opening region of the interlevel insulation, and the region is greater than the interlevel connection opening region. The second interconnection layer is electrically connected to the first interconnection layer via the barrier layer in the interlevel connection opening.Type: GrantFiled: August 17, 2004Date of Patent: February 26, 2008Assignee: Rohm Co., Ltd.Inventors: Goro Nakatani, Hitoshi Tamura
-
Patent number: 7335990Abstract: A semiconductor device, having a composite barrier layer, comprising the following. A substrate has a dielectric layer formed thereover and having an opening within the dielectric layer. The opening exposes a first portion of the substrate. A composite barrier layer lines the opening. The composite barrier layer comprises: a dielectric flash layer within the opening and lining the opening wherein the dielectric flash layer does not cover the first exposed portion of the substrate; an aluminum layer over the dielectric flash layer and over the first exposed portion of the substrate; and a barrier metal layer over the aluminum layer. Wherein the dielectric flash layer, the aluminum layer and the barrier metal layer comprise the composite barrier layer. A planarized metal plug is within the barrier metal layer lined opening.Type: GrantFiled: July 3, 2007Date of Patent: February 26, 2008Assignee: Agency for Science, Technology and ResearchInventors: Chaoyong Li, Siaw Suian Sabrina Su, Moitreyee Mukherjee-Roy, Ramana Murthy Badam
-
Patent number: 7335991Abstract: There is provided a barrier structure provided with a concave portion corresponding to a pattern formed out of a functional liquid, the barrier structure comprising: a first concave portion provided in the barrier to correspond to a first pattern; and a second concave portion that is connected to the first pattern and is provided in the barrier to correspond to a second pattern having a width smaller than that of the first pattern, wherein the height of at least a part of the bottom surface of the second concave portion is greater than that of the bottom surface of the first concave portion.Type: GrantFiled: August 30, 2005Date of Patent: February 26, 2008Assignee: Seiko Epson CorporationInventors: Toshimitsu Hirai, Katsuyuki Moriya
-
Patent number: 7335992Abstract: The semiconductor apparatus includes a pad; a first line layer placed immediately beneath the pad; and a lattice-shaped contact being between the pad and the first line layer.Type: GrantFiled: March 28, 2005Date of Patent: February 26, 2008Assignee: NEC Electronics CorporationInventor: Kunio Anzai
-
Patent number: 7335993Abstract: A multi chip package includes a first semiconductor chip, a second semiconductor chip and a spacer. The spacer is formed between the first semiconductor chip and the second semiconductor chip. The second semiconductor chip is fixed on the first semiconductor chip by an adhesive material that is formed on the first semiconductor chip. Since the spacer is formed between the first semiconductor chip and the second semiconductor chip, the space between the first semiconductor chip and the second semiconductor chip is even.Type: GrantFiled: August 13, 2003Date of Patent: February 26, 2008Assignee: Oki Electric Industry Co., Ltd.Inventor: Yasuhito Anzai
-
Patent number: 7335994Abstract: A semiconductor package component includes a base die and a secondary die flip chip mounted to the base die. The base die includes a set of stacking contacts for flip chip mounting the secondary die to the base die, and a set of interconnect contacts configured as an internal signal transmission system, and a physical structure for supporting a terminal contact system of the package component. The package component also includes an encapsulant on the base die encapsulating the interconnect contacts, an underfill layer between the dice, and terminal contacts configured for flip chip mounting the package component to a supporting substrate. A method for fabricating the package component includes the steps of providing a base wafer containing a plurality of base dice, and flip chip mounting the secondary dice to the base dice on the base wafer.Type: GrantFiled: June 27, 2005Date of Patent: February 26, 2008Assignee: Micron Technology, Inc.Inventors: Dean A. Klein, Alan G. Wood, Trung Tri Doan
-
Patent number: 7335995Abstract: A microelectronic assembly and a fabrication method are provided which includes a microelectronic element such as a chip or element of a package. A plurality of surface-mountable contacts are arranged in an array exposed at a major surface of the microelectronic element. One or more passive elements, e.g., a resistor, inductor, capacitor, or combination of the same are mounted to the microelectronic element, with an inner terminal of the passive element conductively mounted to an exposed surface of one contact and an outer terminal displaced vertically from the major surface of the microelectronic element.Type: GrantFiled: February 22, 2005Date of Patent: February 26, 2008Assignee: Tessera, Inc.Inventors: L. Elliott Pflughaupt, David Gibson, Young-Gon Kim, Craig S. Mitchell, Wael Zohni, Ilyas Mohammed
-
Patent number: 7335996Abstract: A method of bonding includes using a bonding layer having a fluorinated oxide. Fluorine may be introduced into the bonding layer by exposure to a fluorine-containing solution, vapor or gas or by implantation. The bonding layer may also be formed using a method where fluorine is introduced into the layer during its formation. The surface of the bonding layer is terminated with a desired species, preferably an NH2 species. This may be accomplished by exposing the bonding layer to an NH4OH solution. High bonding strength is obtained at room temperature. The method may also include bonding two bonding layers together and creating a fluorine distribution having a peak in the vicinity of the interface between the bonding layers. One of the bonding layers may include two oxide layers formed on each other. The fluorine concentration may also have a second peak at the interface between the two oxide layers.Type: GrantFiled: May 30, 2006Date of Patent: February 26, 2008Assignee: Ziptronix, Inc.Inventor: Qin-Yi Tong
-
Patent number: 7335997Abstract: A control system for use with an ultrasonic surgical instrument includes a generator supplying electrical energy to an ultrasonic surgical instrument, the electrical energy supplied by the generator being controlled such that power applied by the instrument is maintained constant once a predetermined pressure threshold is met. The control system operates by assigning a nominal power at which the ultrasonic instrument is to operate and adjusting the current and voltage applied to the ultrasonic surgical instrument so as to maintain the power applied by the ultrasonic surgical instrument at approximately the nominal power.Type: GrantFiled: March 31, 2005Date of Patent: February 26, 2008Assignee: Ethicon Endo-Surgery, Inc.Inventor: Eitan T. Wiener
-
Patent number: 7335998Abstract: A device for supplying voltage to the loads of an onboard electrical system of a motor vehicle includes a first generator, a regulator allocated to the first generator, a second generator, a regulator allocated to the second generator, and a control apparatus. The control apparatus is connected to at least one, and possibly to both, of the regulators, and the control apparatus supplies these regulators with control signals on the basis of which the loading of the generators is compensated.Type: GrantFiled: February 17, 2006Date of Patent: February 26, 2008Assignee: Robert Bosch GmbHInventor: Gert Wolf
-
Patent number: 7335999Abstract: A fluid-powered actuator assembly is modified to include a low power generator. The low power generator rotates in response to a drive force received from the actuator assembly, and thus only generates electrical power when the actuator assembly is operating. The low power generator is used to supply electrical power to various sensors and circuits, which may be used to implement prognostic and health monitoring capabilities for the actuator assembly.Type: GrantFiled: June 15, 2004Date of Patent: February 26, 2008Assignee: Honeywell International, Inc.Inventors: Calvin C. Potter, David M. Eschborn
-
Patent number: 7336000Abstract: A speed monitor for establishing a lower threshold and an upper threshold for a speed of a rotor or shaft of a turbogenerator. A speed detector detects speed data or a speed signal for a rotor or shaft associated with a turbogenerator. A turbogenerator controller controls an output current of the turbogenerator based on the detected speed data or speed signal to control a rotational speed of the rotor or the shaft. A voltage monitor establishes a lower voltage limit and an upper voltage limit for a generator. A voltage detector detects an output voltage level associated with the generator. A motor/generator controller controls the output voltage level of the generator electrical output by invoking at least one of a motor mode and a generator mode based on the detected output voltage level to maintain a desired operational voltage range.Type: GrantFiled: April 20, 2006Date of Patent: February 26, 2008Assignee: Deere & CompanyInventors: Ronnie Dean Stahlhut, Carl Thomas Vuk
-
Patent number: 7336001Abstract: A door lock control device prevents deterioration in anti-theft property of a vehicle by restricting unjust cancellation of a locked state of a door of the vehicle. In-vehicle operation detecting means detects a predetermined operation performed in a compartment of the vehicle. Locked state canceling means cancels the locked state of the door when the predetermined operation is detected by the in-vehicle operation detecting means. Unjust act detecting means detects an unjust act applied to the vehicle. Locked state cancellation prohibiting means prohibits cancellation of the locked state by the locked state canceling means after the unjust act is detected by the unjust act detecting means.Type: GrantFiled: April 28, 2005Date of Patent: February 26, 2008Assignee: Toyota Jidosha Kabushiki KaishaInventors: Takao Ozawa, Kouichi Masamura, Yoshihide Nakane
-
Patent number: 7336002Abstract: A main power source is, for example, an ordinary Pb battery. At the time of starting an engine, the main power source supplies power to a starter. The main power source is given a higher priority than an auxiliary power source to supply power to ordinary loads. The auxiliary power source is a high performance battery (e.g., Li ion battery), which has superior charge acceptance capability and better state detectability over the main power source. The auxiliary power source stores regenerative power, which is generated by a generator at the time of deceleration of a vehicle, and is used as a redundant power source for the main power source. The main power source and the auxiliary power source are connected to each other through a supply circuit, which has a DC/DC converter, and a second supply circuit, which has a switch.Type: GrantFiled: February 17, 2004Date of Patent: February 26, 2008Assignee: Denso CorporationInventors: Akira Kato, Katsunori Tanaka, Masaru Kamiya, Takashi Senda
-
Patent number: 7336003Abstract: A transfer switch includes first terminals adapted to input power from a first power source, second terminals adapted to input power from a second power source, third terminals adapted to output power to a first load, and a transfer mechanism adapted to selectively electrically connect the one of the first or second terminals to the third terminals. A control mechanism cooperates with the first and second terminals and the transfer mechanism to electrically connect one of the first and third terminals or the second and third terminals. A control circuit and a relay include normally closed contacts and normally open contacts. The relay is de-energized responsive to the first and third terminals being electrically connected, and energized responsive to the second and third terminals being electrically connected. The normally closed contacts shed corresponding second loads and the normally open contacts enable corresponding third loads when the relay is energized.Type: GrantFiled: April 5, 2005Date of Patent: February 26, 2008Assignee: Eaton CorporationInventors: Todd M. Lathrop, Derrick G. Berad
-
Patent number: 7336004Abstract: A boost converter and a buck-boost converter supply power to a load from a series connection between a first and a second power source.Type: GrantFiled: October 16, 2006Date of Patent: February 26, 2008Assignee: Siemens VDO Automotive CorporationInventor: Jih-Sheng Lai
-
Patent number: 7336005Abstract: A switching circuit operative to switch between a first and second power source to an output is disclosed. The circuit comprises a MOSFET switch electrically connected to the first and second power sources and operative to provide power from either one of the power sources to the output. The circuit includes a RC network electrically connected to a gate of the MOSFET switch. The RC network is operative to delay switching between the first and second power sources such that the second power source has the opportunity to fully ramp-up in order to provide continuous power to the output. Accordingly, the second power source can fully provide power to the output when the power is switched from the first power source to the second power source.Type: GrantFiled: October 24, 2006Date of Patent: February 26, 2008Assignee: Sierra Wireless, Inc.Inventors: Samir Hadzimusic, Simon Au
-
Patent number: 7336006Abstract: A magnetic actuator, comprising a magnet, mutually opposite magnetic poles thereof being arranged opposing each other, and a coil, at least one portion thereof being inserted between the corresponding magnetic poles, wherein a driving force for the coil is generated by applying an electric current to the coil in a magnetic field generated by the magnet.Type: GrantFiled: March 12, 2003Date of Patent: February 26, 2008Assignee: Fuji Xerox Co., Ltd.Inventors: Yoichi Watanabe, Kazuyuki Tsukamoto
-
Patent number: 7336007Abstract: A system and method are disclosed for controlling an integrated rotary-linear actuator system that may be coupled to a network via a network interface. The integrated rotary-linear actuator system includes a control system and a rotary-linear actuator having a moveable plunger and associated coils. The coils may be energized to interact with associated magnets to effect corresponding movement of the plunger, which may include rotation and/or linear movement. The network interface facilitates receipt of control information at the control system of the integrated rotary-linear actuator system from the network. The control system may control an amplifier to energize the coils based on the control information.Type: GrantFiled: April 9, 2007Date of Patent: February 26, 2008Assignee: Anorad CorporationInventors: Anwar Chitayat, Mustansir Faizullabhoy
-
Patent number: 7336008Abstract: The invention concerns with connection of a lead from an electrical component of an alternator for a vehicle, and provides a terminal shape suitable for TIG welding (arc welding using a gas shielded non-consumable electrode) without being affected by dimensional accuracy of terminals to be connected to each other. Cross-shaped projections having a larger volume than a welded region of the terminal is provided near the welded region, and weld penetration (welding depth) is controlled based on a difference in heat capacity resulting from the volume difference, or melting is suppressed with promotion of heat radiation. Thus, the welding depth is stabilized without being affected by dimensional accuracy of the terminals including relative positions between them, and an alternator for a vehicle can be provided in which a lead from an electrical component has high connection reliability.Type: GrantFiled: April 18, 2003Date of Patent: February 26, 2008Assignee: Hitachi, Ltd.Inventors: Wasei Horioka, Shin Onose, Shinji Yamazaki, Mitsuaki Izumi, Masami Takano
-
Patent number: 7336009Abstract: An independent and modular apparatus is disclosed for extending the operational capacity of a servo motor. The apparatus includes a frame member having a servo motor and a rotatable shaft mounted therein. The output shaft of the servo motor and the rotatable shaft are displace from one another. Means are incorporated for translating rotation motion from the output shaft to the rotatable shaft so as to enable a torque or rotational capacity for the rotatable shaft that is greater than that of the servo output shaft.Type: GrantFiled: June 18, 2004Date of Patent: February 26, 2008Assignee: BTR Robotics Limited Liability CompanyInventor: Brian Pettey
-
Patent number: 7336010Abstract: A power generating system includes a torque converter system receiving a rotational motion having a first torque from a source and producing a rotational output having a second torque different from the first torque, a transfer system having a first portion coupled to the rotational output of the torque converter system and a second portion magnetically coupled to the first portion, and a generator system coupled to the transfer system to produce and electrical output.Type: GrantFiled: July 13, 2006Date of Patent: February 26, 2008Assignee: Magnetic Torque International, Ltd.Inventor: Richard J. Wise
-
Patent number: 7336011Abstract: A power generating system includes a torque converter system receiving a rotational motion having a first torque from a source and producing a rotational output having a second torque different from the first torque, a transfer system having a first portion coupled to the rotational output of the torque converter system and a second portion magnetically coupled to the first portion, and a generator system coupled to the transfer system to produce and electrical output.Type: GrantFiled: July 13, 2006Date of Patent: February 26, 2008Assignee: Magnetic Torque International Ltd.Inventor: Richard J. Wise
-
Patent number: 7336012Abstract: An apparatus that reduces vibration generation and magnetic leakage, wherein the apparatus is a motor, an articulated serial robot that has a motor built in, a substrate loader that includes the articulated robot, and a related exposure apparatus equipped with the substrate loader. The motor includes a drive shaft to drive the motor; a rotor attached with the shaft; and a stator that opposes the rotor and causes an electromagnetic force to act between the rotor and the stator to drive the drive shaft; an RC stator, for reaction force cancellation attached with the stator; an RC rotor for reaction force cancellation, opposing the RC stator; and a counterweight sleeve attached with the RC rotor, wherein the reaction force, which is applied to the stator via the drive shaft when the counterweight sleeve rotates in a direction opposite that of the drive shaft, is cancelled.Type: GrantFiled: January 7, 2005Date of Patent: February 26, 2008Assignee: Nikon CorporationInventor: Keiichi Tanaka
-
Patent number: 7336013Abstract: In accordance with one embodiment, the present technique provides a bushing that is configured to electrically and mechanically couple a conductor bar of a rotor assembly to an end ring of the rotor assembly. The exemplary bushing has an interior surface that is configured to abut against the conductor bar and an exterior surface that is configured to abut the perimetric surface of an end slot. Advantageously, the bushing, because of a good fit in the end slot and around the conductor bar, provides a good electrical connection between the conductor bar and the end ring. Moreover, the exemplary bushing also provides interferences fits that at least partially secure the end ring to the rotor core.Type: GrantFiled: September 30, 2004Date of Patent: February 26, 2008Assignee: Reliance Electric Technologies, LLCInventor: William P. Pizzichil
-
Patent number: 7336014Abstract: The present invention provides an outer rotor type motor for a drum type washing machine to reduce material and weight for fabrication, simplify fabrication process, provide stable assembly of a stator to a fixing side, such as a tub or a bearing housing, prevent unwinding of stacked steel plates in assembling a helical core, and reduce stress on the steel plates of the core.Type: GrantFiled: January 28, 2005Date of Patent: February 26, 2008Assignee: LG Electronics Inc.Inventor: Woon Yong Lee
-
Patent number: 7336015Abstract: A method of manipulating preferable thin wafers, preferably having a thickness of less than 200 ?m, wherein the wafers are placed prior to polishing or another processing step for reducing the thickness thereof on a transportable electrostatic carrier. The wafers remain on the transportable electrostatic carrier for the duration of and between at least two processing steps, during the manipulating steps and during any necessary intermediate storage.Type: GrantFiled: December 21, 2001Date of Patent: February 26, 2008Assignee: VanTec Gesellschaft für Venturekapital und UnternehmensberatungInventors: Joachim Arlt, Karl-Hermann Busse
-
Patent number: 7336016Abstract: A new surface acoustic wave device in which higher frequency can be achieved and that shows enhanced temperature characteristics, is provided in a surface acoustic wave device utilizing an SH type high speed surface wave, when an IDT electrode is formed on a quartz substrate whose Euler angle is represented as (0°, ? [? is from 125 to 142]°, 90°), temperature coefficient of frequency of the quartz substrate at given temperature is made be minus by controlling the film thickness of the IDT electrode, and thereafter the IDT electrode is covered by a thin film having temperature coefficient of frequency that is plus at the given temperature. According to this, since the temperature coefficient of frequency TCF of the whole device becomes zero and second order temperature coefficient ? is enhanced, a surface acoustic wave device in which higher frequency is easily achieved and that has enhanced temperature characteristics can be provided.Type: GrantFiled: August 5, 2004Date of Patent: February 26, 2008Assignee: Seiko Epson CorporationInventor: Masahiro Oshio
-
Patent number: 7336017Abstract: A surface acoustic wave package comprises a first bare chip having a plurality of electrodes formed thereon, a second bare chip having a plurality of electrodes and via-holes formed thereon, a connecting portion electrically connecting the first bare chip to an upper surface of the second bare chip such that the electrodes of the first bare chip face the electrodes of the second bare chip, and a sealing member provided on the first and second bare chips to form an air-tight space on an operating surface between the first and second bare chips.Type: GrantFiled: September 2, 2005Date of Patent: February 26, 2008Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Seung Hee Lee, Doo Cheol Park, Joo Hun Park, Young Jin Lee, Sang Wook Park, Nam Hyeong Kim