Abstract: The invention relates to a field device and a method for calibrating a field device, having a field device electronics and a sensor unit for process measurements, wherein the field device electronics receives measurement signals of the sensor unit, wherein the field device electronics includes an evaluation unit for evaluating the measurement signals and means for calibrating the field device. According to the invention, the means for calibrating the field device includes a digital adjusting element and a microprocessor, wherein the digital adjusting element is driven by the microprocessor for calibrating the field device.

Abstract: The invention pertains to an eddy current sensor with a sensor circuit having a head portion, including a sensor coil, a base portion and a transmission cable connecting the head portion to the base portion. The transmission cable is a triaxial cable and the sensor coil is connected between the inner conductor and the outer shield of this cable. The base portion of the sensor circuit comprises a voltage follower connected to buffer the voltage of the center conductor and apply it to the inner shield of the triaxial cable in order to isolate the cable's line capacitance from the sensor coil. The invention further concerns a sensor coil for an eddy current sensor, having a segmented winding structure with a particularly low self-capacitance. In a preferred embodiment, the triaxial transmission cable is combined with a sensor coil having this segmented winding structure.

Abstract: The application provides a magnetic sensor which can suppress an irregularity of a central potential due to a change in a temperature, decrease size of the sensor, and lower the manufacturing cost of the sensor. A magneto-resistive element and fixed resister are provided on an element base and have the same configuration elements. A second magnetic layer and non-magnetic layer in the fixed resistor are reversely laminated on each other in a manner different from the magneto-resistive element, and the second magnetic layer is formed in contact with the first magnetic layer, thereby fixing the magnetization directions of the first magnetic layer and the second magnetic layer in the same direction. In this manner, the irregularity of the temperature coefficient between the magneto-resistive element and the fixed resistor is suppressed, and the irregularity of the central potential due to the change in the temperature is suppressed.

Abstract: NMR data are acquired using a phase-alternation of the tipping pulse. Averaged properties are estimated over a window length. The averaged properties are inverted to undo the effects of the averaging. A matrix defined in terms of Walsh functions is used in the inversion.

Abstract: In a method for representation of flow in a magnetic resonance image, a first magnetic resonance image of an examination subject is acquired, wherein the flow occurring in the examination subject is not compensated in a first spatial direction; a second magnetic resonance image is acquired, wherein the flow occurring in the first spatial direction is compensated, the phase of the magnetization in each of the first and the second magnetic resonance images is calculated of the phase difference between the first phase image and the second phase image, which is calculated is a measure for the flow along the first spatial direction. A third magnetic resonance image is acquired, wherein the flow in a second spatial direction perpendicular to the first spatial direction is not compensated, and a fourth magnetic resonance image is acquired, wherein the flow occurring in the second spatial direction is compensated.

Abstract: The present invention is directed to a method of MR imaging whereby a k-space blade extending through a center of k-space from a subject in motion is acquired. A high-pass convolution of the k-space blade with a reference k-space blade is then determined and converted to a ? function. In-plane motion of the subject during data acquisition of the k-space is then determined from the ? function.

Abstract: An MRI RF transmit system uses a plurality of RF transmit coils, each being driven with separately controllable RF magnitude and phase. The magnitude and phase of each coil drive are separately and independently controlled so that the RF transmit coils act as if they are decoupled from each other. The controlled magnitude and phase values may be based on empirically derived information relating to self and mutual coupling of RF transmit coils.

Abstract: A mounting device for a local gradient coil unit for mounting same in the examination area of a magnetic resonance unit has one or more guide rails, which are able to be arranged in the examination area, supporting the gradient coil unit, with a locator structure for positioning the gradient coil unit axially on both sides in a mounting position in the examination area, along which guide rail(s) the gradient coil unit slides until it reaches the axial mounting position. One or more fixing elements are fitted on the gradient coil unit for bracing the gradient coil unit in the examination area against the guide rail(s) in the mounting position.

Abstract: A magnetic resonance imaging system performing various types of imaging that involves movement of a patient's couch. The system has a patient's couch having a tabletop movable in a predetermined direction passing through a static magnetic field as well as reception multiple RF coils consisting of for example a plurality of coil groups. The tabletop is automatically moved in its longitudinal direction in accordance with a length of each coil group in the predetermined direction. At each moved position, scanning is performed on a given pulse sequence. An echo signal is received through the multiple RF coils, then switched over by an input switchover unit to be sent to a receiving-system circuit. The echo signal is subjected to given processing in this circuit so that it is converted to echo data. The echo data are produced into an MR image by a host computer.

Abstract: A magnet for an NMR analyzer includes a superconductor coil for generating a magnetic field in a magnetic space surrounded by the superconductor coil. The superconductor coil has a shim coil group disposed at least one of inside and outside of the superconducting coil. The superconducting coil provides a first access port for receiving a probe inserted into the magnetic space along a central axis thereof and a second access port having one end for receiving a sample tube containing a sample inserted into the magnetic space in a direction transverse to the central axis of the magnetic space. The second access port is open at an other end thereof.

Abstract: Portable locators are disclosed for finding and mapping buried objects such as utilities. A articulatable antenna node configuration and the use of Doppler radar and GPS navigation are also disclosed.

Abstract: An aerial electronic system for detection of surface and underground threats comprises an electromagnetic (EM) gradiometer flown aloft over the possible ground and underground threats to a convoy. The EM gradiometer is disposed in a Styrofoam torpedo shaped pod that is towed in flight behind an airplane. An illumination transmitter and loop antenna mounted to the airplane radiate a primary EM wave that travels down to the ground surface and penetrates beneath. Frequencies of 80 KHz to 1 MHz are selected according to whether the targets are laying on the surface or deeply buried. Detonation wire pairs, buried cables and pipes, and other conductors will re-radiate a secondary wave that can be sensed by the EM gradiometer. A reference sample of the transmitter signal is carried down a fiberoptic from the airplane to the towed pod. This signal is used in the synchronous detection to measure the secondary EM wave phase.

Abstract: Multi-component induction measurements are made using a resistivity logging tool in an anistropic earth formation. A subset of the multi-component measurements are inverted to first determine horizontal resistivities. Using the determined horizontal resistivities and another subset of the multi-component measurements, the vertical resistivities are obtained. Results of using the in-phase signals are comparable to those obtained using multifrequency focusing of quadrature signals.

Abstract: A cell evaluation device has a short circuit detection portion to detect an internal short circuit within a test cell that has been subjected to nail penetration or crushing using the pressure from a pressurization portion, a pressure control portion to halt the operation of the pressurization portion on detection of a short circuit, and a cell information detection portion to collect and record cell information such as the cell temperature. By using such a cell evaluation device, the location of an internal short circuit during an abuse test is specified, and variations in the cell temperature increase accompanying the internal short circuit is minimized.

Abstract: A vehicle circuit tester for electrically testing the circuit system of a trailer. The tester can connect to a variety of types of trailers for the purpose of analyzing or monitoring the trailer's circuit system. The tester includes indicators that indicate continuity of the various circuits, thus confirming operability of the trailer lamps. The tester includes wiring connectors in a variety of dimensions and plug configurations, most of which are standardized and widely adopted. As such, the vehicle circuit tester is provided with a plurality of wiring connectors conventionally provided on different sizes and types of trailers. The tester includes probe and ground wires that can be wound up on a reel inside the tester.

Abstract: A connecting sleeve generally used for a bus bar connection is produced from an insulating elastic material, often an elastomer material, having insulating properties which are deteriorated by partial discharges and decrease over the operating time of the switchboard system. According to the invention, so-called partial discharge measuring methods must be carried out, inter alia also in the UHF range (UHF: ultra high frequency), in order to identify damaging effects on the insulating material in time. For the reliable and simple detection of the measuring signals, the connecting sleeve (M) has an outer, electroconductive surface (OA) which is earthed, and an inner, electroconductive surface (OI) to which the voltage potential of the bus bar (S) is applied, in addition to a coupling electrode (KE) which is integrated into the insulating material (I).

Abstract: A delay lock circuit includes a measuring path, a forward path, and a feedback path. The measuring path samples a pulse with a reference signal in a measurement to obtain a measured delay. The forward path delays the reference signal based on the measured delay to generate an internal signal. The feedback path includes a calibrating unit for generating the pulse based on a plurality of feedback signals generated from the reference signal. The delay lock circuit further includes a monitoring unit for monitoring the measurement. Based on the monitoring, the monitoring unit enables the calibrating unit to conditionally adjust the width of the pulse.

Abstract: A circuit arrangement for detecting a load current through a load includes a main transistor, a sensing transistor through which a load current flows that is a measure of the load current flowing through the main transistor. In addition, a resistance is connected in series with the load path of the sensing transistor, and a current source is connected to a node arranged between the sensing transistor and the resistance. A detector detects the load current flowing through the main transistor by measuring the voltage across the resistance.

Abstract: An apparatus and method are disclosed for measuring bias of polysilicon shapes relative to a silicon area wherein the presence of an electrical coupling is used to determine the presence of bias. Bridging vertices on the polysilicon shapes are formed. Bridging vertices over the silicon area create low resistance connections between those bridging vertices and the silicon area; other bridging vertices over ROX (recessed oxide) areas do not create low resistance connections between those other bridging vertices and the silicon area. Determining which bridging vertices have low resistance connections to the silicon area and how many bridging vertices have low resistance connections to the silicon area are used to determine the bias of the polysilicon shapes relative to the silicon area.

Abstract: The invention relates to printed circuit board test devices (1) comprising a support (4) receiving a circuit board (5) by said board's edges, said board being designed to be fitted as needed with electrical or electronic components (20), said devices further comprising at least one needle (15) which is connected to an electrical test device (17) and which shall electrically contact contact areas (21) on the board (5), the needle (15) being obliquely displaceable by a needle drive (13) in the needle direction, the needle drive being adjustable—by at least one holding-fixture drive (8)—in a adjustment plane (7) which is parallel to the circuit board (5), the drives (8, 13) being actuated by a needle control (10) to spatially position the needle tip (18) at a predetermined spatial coordinate, said devices (1) being characterized in that it includes a distance measuring device (25, 13?) designed to measure the distance between the adjustment plane (7) and the circuit board (5, 5?) at least at one site and to tran

Abstract: A test apparatus for testing a device under test (DUT) to detect a defect comprises a measurement circuit (ME), a threshold circuit (TH), and a control circuit (CG). The measurement circuit (ME) comprises a counter (C1) which counts clock pulses (OLK) during a count period (TC) to obtain a counted number (N) of clock pulses (CLK). The count period (TC) has a start determined by the start (tl) of a testing cycle which occurs at the instant a switch (S) which is coupled to an terminal (IN) of the device under test (DUT) removes a power supply voltage (VDD) from the terminal (IN) and the voltage (VDD?) at the terminal (IN) starts decaying. An end of the count period (TC) is determined by an instant (t2) a comparator (COM1) detects that the voltage (VDD?) at the terminal (IN) crosses a reference value (VREF). The control circuit (CG) generates the clock signal (CLK) and/or a reference number (NTH) taking into account the variability of the manufacturing process of the circuit under test (CUT).

Abstract: A power line control circuit of a semiconductor device in which a width of a power line can be selectively controlled. The power line control circuit of the semiconductor device according to the present invention can selectively control the width of the power line employing the dummy power line. It is therefore possible to easily change the width of the power lines and to reduce the manufacturing cost and the manufacturing time depending on the formation of the power lines. Furthermore, the power line control circuit of the semiconductor device according to the present invention can selectively control the width of the power lines, if appropriate. Accordingly, mesh of optimized power lines can be provided. Furthermore, more stabilized product characteristics can be secured and the yield of semiconductor memory devices can be enhanced.

Abstract: Systems and methods for frequency specific closed loop feedback control of integrated circuits. In one embodiment, a plurality of controllable inputs to an integrated circuit is adjusted to achieve a frequency specific predetermined value of a dynamic operating indicator of the integrated circuit at the desired specific operating frequency. The predetermined value is stored in a data structure within a computer usable media. The data structure comprises a plurality of frequency specific predetermined values for a variety of operating frequencies. An operating condition of an integrated circuit is controlled via closed loop feedback based on dynamic operating indicators of the measured behavior of the integrated circuit.

Abstract: An assembly for simultaneously electrically testing a plurality of electronic components. There is a test fixture, and a lead frame carrying a plurality of electronic components to be tested, each such electronic component having multiple electrical leads. A layer of Anisotropic Conductive Elastomer (ACE) is in contact with the test fixture and in contact with the leads of the plurality of electronic components. There is a device for applying a compressive force to the leads, the ACE and the test fixture, to make electrical contact between the leads and the test fixture through the ACE.

Abstract: Systems and methods for closed loop feedback control of integrated circuits. In one embodiment, a plurality of controllable inputs to an integrated circuit is adjusted to achieve a predetermined value of a dynamic operating indicator of the integrated circuit. An operating condition of an integrated circuit is controlled via closed loop feedback based on dynamic operating indicators of the integrated circuit's behavior.

Abstract: A test circuit for a flat panel display device is provided. The test circuit includes a substrate, a plurality of pixel structures, a plurality of signal lines and a plurality of shorting bar sets. The substrate includes at least one scan side, at least one data side and a pixel area. Each pixel structure formed in the pixel area having n sub-pixels, where n is a positive integer. The signal lines are formed on the substrate, and each signal line is connected to a corresponding sub-pixel. Each shorting bar set is formed on at least one of the at least one scan side and the at least one data side, wherein the shorting bar sets are electrically connected to the signal lines.

Abstract: A plurality of individually retractable racks on which a single module is mounted on each rack is disposed on the upper and middle tiers of a portable carriage main body. Provided to the lower tier of the carriage main body are a operating panel for setting work content and conditions; a signal source for selectively outputting a circuit adjustment signal, an aging testing signal, and a display inspection signal; a power supply for circuit adjustment, a power supply for aging testing, and a power supply for display inspection; and an output unit for selecting an operation from circuit adjustment, aging testing, and display inspection on the basis of the work content and work conditions that have been input in the operating panel, and feeding the power and signals for the selected operation to the modules.

Abstract: Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fuses (eFUSES).

Abstract: A communication system having first and second states for use with a shared transmission line composed of at least two conductors and composed of first and second transmission line segments connected to each other at a single connection point. In the first state, a termination is coupled to the single connection point and is operative to at least attenuate a signal propagated between the first and second segments. In the second state, a driver is coupled to the connection point and is operative to conduct a signal over the first and second segments.

Abstract: A programmable look-up-table (LUT) structure adapted for carry logic incrementer implementation in an integrated circuit, comprising: three or more data inputs and a carry-in input, said data inputs comprised of consecutive bits in a data string, said carry-in comprised of the increment value to the least order bit of said data string; and three or more data outputs and a carry-out output, said data outputs comprised of the incremented values of said data inputs, and said carry-out resulting from the incremented value of the highest order bit of said data inputs; wherein, said three or more data outputs are computed in a single carry computation stage within the LUT structure.

Abstract: Apparatus and method for producing memory modules having a plurality of branches connected to a memory bus, each branch containing at least one dynamic random access memory (DRAM) device or SDRAM device connected to the memory bus via at least one transmission signal (TS) line and/or at least one sub-transmission signal (STS) line. The memory modules include at least one branch containing a capacitor connected in parallel to the TS line or STS line and the DRAM device or SDRAM device. A computing system implementing the memory modules is also discussed.

Abstract: A multiplexer can be implemented in a programmable logic device, using addition elements which are optimised for performing a one-bit addition function. A logic device receives a first data input value and a first select input. The logic device then routes the first data input to the addition element as a first input one-bit value, and routes either the first data input or its inverse to the addition element as a second input one-bit value, depending on the value of the first select input.

Abstract: A level converter for interfacing two circuits supplied by different supply voltages, and integrated circuit including the level converter interfacing circuit in two different voltage islands. A first buffer is supplied by a virtual supply and receives an input signal from a lower voltage circuit. The first buffer drives a second buffer, which is supplied by a higher supply voltage. An output from the second buffer switches a supply select to selectively pass the higher supply voltage or a reduced supply voltage to the first buffer.

Abstract: A control circuit including a first control unit, controlling a logic circuit, connected between a power supply and a virtual ground, the control unit connecting the virtual ground to a ground in response to a mode control signal when the logic circuit operates in an active mode and disconnecting the virtual ground from the ground in response to the mode control signal when the logic circuit operates in a sleep mode. A method of controlling including connecting the logic circuit between a power supply and a virtual ground, connecting the virtual ground to a ground in response to a mode control signal when the logic circuit operates in an active mode, and disconnecting the virtual ground from the ground in response to the mode control signal when the logic circuit operates in a sleep mode.

Abstract: The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors.

Abstract: Stacked inverter delay chains. In accordance with a first embodiment of the present invention, a series stack of two p-type devices is coupled to a series stack of three n-type devices, forming a stacked inverter comprising desirable delay, die area and power characteristics. Two stacked inverters are coupled together to form a stacked inverter delay chain that is more efficient in terms of die area, active and passive power consumption than conventional delay chains comprising conventional inverters.

Abstract: A logic circuit consists of a first transistor network and a complementary second transistor network connected at a central node. The central node serves as a first logic output. Each of the transistor networks is also connected to a respective root. A third transistor network is connected between an intermediate node of one of the transistor networks and the network's respective root. For a homogeneous graft, the third transistor network has a complementary structure to the transistors between the intermediate node and the central node, is of the same transistor type as the given transistor network, and has inverted inputs relative to the transistors between the intermediate node and the central node. The third transistor network (the graft network) provides a second logic output to the logic circuit.

Abstract: A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The dynamic node has a keeper circuit comprising an inverter with its input coupled to the dynamic node and its output coupled to the back gate of a dual gate PFET device. The source of the dual gate PFET is coupled to the power supply and its drain is coupled to the dynamic node forming a half latch. The front gate of the dual gate PFET is coupled to a logic circuit with a mode input and a logic input coupled back to a node sensing the state of the dynamic node. The mode input may be a slow mode to preserve dynamic node state or the clock delayed that turns ON the strong keeper after evaluation.

Abstract: A phase detector generates a first output signal if a feedback clock signal leads a reference clock signal by more than a first time. The phase detector generates a second output signal if the feedback clock signal lags the reference clock signal by more than a second time. If the feedback clock signal either leads the reference clock signal by less than the first time or lags the reference clock signal by less than the second time, neither output signal is generated. The phase detector may be used in a delay-lock loop in which the first and second output signals increase or decrease a delay of the reference clock signal by respective first and second delay increments. In such case, the each of the first and second delay increments should be less than the sum of the first and second times.

Abstract: This invention provides a comparator circuit which outputs a stable waveform without oscillation even if a gradient of a change of a comparison input signal is small and determines a magnitude of the comparison input signal within a predetermined threshold value regardless of the increase/decrease direction of the comparison input signal.

Abstract: A semiconductor integrated circuit includes a pump circuit configured to raise an external power supply voltage to generate a stepped-up voltage, and a detector circuit configured to detect the stepped-up voltage generated by the pump circuit to control activation/deactivation of the pump circuit, wherein the detector circuit includes a differential amplifier configured to compare the stepped-up voltage with a reference voltage, and a current control circuit configured to control an amount of a bias current running through the differential amplifier in response to the activation/deactivation of the pump circuit.

Abstract: A plurality of output drive devices are capable of tolerating an overvoltage produced by an electrical connection with an external device operating in a high-voltage supply realm. The drive devices are capable of sustaining a continuous electrical connection to the elevated voltage levels and produce communications at an output voltage level equal to the supply voltage indigenous to the device. A high-voltage tolerant driver includes a plurality of output drive devices capable of tolerating an overvoltage, sustaining an electrical connection to an elevated voltage level, and producing an output voltage at an indigenous supply level. An initial pullup drive circuit is coupled to the plurality of output drive devices and produces an initial elevated drive voltage to the plurality of output drive devices. A sustain pullup circuit is coupled to the plurality of output drive devices and produces a sustained output voltage at the indigenous supply level.

Abstract: A dual differential sawtooth signal generator includes a first sawtooth voltage generator that has a first capacitor and a second capacitor that are alternately charged with a feedback control source current from a low voltage reference voltage level. A second sawtooth voltage generator has a first discharge capacitor and a second discharge capacitor that are alternately discharged with a feedback control sink current from a high voltage reference voltage level. The output signals of the two sawtooth voltage generators are compared to control a phase frequency comparator that provides signals to control a dual charge pump that provides the feedback control source current and that provides the feedback control sink current.

Abstract: An apparatus for synchronizing signals. For devices, such as memory devices, implementing a synchronization device to synchronize signals, a synchronization device having a delay locked loop coupled to a phase locked loop may be implemented. The delay locked loop is implemented to measure the period of a reference signal and to mirror the period into a second delay line such that an adjusted reference signal having a frequency approximately equal to the frequency of the reference clock may be generated. The adjusted reference signal is delivered to an oscillator such that the oscillator begins oscillating at approximately the same frequency as the reference clock signal to provide a fast locking synchronization device.

Abstract: A delay-locked loop (DLL) to produce a plurality of delayed clock signals comprising combinational logic for false lock detection is provided. The combinational logic uses only a subset of the plurality of delayed clock signals to provide a forward indicator indicating a delay period (?t) is longer than a desired delay period. The combinational logic further provides a back indicator indicating the delay period (?t) is shorter than a desired delay period.

Abstract: A controller that is linearly responsive to an input voltage provides continuously adjustable control of the width of a periodically repeating digital pulse, thereby achieving a linear voltage to duty-cycle ratio transfer function. The circuit of the present invention includes a master clock input, a ratio control voltage input, a controlled duty cycle clock output, a high gain amplifier configured as an integrator having differential inputs, each equipped with a low pass filter, a controlled current source, a resettable timing capacitor, a threshold detector and a reference pulse generator.

Abstract: The inventive technique can dynamically adjust the current being applied within the components of a prescaler or divider. This dynamic scaling of the current can improve the speed of the divider by a factor of two or reduce the average current in half when compared to the conventional prescaler. Inverters are used to directly adjust the dynamic value of the currents. The removal of the conventional NMOS device within the conventional circuit eliminates one gate delay in the CML prescaler. Second, the inventive prescaler circuits operate under a current injection/extraction technique. A group of small matched inverters can be used to drive each current switching circuit independently within the entire prescaler as compared to a large buffer driving the entire conventional prescaler. Finally, dynamic current scaling offers the designer additional flexibility in the design trade off between the maximum current applied to the load and achieving the maximum performance.

Abstract: A signal distribution tree structure for distributing signals within a plurality of signal tree branches to a plurality of signal sinks, wherein the signal in subsequent sub trees (11) is driven by a preceding amplifier (2), which is characterized in that the amplifiers are logic gates (3), which combines the signals of a preferred input (31) connected to a preceding logic gate in the signal path with a signal of a secondary input (32) connected to an adjacent tree (12) path of a neighboring and/or preceding sub tree.

Abstract: The clock supply circuit of the present invention comprises a plurality of clock supply paths and a clock gate circuit. The clock supply paths branch a clock signal and supply each of the branched clock signals to a plurality of sequential circuits via a buffer. The clock gate circuit is inserted at least to one of the clock supply paths, which lets through the clock signals when a control signal is in a first logic state and, when the control signal is in a second logic state, outputs an inversion signal of a logic level that is outputted in a previous occasion where the control signal in the second logic state is applied.

Abstract: A dual power supply digital device includes a down converter for converting an externally applied supply voltage to a regulated first supply voltage for powering a core part of the logic circuitry of the digital device. A second supply voltage source provides a second supply voltage for powering input buffers of the I/O pads of the digital device. A voltage translator latch stage may be powered at the regulated down converted first supply voltage for replicating a stored inverted replica of a logic value present on a respective I/O pad of the digital device onto an input node of a respective second input logic buffer powered at the regulated core supply voltage. The device may further include a transistor having a turn-on threshold coupling the input node of the second buffer to the regulated down converted core supply voltage, with the transistor having a control gate connected to the second power supply source.