Patents Issued in February 28, 2008
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Publication number: 20080049492Abstract: An electron spin-based memory cell has a first ferromagnetic layer with a changeable magnetization state and a second ferromagnetic layer with a fixed magnetization state. A non-volatile logic state of such cell is dependent on a relationship between said first ferromagnetic layer and said second ferromagnetic layer, including whether said changeable magnetization state and said fixed magnetization state are parallel or antiparallel. To facilitate writing, the cell is adapted carry at least a portion of a write pulse.Type: ApplicationFiled: October 30, 2007Publication date: February 28, 2008Inventor: Mark Johnson
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Publication number: 20080049493Abstract: A method of post-programming a flash memory device includes the steps of: post-programming memory cells of a selected word line in a predetermined unit; determining, after incrementing an address for selecting the next word line, whether the incremented address matches one of reference addresses; and varying the post-programming unit of the selected memory cells whenever the incremented address matches one of reference addresses.Type: ApplicationFiled: December 29, 2006Publication date: February 28, 2008Inventors: Doo-Sub Lee, Jong-In Choi
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Publication number: 20080049494Abstract: A method for programming that biases a selected word line with a programming voltage. An unselected word line on the source side and an unselected word line on the drain side of the selected word line are biased at a pass voltage that is less than the normal pass voltage. These unselected word lines are both located a predetermined distance from the selected word line. The remaining word lines are biased at the normal pass voltage.Type: ApplicationFiled: August 22, 2006Publication date: February 28, 2008Inventor: Seiichi Aritome
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Publication number: 20080049495Abstract: Methods and apparatuses for automatically measuring memory cell threshold voltages are disclosed. Measurement circuitry includes an internal reference current generator, a plurality of memory cells, a pre-charge bit line reference circuit, and comparator and latch circuitry. If the reference current is greater than the memory cell current, the bit line voltage will increase. Conversely, if the reference current is less than the memory cell current, the bit line voltage will decrease. The reference current is generated in large steps until a comparator, that compares the bit line voltage and a pre-charged bit line reference voltage, is switched. The reference current then generates a current in small steps until the comparator is again switched. The reference current converges on the memory cell current within an accuracy of 10 nA. The memory cell threshold voltage is then determined from the memory cell current. Systems including memory according to an embodiment of the invention are also disclosed.Type: ApplicationFiled: August 28, 2006Publication date: February 28, 2008Inventor: Shigekazu Yamada
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METHOD FOR MODIFYING DATA MORE THAN ONCE IN A MULTI-LEVEL CELL MEMORY LOCATION WITHIN A MEMORY ARRAY
Publication number: 20080049496Abstract: A method and apparatus for programming one or more bits in an upper page twice depending on the value in a corresponding bit in a corresponding lower page in a multi-level cell device. The method includes the steps of initializing the bit in the lower page and the bit in the upper page by storing a value of one in each of the bits. One or more bits in the lower page are then programmed such that a one is stored in the one or more bits of the lower page. One or more bits in the upper page are then programmed such that a one is stored in the one or more bits of the upper page. The one or more bits in the upper page are then reprogrammed such that the value in the one or more bits of the upper page transitions from a one to a zero. The transition from a one to a zero in the one or more bits of the upper page is used to mark for performance of a block management function the block.Type: ApplicationFiled: August 22, 2006Publication date: February 28, 2008Inventor: Michael M. Abraham -
Publication number: 20080049497Abstract: Methods of programming a multi-bit non-volatile memory device are provided. The multi-bit non-volatile memory device includes a memory cell array including a plurality of memory cells and a storage unit electrically coupled to the memory cell array. A first bit (FB) of multi-bit data is programmed from the storage unit into one of the plurality of memory cells in the memory cell array. A second bit (SB) of multi-bit data is programmed from the storage unit into one of the plurality of memory cells in the memory cell array using data inversion. Related memory devices are also provided.Type: ApplicationFiled: August 22, 2007Publication date: February 28, 2008Inventor: Hyun Sun Mo
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Publication number: 20080049498Abstract: Techniques are used to store information in a medium such as the memory cells of an integrated circuit, and also retrieval of information from the medium. The integrated circuit includes nonvolatile memory cells (416) capable of multilevel or analog voltage level storage. The integrated circuit may store or record information in analog or digital form, or both. Information is stored in and retrieved from the integrated circuit using a user-selected sampling frequency. The user's selection of the sampling frequency is stored within the integrated circuit.Type: ApplicationFiled: October 22, 2007Publication date: February 28, 2008Inventors: Carl Werner, Andreas Haeberli, Leon Wong, Cheng-Yuan Wang, Hock So, Sau Wong
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Publication number: 20080049499Abstract: A flash memory device includes: a memory cell array including pluralities of blocks; a block status storage unit including pluralities of latch cells arranged in rows and columns to store block status information signals corresponding to each of the blocks and providing the block status information signals in response to each of the write and read addresses; and a controller regulating an access to the memory cell array in response to the block status information signals. The block status storage unit provides information about whether a read address input during a read-while-write operation or suspend read operation is valid, and offers information about whether a current block is a write block or a write protection block.Type: ApplicationFiled: November 28, 2006Publication date: February 28, 2008Inventor: Doo-Sub Lee
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Publication number: 20080049500Abstract: A highly-integrated nonvolatile memory. A memory cell array where plural memory cells are arranged in matrix in row and column directions, plural first and second word lines, and plural bit lines are included. Each of the plural memory cells includes a first memory transistor and a second memory transistor which are connected in series. A gate electrode of the first memory transistor is connected to the first word line, a gate electrode of the second memory transistor is connected to the second word line, one of source and drain regions of the first memory transistor is connected to the first bit line, and one of source and drain regions of the second memory transistor is connected to the second bit line. Each of the first bit line and the second bit line is provided in common for memory cells in columns which are adjacent to each other.Type: ApplicationFiled: July 12, 2007Publication date: February 28, 2008Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Kiyoshi Kato, Shunpei Yamazaki
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Publication number: 20080049501Abstract: The present invention provides a cell array of a flash memory device. The cell array includes a memory cell transistor connected to a word line, a first selection transistor for controlling a first connection between the memory cell transistor and a bit line in response to a selection signal, and a second selection transistor for controlling a second connection between the memory cell transistor and a common source line in response to the selection signal.Type: ApplicationFiled: July 23, 2007Publication date: February 28, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Ho-Jung KIM
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Publication number: 20080049502Abstract: A flash memory and a program method of the flash memory include applying a pass voltage to word lines to boost a channel voltage, which is discharged to a ground voltage. A program voltage is applied to a selected word line and a local voltage is applied to at least one word line supplied with the pass voltage while the program voltage is being applied to the selected word line. The local voltage is lower than the pass voltage and equal to or higher than the ground voltage. The boosted channel voltage may be discharged before the program voltage is applied to the selected word line.Type: ApplicationFiled: July 30, 2007Publication date: February 28, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dae-Seok BYEON, Young-Ho LIM
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Publication number: 20080049503Abstract: A nonvolatile storage is disclosed which has a plurality of blocks each serving as one unit in erasing operation and performs a plurality of erasing operations successively, the nonvolatile storage comprising: a volatile memory cell array for storing erase setting information on each block, the information indicating whether or not its associated block is a target to be erased; a write amplifier for writing the erase setting information in the volatile memory cell array; a first readout amplifier for reading out the erase setting information on a target block from the volatile memory cell array upon start of the erasing operation; and a second readout amplifier for reading out the erase setting information on a target block from the volatile memory cell array upon start of readout operation.Type: ApplicationFiled: July 18, 2007Publication date: February 28, 2008Inventors: Mitsuhiro Nagao, Masahiro Niimi, Kenji Nagai
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Publication number: 20080049504Abstract: An address at which a writing error occurs is held, and after a completion of a series of writings, the data of the held address is read. Then, a faulty-block processing is performed only for the addresses, for which it is determined that retry of writing is required, thereby preventing an increase of faulty-blocks. This can suppress the problem that when a writing is performed in a particular flash memory, a writing error frequently occurs and a large number of faulty blocks occur.Type: ApplicationFiled: May 12, 2005Publication date: February 28, 2008Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Tetsushi Kasahara, Tomoaki Izumi, Masahiro Nakanishi, Kazuaki Tamura, Kiminori Matsuno, Yoshihisa Inagaki, Manabu Inoue
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Publication number: 20080049505Abstract: A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol. The command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data. The modular command protocol is used for executing concurrent operations in each memory device to further improve performance.Type: ApplicationFiled: August 22, 2007Publication date: February 28, 2008Applicant: MOSAID TECHNOLOGIES INCORPORATEDInventors: Jin-Ki KIM, HakJune OH, Hong Beom PYEON, Steven PRZYBYLSKI
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Publication number: 20080049506Abstract: A set of storage elements is programmed beginning with a word line WLn adjacent a select gate line for the set. After programming the first word line, the next word line WLn+1 adjacent to the first word line is skipped and the next word line WLn+2 adjacent to WLn+1 is programmed. WLn+1 is then programmed. Programming continues according to the sequence {WLn+4, WLn+3, WLn+6, WLn+5, . . . } until all but the last word line for the set have been programmed. The last word line is then programmed. By programming in this manner, some of the word lines of the set (WLn+1, WLn+3, etc.) have no subsequently programmed neighboring word lines. The memory cells of these word lines will not experience any floating gate to floating gate coupling threshold voltage shift impact due to subsequently programmed neighboring memory cells. The word lines having no subsequently programmed neighbors are read without using offsets or compensations based on neighboring memory cells.Type: ApplicationFiled: October 31, 2007Publication date: February 28, 2008Inventor: Daniel Guterman
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Publication number: 20080049507Abstract: A flash memory device comprises a memory cell array including a plurality of NAND strings respectively connected to a plurality of bit lines, and further comprising a disturbed string coupled to a disturbed bit line. In a program operation of the flash memory device, a voltage level of the disturbed bit line is detected to detect program or pass voltage disturbance in the memory cell array.Type: ApplicationFiled: March 30, 2007Publication date: February 28, 2008Inventor: Jong-Soo Lee
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Publication number: 20080049508Abstract: A nonvolatile semiconductor memory includes a memory cell array having a plurality of NAND cell units which are arranged with a plurality of memory cells connected in series and a first selection transistor and a second selection transistor which are each connected to both ends of the plurality of memory cells respectively, a plurality of word lines and a plurality of bit lines which are connected to the plurality of memory cells and a data read control part wherein at least one of the memory cells is selected and when data is read from that memory cell a read pass voltage is applied to a word line which is connected to a non-selected memory cell other than the selected memory cell, and after applying the read pass voltage a voltage is applied to a control gate of the first selection transistor or the second selection transistor, and when applying the read pass voltage, the read pass voltage which is applied to the word line which is connected to at least one of the non-selected memory cells which is adjacentType: ApplicationFiled: August 14, 2007Publication date: February 28, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Makoto IWAI, Yoshihisa Watanabe
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Publication number: 20080049509Abstract: A nonvolatile semiconductor memory device includes a memory cell array 101 having a plurality memory strings, each of said plurality of memory strings having a plurality of memory cells connected in series, each of said plurality of memory cells having a control gate, said plurality of memory cells including a read-memory cell whose programmed data is read and a plurality of non-read-memory cells other than said read-memory cell, each said control gate of each said plurality of non-read-memory cells being applied with a read pass voltage to read said programmed data programmed in said read-memory cell, a read pass voltage application control part 201 for applying a predetermined read pass voltage to the control gates of all non-read memory cells among said plurality of memory cells other than a read-memory cell whose stored data are read, and a clock signal cycle control part 203 for controlling a cycle of a clock signal which is provided to said read pass voltage application control part 201.Type: ApplicationFiled: August 23, 2007Publication date: February 28, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Makoto Iwai
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Publication number: 20080049510Abstract: A Flash memory controller is disclosed. The Flash memory controller comprises a host interface, a Flash memory interface, controller logic coupled between the host interface the controller logic handling a plurality of voltages. The controller also includes a mechanism for allowing a multiple voltage host to interface with a high voltage or a multiple voltage Flash memory. A multiple voltage Flash memory controller in accordance with the present invention provides the following advantages over conventional Flash memory controllers: (1) a voltage host is allowed to interface with multiple Flash memory components that operate at different voltages in any combination; (2) power consumption efficiency is improved by integrating the programmable voltage regulator, and voltage comparator mechanism with the Flash memory controller; (3) External jumper selection is eliminated for power source configuration; and (4) Flash memory controller power source interface pin-outs are simplified.Type: ApplicationFiled: November 8, 2007Publication date: February 28, 2008Applicant: Kingston Technology Company, Inc.Inventors: Ben Wei Chen, David Chen, David Sun
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Publication number: 20080049511Abstract: The capacitive coupling between two adjacent bitlines of a NAND memory device may be exploited for boosting the voltage of bitlines that are not to be programmed in order to inhibit program operations on them. The even (odd) bitlines that include cells not to be programmed are biased with a first voltage for inhibiting them from being programmed while the even (odd) bitlines that include cells to be programmed are grounded. The adjacent odd (even) bitlines are biased at the supply voltage or at an auxiliary voltage for boosting the bias voltage of the even (odd) bitlines above the supply voltage. The bias voltage of the even (odd) bitlines that include cells not to be programmed is boosted because of the relevant parasitic coupling capacitances between adjacent bitlines.Type: ApplicationFiled: July 26, 2007Publication date: February 28, 2008Applicants: STMicroelectronics S.r.I., Hynix Semiconductor, Inc.Inventors: LUCA CRIPPA, ROBERTO RAVASIO, RINO MICHELONI
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Publication number: 20080049512Abstract: A method for conducting programming and erasure of charge-trapped memory devices includes: conducting at least one program/erase cycle of a charge-trapped memory device on the basis of a given threshold voltage of the charge-trapped memory device as a reference point; determining a wear-level of the erasing procedure; shifting the reference point according to a result of the determination of the wear-level; conducting one or more program/erase cycle on the basis of the shifted threshold; and conducting read and verify operations on the basis of the shifted threshold.Type: ApplicationFiled: August 23, 2006Publication date: February 28, 2008Inventors: Konrad Seidel, Uwe Augustin, Gert Koebernick, Soren Irmer, Daniel-Andre Loehr, Volker Zipprich-Rasch, Mirko Reissmann
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Publication number: 20080049513Abstract: A method and apparatus are provided for programming a non-volatile data storage device, in which a fast write operation can be performed using a plurality of page buffers included in the non-volatile data storage device when the write operation is performed in a way of using interleaving for each channel in a multi-channel system using a plurality of non-volatile data storage devices. The method includes programming data in a memory cell array included in the non-volatile data storage device using a page buffer selected from among a plurality of page buffers included in the non-volatile data storage device and performing a setup operation for loading data using another page buffer, which is different from the page buffer selected during the programming.Type: ApplicationFiled: March 5, 2007Publication date: February 28, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seong-hun Jeong, Houng-sog Min, Dong-woo Lee, Shin-wook Kang, Hyang-suk Park
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Publication number: 20080049514Abstract: An automatic redundancy system may exploit an existing microprocessor management system on chip for carrying out autonomously, without communicating with an external testing machine, the operations of: writing data in the memory array according to one or more pre-established test patterns, verifying data successively read from the memory array, and substituting failed elements of the memory array with equivalent redundancy structures. A logic structure may detect and store memory array failures upstream of the output data path. Thereby, data collection relating to failures may be accomplished more quickly and without any interaction with the testing machine apart from communicating the end of the execution of the redundancy process.Type: ApplicationFiled: July 20, 2007Publication date: February 28, 2008Applicant: STMicroelectronics S.r.l.Inventors: Antonino Mondello, Alessandro Tumminia, Luigi Buono
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Publication number: 20080049515Abstract: Obtained is a highly-reliable non-volatile memory without increasing the area of a memory cell or adding a step to a CMOS process. The non-volatile memory includes an SRAM cell configured of 6 MOS transistors, a first word line electrically connected to the gate of a first transfer MOS transistor, and a second word line electrically connected to the gate of a second transfer MOS transistor. During a write operation of a first PMOS transistor, a drive circuit applies a positive voltage whose absolute value is not larger than a junction breakdown voltage to an n-type well as well as the sources of first and second PMOS transistors, concurrently applying the positive voltage to the first word line and a ground voltage to the second word line and a first data line.Type: ApplicationFiled: August 21, 2007Publication date: February 28, 2008Applicant: NEC ELECTRONICS CORPORATIONInventors: Noriaki Kodama, Kenichi Hidaka
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Publication number: 20080049516Abstract: A method is provided for programming a nonvolatile memory device including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window that identifies a plurality of memory cells in the array. A first group of memory cells to be programmed is identified from the plurality of memory cells in the programming window. The first group of memory cells is programmed and a programming state of the first group of memory cells is verified.Type: ApplicationFiled: October 31, 2007Publication date: February 28, 2008Applicant: SPANSION L.L.C.Inventors: Aaron LEE, Hounien CHEN, Sachit CHANDRA, Nancy LEONG, Guowei WANG
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Publication number: 20080049517Abstract: A multi-level non-volatile memory including a memory cell disposed on a substrate is provided. The memory cell includes a control gate, a charge storage layer, a doped region, a select gate, and an assist gate. The control gate is disposed on the substrate. The charge storage layer is disposed between the control gate and the substrate. The doped region is disposed in the substrate at the first side of the control gate. The select gate is disposed on the sidewall of the first side of the control gate and on the substrate between the control gate and the doped region. The assist gate is disposed on the sidewall of the second side of the control gate. An inversion layer is formed in the substrate below the assist gate when a voltage is applied to the assist gate.Type: ApplicationFiled: August 25, 2006Publication date: February 28, 2008Applicant: POWERCHIP SEMICONDUCTOR CORP.Inventors: Chih-Wei Hung, Chih-Chen Chou
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Publication number: 20080049518Abstract: A method of charging a floating gate in a nonvolatile memory cell comprises bringing a substrate channel within the memory cell to a first voltage, bringing a control gate to a programming voltage, and floating the substrate channel voltage while the control gate is at the programming voltage. Memory devices include state machines or controllers operable to perform the described method, and operation of such a state machine, memory device, and information handling system are described.Type: ApplicationFiled: August 28, 2006Publication date: February 28, 2008Inventors: Ramin Ghodsi, Qiang Tang
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Publication number: 20080049519Abstract: Electronic circuitry is described having a first transistor having a first gate dielectric located between an electrically floating gate and a semiconductor substrate. The first injection current flows through the first gate dielectric to establish a first amount of electrical charge on the gate electrode. The electronic circuitry also includes a second transistor having a second gate dielectric located between the gate electrode and the semiconductor substrate. A band-to-band tunneling current flows between valence and conduction bands of the second transistor to create a second injection current that flows through the second gate dielectric to establish the first amount of electrical charge on the gate electrode. Non volatile memory cell circuits having the above described circuitry are also described.Type: ApplicationFiled: November 16, 2006Publication date: February 28, 2008Inventor: Andrew E. Horch
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Publication number: 20080049520Abstract: Provided are a flash memory system and a programming method performed in the flash memory system. The flash memory system includes a buffer unit including a plurality of buffers, and temporarily storing data transmitted by a host; a plurality of channel units each including at least one flash memory chip that includes a plurality of memory cell arrays; and a control unit which controls the data stored in the buffer unit to be sequentially transmitted to the channel units and the transmitted data to be recorded to the memory cell arrays of the flash memory chips in the channel units.Type: ApplicationFiled: April 4, 2007Publication date: February 28, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Shin-wook Kang, Dong-woo Lee
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Publication number: 20080049521Abstract: A method for operating a flash memory device. The memory device includes a matrix of memory cells each one having a programmable threshold voltage defining a value stored in the memory cell. The method includes the steps of erasing a block of memory cells, and compacting the threshold voltages of the memory cells of the block within a predefined compacting range, wherein the step of compacting includes: selecting at least one first memory cell of the block for writing a target value; restoring the threshold voltage of a subset of the memory cells of the block to the compacting range, the subset including the at least one first memory cell and/or at least one second memory cell of the block being adjacent to the at least one first memory cell; and at least partially writing the target value into the at least one first memory cell.Type: ApplicationFiled: August 24, 2007Publication date: February 28, 2008Applicants: STMicroelectronics S.R.L., Hynix Semiconductor IncInventors: Rino Micheloni, Luca Crippa, Roberto Ravasio, Federico Pio
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Publication number: 20080049522Abstract: A Content Addressable Memory (CAM) or Ternary CAM (TCAM) provides error detection and correction (EDAC). EDAC codes are chosen based on logical and physical properties of the CAM/TCAM. An entry in the CAM/TCAM comprises a plurality of groups, each group comprising a plurality of storage bits. Writes to the storage bits are encoded to enable EDAC. Lookup data is divided into lookup groups of one or more bits, and is applied to corresponding groups of entries to be searched. In one embodiment, storage bits in a group are first decoded to detect and/or to correct errors and then compared with a lookup group to produce a hit indication. In another embodiment, storage bits in a group are logically combined with a lookup group to produce a hit indication, wherein a correctable error in the storage bits does not affect correctness of the hit indication.Type: ApplicationFiled: August 24, 2006Publication date: February 28, 2008Applicant: Cisco Technology, Inc.Inventor: Earl T. Cohen
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Publication number: 20080049523Abstract: Example embodiments relate to a line defect detection circuit, including a first driver disposed at one end of a line and configured to drive the line using a first voltage or a second voltage in response to a control signal, and a second driver disposed at the other end of the line and configured to drive the line using the second voltage in response to a stress signal.Type: ApplicationFiled: July 13, 2007Publication date: February 28, 2008Inventors: Eunsung Seo, Kye-Hyun Kyung
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Publication number: 20080049524Abstract: A memory cell stores information in the form of a first logic level and a second logic level that are complementary to each other. The memory cell includes a first storage circuit and a second storage circuit for storing the first logic level and the second logic level. The first and second storage circuits each have a respective input and output. An isolation circuit provides electrical isolation of the input of the first storage device from the output of the second storage device, except during access to the first and second storage circuits.Type: ApplicationFiled: August 23, 2007Publication date: February 28, 2008Applicant: STMicroelectronics SAInventors: Gilles Gasiot, Francois Jacquet, Philippe Roche
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Publication number: 20080049525Abstract: In an embodiment, an integrated semiconductor memory includes a plurality of data lines via which data read out or to be read out from memory cells can be communicated, wherein the data lines comprise redundant data lines and non-redundant data lines, wherein the semiconductor memory has at least one data distributor line, and wherein a plurality of redundant data lines are connected up to the at least one data distributor line in such a way that in each case a redundant data line or a group of redundant data lines from the plurality of redundant data lines can be selected and can be connected to the at least one data distributor line.Type: ApplicationFiled: July 25, 2007Publication date: February 28, 2008Inventor: Peter Beer
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Publication number: 20080049526Abstract: A semiconductor memory device includes both a data redundancy memory cell array and a local redundancy memory cell array. Cells of the data redundancy memory cell array and/or cells the local redundancy memory cell arrays may be substituted for one or more defective cells of a normal memory cell array, depending on the number of defects generated in the normal memory cell array. An embodiment of a semiconductor memory device may include a plurality of normal memory blocks, each normal memory block comprising a normal memory cell array and a local redundancy memory cell array, at least one data line redundancy memory block, each data line redundancy memory block comprising a data redundancy memory cell array, and a redundancy controller to substitute columns of the data line redundancy memory cell array for some columns of at least two columns in each normal memory cell array, and to substitute columns of the local redundancy memory cell array for the remaining columns of the at least two columns.Type: ApplicationFiled: July 27, 2007Publication date: February 28, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Han-Gyun JUNG, Seung-Bum KO, Nak-Won HEO
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Publication number: 20080049527Abstract: Disclosed is a method for testing a memory device, which can test a memory cell block while testing another memory cell block, so as to catch a process defect of the memory device within a short time period, thereby reducing the test time. The method for testing a memory device provided with a bank including N memory cell blocks and sense amplifiers, the method comprising the steps of: a) expressing the N memory cell blocks as a first, a second, . . . , an Nth memory cell block; b) sequentially activating odd-numbered memory cell blocks of the N memory cell blocks one by one in a predetermined time period; c) performing sense, read (or write) and precharge operations for each activated memory cell block; and d) performing steps a) to c) for even-numbered memory cell blocks after tests for all the odd-numbered memory cell blocks are finished.Type: ApplicationFiled: October 30, 2007Publication date: February 28, 2008Inventor: Young Shim
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Publication number: 20080049528Abstract: In an embodiment, a bit line sense amplifier of a semiconductor memory device with an open bit line structure includes sense amplifier blocks, first voltage drivers, and a second voltage driver. The sense amplifier blocks include a first sense amplifier and a second sense amplifier, each sensing and amplifying a signal difference between a bit line and a complementary bit line. The first voltage drivers apply a power source voltage to the first sense amplifier, and the second voltage driver applies a ground voltage to the second sense amplifier. The first voltage drivers are disposed for every two or more sense amplifier blocks in a bit line sense amplifier region in which the sense amplifier blocks are arranged, and the second voltage driver is disposed in a conjunction region in which a control circuit is located to control the sense amplifier blocks. Both capacitive noise and device size are minimized.Type: ApplicationFiled: August 6, 2007Publication date: February 28, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyang-Ja YANG, Su-Yeon KIM
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Publication number: 20080049529Abstract: This disclosure concerns a semiconductor memory device comprising memory cells; word lines connected to the gates of the memory cells; bit lines connected to the drains of the plurality of memory cells; sense amplifiers detecting data stored in the memory cells via the bit lines, the sense amplifiers writing data to the memory cells via the bit lines and latching read data or data to be written; and a plurality of transfer gates connecting or disconnecting the sense amplifiers to or from the bit lines, in a period of a serial access for continuously writing the data to the memory cells connected to an activated word line among the word lines, the transfer gates connecting the sense amplifiers to the bit lines corresponding to the sense amplifiers, respectively, after the sense amplifiers corresponding to the memory cells latch the data.Type: ApplicationFiled: August 23, 2007Publication date: February 28, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Takashi Ohsawa
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Publication number: 20080049530Abstract: In a conventional equalizer circuit, in an equalizing operation for setting voltages of a wiring pair having a predetermined voltage difference therebetween to be the same, it takes a long time to make the voltages of the wirings in a pair converge to a voltage having an offset with respect to a midpoint voltage of the voltages of the wiring pair after the equalizing operation. According to an equalizer circuit of the present invention, provided is an equalizer circuit (50) which sets the voltages of a first wiring (SAP) and a second wiring (SAN) to be substantially the same and which has a first transistor (N1) connected between the first wiring (SAP) and a first power supply circuit (for example, HVDD?Va) and a second transistor (N2) connected between the first wiring SAP and the second wiring (SAN). The equalizer circuit 50 makes the first transistor (N1) conductive, and then makes the second transistor (N2) conductive.Type: ApplicationFiled: August 23, 2007Publication date: February 28, 2008Applicant: NEC ELECTRONICS CORPORATIONInventors: Takuya Hirota, Takao Yanagida, Hiroyuki Takahashi
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Publication number: 20080049531Abstract: A memory arrangement and method of operating a memory arrangement is disclosed. In one embodiment of the memory arrangement according to the invention, rewritable memory cells are arranged at crossovers between word lines and bit lines, said memory cells being configured in such a manner that the information stored in them is essentially read out in a nondestructive manner. According to the invention, the memory arrangement has a flag cell either for each word line or for each bit line, said flag cell being able to store an item of information that indicates whether at least one of the memory cells either along the respective word line or along the respective bit line has been subjected to a reading operation since a basic state occurred.Type: ApplicationFiled: October 27, 2004Publication date: February 28, 2008Inventor: Michael Kund
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Publication number: 20080049532Abstract: A semiconductor memory device has a refresh control circuit for switchingly controlling a first refresh mode in which access to the memory cell array from outside is prohibited while retaining data and a second refresh mode in which access to the memory cell array from outside is permitted while retaining data and for performing the refresh operation of the memory cells corresponding to a selected word line, and a designating circuit for individually designating a portion to be refreshed in the first refresh mode and a portion to be refreshed in the second refresh mode. In the semiconductor memory device, the refresh control circuit performs the refresh operation when the portion to which the selected word line belongs is designated to be refreshed, and does not perform the refresh operation when the portion to which the selected word line belongs is not designated to be refreshed.Type: ApplicationFiled: August 21, 2007Publication date: February 28, 2008Applicant: ELPIDA MEMORY, INC.Inventor: Kazuhiko KAJIGAYA
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Publication number: 20080049533Abstract: A supply voltage distribution system for distributing a supply voltage through a semiconductor device, the supply voltage distribution system comprising: a first supply voltage distribution line arrangement and a second supply voltage distribution line arrangement, said first supply voltage distribution line arrangement and said second supply voltage distribution line arrangement being adapted to receive from outside the semiconductor device a semiconductor device supply voltage and to distribute a supply voltage to respective first and second portions of the semiconductor device; a voltage-to-voltage conversion circuit connected to the first supply voltage distribution line arrangement, wherein the voltage-to-voltage conversion circuit is adapted to either transfer onto the first supply voltage distribution line arrangement the semiconductor device supply voltage received from outside the semiconductor device, or to put on the first supply voltage distribution line a converted supply voltage having a value dType: ApplicationFiled: July 27, 2007Publication date: February 28, 2008Inventors: Donghyun Seo, Jaeyong Cha
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Publication number: 20080049534Abstract: A static random access memory (SRAM) comprising a plurality of SRAM cells, a plurality of wordlines(WL0-WLN) and a voltage regulator for driving the wordlines with a wordline voltage signal (VWLP). The wordline voltage signal is determined so as to reduce the likelihood of occurrence of read-disturbances and other memory instabilities. In one embodiment, the wordline voltage signal is determined as a function of the metastability voltage (VMETA) of the SRAM cells and an adjusted most positive down level voltage (VAMPDL) that is a function of a predetermined voltage margin (VM) and a most positive down level voltage (VMPDL) that corresponds to the read-disturb voltage of the SRAM cells.Type: ApplicationFiled: October 25, 2007Publication date: February 28, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Fifield, Harold Pilo
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Publication number: 20080049535Abstract: A comparing unit (12) in a readout control unit (11) compares one bit data stored in a memory body (20) with a value stored in a data storage unit B[m] which is prepared to store the one bit data. The data storage unit B[m] includes three memory cells MC[k] and the stored value of the data storage unit B[m] is obtained by a logical operation unit (16) operable to calculate an exclusive OR with respect to the three memory cells MC[k]. When mismatching is detected in the comparing unit (12), a rewrite cell determination unit (13) determines one of the three memory cells MC[k], to which rewriting of the stored value is performed. In the case where the stored value in the data storage unit B[m], if the data storage unit B[m] has a memory cell MC[k] to which writing can be performed, the writing is performed in priority to erasing.Type: ApplicationFiled: July 14, 2005Publication date: February 28, 2008Inventor: Kozo Nishimura
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Publication number: 20080049536Abstract: A semiconductor memory device comprises a plurality of input/output (I/O) ports, a plurality of memory cell arrays and a region configurator. The region configurator is adapted to hold share region information about at least one share region. In the memory cell arrays, at least one share region accessible through the I/O ports is configured on the basis of the share region information.Type: ApplicationFiled: August 21, 2007Publication date: February 28, 2008Applicant: ELPIDA MEMORY INC.Inventor: Kazuhiko Kajigaya
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Publication number: 20080049537Abstract: The present invention relates to an 1-transistor DRAM cell, a DRAM device and a manufacturing method therefor, a driving circuit for a DRAM, a driving method therefore, and a driving method for an 1-transistor DRAM, and a double-gate type 1-transistor DRAM. The present invention comprises a data hold process biasing a word line at a negative voltage level and biasing a sensing line and a bit line at a first constant voltage level; a data purging process resetting data by biasing the word line and the bottom word line at a second constant voltage level and biasing the sensing line and the bit line at the first constant voltage level; and a data write process biasing the word line and the bottom word line at the second constant voltage level and supplying a write data to the bit line.Type: ApplicationFiled: July 23, 2007Publication date: February 28, 2008Inventor: Hee KANG
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Publication number: 20080049538Abstract: A semiconductor memory device includes: a memory array; an internal address supplying unit configured to produce a first internal address in response to an external address; a first fuse unit configured to includes fuses and anti-fuses integrated; an address switching circuit configured to produce a second internal address on the basis of the first internal address; and a decoder circuit configured to select a memory cell of the memory array in response to the second internal address. The internal address supplying unit is configured to be capable of fixing a specific address bit in the first internal address. The second internal address includes: fuse independent address bits produced from address bits which is not the specific address bit in the first internal address, independently of a state of the first fuse unit, and a fuse dependent address bit having a value corresponding to the state of the first fuse unit and a vale of the specific address bit.Type: ApplicationFiled: July 11, 2007Publication date: February 28, 2008Applicant: NEC Electronics CorporationInventor: Hiroshi Sugawara
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Publication number: 20080049539Abstract: Disclosed is a word line driving circuit which includes a first MOS transistor and a second MOS transistor having mutually different conductivity types and a third MOS transistor of a conductivity type which is the same as that of the first MOS transistor. Gates of the first and second MOS transistors are connected in common for receiving an input signal. Sources of the first and second MOS transistors are connected to a first power supply and a second power supply, respectively. The third MOS transistor is connected between a drain of the first MOS transistor and a drain of the second MOS transistor. A connection node between the drain of the second MOS transistor and a drain of the third MOS transistor is connected to a word line. When the input signal is set to a high level and when the second transistor is turned on, a potential lower than a high level of the input signal is supplied to a gate of the third MOS transistor.Type: ApplicationFiled: July 12, 2007Publication date: February 28, 2008Applicant: NEC ELECTRONICS CORPORATIONInventor: Masaki Miyata
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Publication number: 20080049540Abstract: A semiconductor memory device and a related method are disclosed. The semiconductor memory device includes a data sensing output unit simultaneously providing first and second data to first and second data path lines, respectively; and a data output circuit, wherein the first and second data are serially output to an output terminal through the data output circuit. The device further includes a data transmitter operationally connecting the first data path line to the data output circuit and operationally connecting the second data path line to the data output circuit; and a data path controller connected between the data sensing output unit and the data transmitter, delaying the second data, and including first and second delay elements, wherein each of the first and second delay elements is disposed along one of the first and second data path lines.Type: ApplicationFiled: April 3, 2007Publication date: February 28, 2008Inventor: Woo-Pyo Jeong
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Publication number: 20080049541Abstract: A semiconductor memory device includes an FIFO block connected to a data input/output terminal DQ, a time-division transfer circuit that inputs and outputs in parallel n-bit data inputted and outputted continuously via the data input/output terminal DQ, a data bus RWBS that performs a data transfer between the time-division transfer circuit and the FIFO block, and a mode register that sets a burst length. When a minimum burst length settable to the mode register is m (<n), the time-division transfer circuit performs the data transfer using the data bus in units of m bits irrespective of the burst length. Thereby, it becomes possible to set the burst length smaller than a prefetch number without performing a burst chop.Type: ApplicationFiled: August 27, 2007Publication date: February 28, 2008Applicant: Elpida Memory, Inc.Inventor: Hiroki Fujisawa