Abstract: A method and kit are provided for visualization of a latent pattern of molecular structures on a substrate surface. The method is comprised of exposing the substrate to a solution of nano-particles or to a powder of nano-particles. A detectable change is brought about as a result of non-specific binding nano-particles to the chemical groups on the substrate surface carrying the target molecular structures. The invention also provides compositions and kit for practicing the method. Further, the invention provides methods of capturing image of the substrate surface for visualization and quantitation of the molecular structures.

Abstract: Compounds of methamphetamine derivatives having a meta-substituted alkyl linker on the benzene ring and a protective group on the nitrogen of the methamphetamine hapten. Such compounds have the structure. wherein R1 is an alkyl linker comprising 2-15 carbon atoms and 0-6 heteroatoms, R2 is a leaving group, and R3 is a protecting group.

Abstract: A surface reconstruction method for a silicon carbide substrate (1) includes a silicon film forming step of forming a silicon film (2) on a surface of the silicon carbide substrate (1) and a heat treatment step of heat-treating the silicon carbide substrate (1) and the silicon film (2) without providing a polycrystalline silicon carbide substrate on a surface of the silicon film (2). Here, after the heat treatment step, a silicon film removal step of removing the silicon film (2) may be included. Further, a silicon oxide film forming step of oxidizing the silicon film (2) after the heat treatment step to generate a silicon oxide film, and a silicon oxide film removal step of removing the silicon oxide film may-be included.

Abstract: An encapsulated MEMS process including a high-temperature anti-stiction coating that is stable under processing steps at temperatures over 450 C is described. The coating is applied after device release but before sealing vents in the encapsulation layer. Alternatively, an anti-stiction coating may be applied to released devices directly before encapsulation.

Abstract: A liquid crystal display panel device includes a liquid crystal display panel, a sealing material disposed along a first outer perimeter of the liquid crystal display panel, a barrier wall disposed along a second outer perimeter of the liquid crystal display panel, and a liquid crystal material disposed within the second outer perimeter of the liquid crystal display panel, wherein the first outer perimeter is greater than the second outer perimeter and at least one cavity space is formed between the first and second outer perimeters.

Abstract: An apparatus and method for real-time monitoring process conditions of a semiconductor wafer processing operation. A semiconductor wafer subject to processing in a wafer processing tool is embedded with one or more sensor devices. In response to receipt of wireless electromagnetic signals, the embedded sensor devices are activated for generating sensory data. The electromagnetic signals are further utilized to activate a transmitter device provided in the wafer to wirelessly transmit the sensory data generated from the activated embedded sensor device. The transmitted electromagnetic signals comprising the sensory data are communicated to a control device for controlling processing conditions of the process tool based upon the received sensory data.

Abstract: A charged particle beam irradiation method includes setting an observation region on a sample, the sample including an object pattern to be observed, and the observation region including the object pattern, setting an irradiation region on the sample, the irradiation region being to be irradiated with a charged particle beam, the irradiation region including the observation region and being larger than the observation region, setting a non-irradiation region in the irradiation region, the non-irradiation region failing to be irradiated with the charged particle beam, irradiating the irradiation region except the non-irradiation region with the charged particle beam, and irradiating the observation region with a charged particle beam after the irradiating the irradiation region except the non-irradiation region with the charged particle beam.

Abstract: A trench capacitor structure in which arsenic contamination is substantially reduced and/or essentially eliminated from diffusing into a semiconductor substrate along sidewalls of a trench opening having a high aspect ratio is provided. The present invention also provides a method of fabricating such a trench capacitor structure as well as a method for detecting the arsenic contamination during the drive-in annealing step. The detection of arsenic for product running through the manufacturing lines uses the effect of arsenic enhanced oxidation. That is, the high temperature oxidation anneal used to drive arsenic into the semiconductor substrate is monitored for thickness. For large levels of arsenic outdiffusion, the oxidation rate will increase resulting in a thicker oxide layer. If such an event is detected, the product that has been through the process steps to form the buried plate up to the drive-in anneal, can be reworked to reduce arsenic contamination.

Abstract: A method for manufacturing a semiconductor laser element includes forming a semiconductor laminated structure, having an active layer, on a substrate; etching the semiconductor laminated structure to form a mesa; cleaning the side of the mesa at a temperature lower thank a critical temperature at which an oxide layer forms on the side of the mesa using an etching gas; cleaning the side of the mesa at a temperature higher than the critical temperature using an etching gas; and forming a burying layer coating the side of the mesa after cleaning the side of the mesa.

Abstract: A light-absorbing layer is selectively formed over an insulating surface, an insulating layer is formed over the insulating surface and the light-absorbing layer, the insulating surface, the light-absorbing layer, and the insulating layer are irradiated with laser light to selectively remove only the insulating layer above the light-absorbing layer in an irradiated region of the insulating layer so that an opening reaching the light-absorbing layer is formed in the insulating layer, and a conductive film is formed in the opening so as to be in contact with the light-absorbing layer. By forming the conductive film in the opening so as to be in contact with the exposed light-absorbing layer, the conductive film can be electrically connected to the light-absorbing layer with the insulating layer interposed therebetween.

Abstract: A manufacturing method of a display panel for an LCD includes forming a gate line on a flexible insulation substrate, depositing a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer and forming a data line and a drain electrode on the semiconductor layer and the gate insulating layer. The forming the semiconductor layer may be performed by PECVD at about 100° C. to about 180° C., the gate insulating layer may have a thickness of about 2000 ? to about 5500. The method may further include performing hydrogen plasma treatment on the gate insulating layer after the depositing the gate insulating layer and annealing the substrate having the plurality of thin films after the forming the data line and the drain electrode. The insulation substrate may include PES.

Abstract: In a method of fabricating a display substrate, a photoresist layer pattern is formed on a substrate where a thin film transistor (TFT) is formed, and a transparent conductive layer is formed on the photoresist layer pattern. Then, the transparent conductive layer is patterned by a lift-off method to form a transparent conductive layer pattern while partially removing the photoresist layer pattern.

Abstract: A high-luminance light emitting element is manufactured by a method comprising: forming a light emitting layer on a first surface of a GaP substrate including the first surface and a second surface opposed to the first surface and having an area smaller than the first area, the light emitting layer emitting light of a wavelength ? permitted to pass through the GaP substrate; forming a plurality of side surfaces on the GaP substrate to be respectively aslant by substantially the same angle to become narrower toward the second surface; and forming a plurality of depressions and protrusions as high as 0.1? to 3? on the side surfaces.

Abstract: The present invention relates to a nitride semiconductor laser device provided with a window layer on a light-emitting end face of the resonator which comprises an active layer of nitride semiconductor between the n-type nitride semiconductor layers and the p-type nitride semiconductor layers, in which at least the radiation-emitting end face of said resonator is covered by said window layer comprising monocrystalline nitride of general formula AlxGa1-x-yInyN, where 0?x+y?1, 0?x?1 and 0?y<1, having a wider energy gap than that of the active layer and being formed at a low temperature so as not to damage said active layer.

Abstract: A method for manufacturing a silicon device includes steps of: forming a silicon layer 4a that indicates a second conductivity type on a first surface S1a of a silicon substrate 2a that indicates a first conductivity type; and exposing, after the step, a third surface S3a of the silicon layer 4a for a period of a minimum of 30 minutes and a maximum of 6 hours to an argon-containing atmosphere which is adjusted to temperatures of a minimum of 400° C. and a maximum of 900° C. and pressures of a minimum of 4 MPa and a maximum of 200 MPa.

Abstract: The invention provides a composition that is a dispersion made from a Group III nitride, a solvent system, and a dispersant. The dispersion can be used to prepare Group III nitride thin films on a wide range of substrates, for example, glass, silicon, silicon dioxide, silicon nitride, silicon carbide, aluminum nitride, sapphire, and organic polymers. The particle size of the Group III nitride used for producing the thin films can be controlled by adjusting centrifugation of the dispersion and selecting a desired layer of supernatant. The dispersant can be removed from the thin films by calcination. The Group III nitride can contain a dopant. Doped Group III nitride thin films can emit visible light upon irradiation. Green, red, and yellow light emissions result from irradiating erbium-, europium-, and cerium-doped gallium nitride, respectively.

Abstract: A method for producing a semiconductor device includes the steps of forming a predetermined device in a device layer grown on a semiconductor substrate with a sacrificial layer provided therebetween; and removing the sacrificial layer by etching to separate the semiconductor substrate from the device layer while a supporting substrate is bonded to the side of the device layer, wherein in the step of removing the sacrificial layer, a groove extending from the device layer to the sacrificial layer is formed before the sacrificial layer is removed, and the etching solution is allowed to penetrate to the sacrificial layer through the groove.

Abstract: Methods for a multiple die package for integrated circuits are disclosed. An insulator layer is provided and one or more vias are formed within it. The insulator may be provided without vias, and vias formed later. At least one integrated circuit is provided and electrically coupled to at least one lead of a first leadframe overlying one surface of the insulator. At least one second integrated circuit is provided and electrically coupled to a second leadframe overlying a second surface of the insulator. Electrical connections between the two leadframes and the first and second integrated circuits are made through the insulator at selected locations, by coupling at least one lead of the first and second leadframes one to another. The leads of the first and second leadframe may be physically coupled by a welding process within vias in the insulator. A method for a removable storage card is also described.

Abstract: A plasma conditioning method of improving the adhesion between an integrated circuit chip, having active and passive surfaces, the active surface polymer-coated and having a plurality of electrical coupling members, and an insulating underfill material. The method comprises the steps of positioning a wafer having a plurality of integrated circuits, including the coupling members, in a vacuum chamber of a plasma apparatus so that the polymer-coated surface faces the plasma source. Next, a plasma is initiated; the ion mean free path is controlled so that the ions reach the wafer surface with predetermined energy. The wafer surface is then exposed to the plasma for a length of time sufficient to roughen the polymer surface, clean the polymer surface from organic contamination and improve the surface affinity to adhesion. The adhesion ability of this surface to organic underfill material is thus enhanced.

Abstract: An encapsulated MEMS process including a high-temperature anti-stiction coating that is stable under processing steps at temperatures over 450° C. is described. The coating is applied after device release but before sealing vents in the encapsulation layer. Alternatively, an anti-stiction coating may be applied to released devices directly before encapsulation.

Abstract: In a state of a first semiconductor integrated circuit device on which a first semiconductor integrated circuit board including a first mask ROM and a programmable ROM are mounted, an ultimate program determined by using the programmable ROM is stored in a second ROM of a second semiconductor integrated circuit board which is substantially similar in structure to the first semiconductor integrated circuit board, thereby manufacturing a second semiconductor integrated circuit device as an ultimate product.

Abstract: A semiconductor structure and methods for fabricating the semiconductor structure include a gate electrode located over a channel region within a semiconductor substrate and a spacer layer adjacent the gate electrode. The spacer layer extends vertically above the gate electrode. The semiconductor structure also includes a first stressed layer having a first stress located over the gate electrode and a second stressed layer having a second stress different than the first stress located over the first stressed layer. At least a portion of the first stressed layer is laterally contained by the spacer layer. At least a portion of the second stressed layer is not laterally contained by the spacer layer.

Abstract: In formation of a source/drain region of an NMOS transistor, a gate-directional extension region <41a> of an N+ block region <41> in an N+ block resist film <51> prevents a well region <11> located under the gate-directional extension region <41a> from implantation of an N-type impurity. A high resistance forming region, which is the well region <11> having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode <9>, can be formed as a high resistance forming region <A2> narrower than a conventional high resistance forming region <A1>. Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.

Abstract: Provided is a non-planar transistor with a multi-gate structure that includes a germanium channel region, and a method of manufacturing the same. The non-planar transistor includes a silicon body and a channel region that covers exposed surfaces of the silicon body. The channel region is formed of a germanium layer and includes a first channel region and a second channel region. In order to form the germanium channel region, a mesa type active region is formed on the substrate, and a germanium layer is formed to cover two sidewalls and an upper surface of the active region.

Abstract: Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach, and semiconductor structures formed by the methods. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be interrupted to implant ions that are subsequently transformed into a region that electrically isolates the fin from the substrate. The isolation region is self-aligned with the fin because the mask used to form the damascene-body fin also serves as an implantation mask for the implanted ions. The fin may be supported by the patterned layer during processing that forms the FinFET and, more specifically, the gate of the FinFET. The electrical isolation surrounding the FinFET may also be supplied by a self-aligned process that recesses the substrate about the FinFET and at least partially fills the recess with a dielectric material.

Abstract: There is provided an array substrate of an LCD device including a plurality of gate lines aligned on the substrate, a plurality of data lines crossing the gate lines to form a plurality of pixel regions, a thin film transistor located at the intersection of the gate lines and the data lines, and a pixel electrode located in each pixel region, wherein the array substrate further includes a storage capacitor including a lower storage electrode being across the data line and being in parallel with the gate line on the same layer as the gate line, and a semiconductor layer, being formed by a diffraction pattern, interposed between the lower storage electrode and the pixel electrode.

Abstract: A structure and method of fabrication of a semiconductor device having a stress relief layer under a stress layer in one region of a substrate. In a first example, a stress relief layer is formed over a first region of the substrate (e.g., PFET region) and not over a second region (e.g., NFET region). A stress layer is over the stress relief layer in the first region and over the devices and substrate/silicide in the second region. The NFET transistor performance is enhanced due to the overall tensile stress in the NFET channel while the degradation in the PFET transistor performance is reduced/eliminated due to the inclusion of the stress relief layer. In a second example embodiment, the stress relief layer is formed over the second region, but not the first region and the stress of the stress layer is reversed.

Abstract: A dual stress liner manufacturing method and device is described. Overlapping stress liner layers of opposite effect (e.g., tensile versus compression) may be deposited over portions of the device, and the uppermost overlapping layer may be polished down in a process that uses the bottom overlapping layer as a stopper. An insulating film may be deposited on the stress liner layers before the polishing, and another insulating film may be deposited above the first insulating film after the polishing. Contacts may be formed such that the contacts need only penetrate one stress liner layer to reach a transistor well or gate structure.

Abstract: A method for fabricating a semiconductor device includes the steps of: a) forming an insulating film on a semiconductor substrate; b) forming a first conductive film of a material which does not contain nitrogen on the insulating film; and c) forming a second conductive film of a material containing nitrogen on the first conductive film. The method further includes the step of d) patterning the first conductive film and the second conductive film to form a gate electrode and patterning the insulating film to form a gate insulating film.

Abstract: Methods for removing material from one layer of a semiconductor device structure, such as an etch stop layer beneath a capacitor container, without substantially removing material from an overlying layer that includes the same material, such as a protective or reinforcing lattice over the capacitor container, include employing process parameters in which material may be removed from features, as desired, while a sufficient amount of polymer is formed and deposited on features from which material removal is not desired. Methods for designing suitable processes are also disclosed, as are semiconductor device structures that are formed using such processes.

Abstract: A method of selecting a cathode material and a resistance material for use in a RRAM includes determining the work function of a group of potential resistance materials; determining the work function of a group of potential cathode materials; and selecting a suitable material for the resistance material from the group of potential resistance materials and selecting a suitable material for the cathode material from the group of potential cathode material, wherein the work function of the cathode material is at least 0.2 eV less than the work function of the resistance material.

Abstract: A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact electrically coupling a semiconductor body and a semiconductor substrate of the SOI wafer. The semiconductor body includes a channel region for the access device of one of the vertical memory cells. The body contact, which extends through a buried dielectric layer of the SOI wafer, provides a current leakage path that reduces the impact of floating body effects upon the vertical memory cell. The body contact may be formed by etching a via that extends through the semiconductor body and buried dielectric layer of the SOI wafer and extends into the substrate and partially filling the via with a conductive material that electrically couples the semiconductor body with the substrate.

Abstract: A metal-insulator-metal capacitor includes a first electrode in a first wiring level, a second electrode above the first wiring level and extending into a first portion of the first electrode that surrounds the second electrode, and a dielectric film separating the first electrode from the second electrode.

Abstract: A method of fabricating a compound device includes forming a first gate insulating pattern on a semiconductor substrate including a first region and a second region, forming a second gate insulating layer on the first gate insulating pattern, and after forming the second gate insulating layer, forming a well in the second region of the semiconductor substrate.

Abstract: A method of forming a vertical MOSFET device includes forming a trench within a drift layer substrate, the drift layer comprising a first polarity type, the trench generally defining a well region of a second polarity type opposite the first polarity type. An ohmic contact layer is formed within a bottom surface of the trench, the ohmic contact layer comprising a material of the second polarity type. A layer of the second polarity type is epitaxially grown over the drift layer, sidewall surfaces of the trench, and the ohmic contact layer. A layer of the first polarity type is epitaxially grown over the epitaxially grown layer of the second polarity type so as to refill the trench, and the epitaxially grown layers of the first and second polarity type are planarized so as to expose an upper surface of the drift layer substrate.

Abstract: Semiconductor structures and methods are provided for a semiconductor device (40) employing a superjunction structure (41) and overlying trench (91) with embedded control gate (48). The method comprises, forming (52-6, 52-9) interleaved first (70-1, 70-2, 70-3, 70-4, etc.) and second (74-1, 74-2, 74-3, etc.

Abstract: A method for preparing a memory structure comprises the steps of forming a plurality of line-shaped blocks on a dielectric structure of a substrate, and forming a first etching mask exposing a sidewall of the line-shaped blocks. A portion of the line-shaped blocks is removed incorporating the first etching mask to reduce the width of the line-shaped blocks to form a second etching mask including a plurality of first blocks and second blocks arranged in an interlaced manner. Subsequently, a portion of the dielectric structure not covered by the second etching mask is removed to form a plurality of openings in the dielectric structure, and a conductive plug is formed in each of the openings. The plurality of openings includes first openings positioned between the first blocks and second openings positioned between the second blocks, and the first opening and the second opening extend to opposite sides of an active area.

Abstract: A method of forming a metal-containing gate includes forming a high-k dielectric layer over a substrate. A process using an oxygen-containing solution is provided to process the high-k dielectric layer. A metal-containing layer is formed over the high-k dielectric layer. The high-k dielectric layer and metal-containing layer are patterned, thereby defining a gate structure.

Abstract: The present invention provides a method in which a low-resistance connection between the MOS channel and silicided source/drain regions is provided that has an independence from the extension ion implant process as well as device overlap capacitance. The method of the present invention broadly includes selectively removing outer spacers of an MOS structure and then selectively plating a metallic or intermetallic material on exposed portions of a semiconductor substrate that were previously protected by the outer spacers. The present invention also provides a semiconductor structure that is formed utilizing the method. The semiconductor structure includes a low-resistance connection between the silicided source/drain regions and the channel regions which includes a selectively plated metallic or intermetallic material.

Abstract: The present invention relates to a heterojunction tunneling effect transistor (TFET), which comprises spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region. The drain region comprises a first semiconductor material and is doped with a first dopant species of a first conductivity type. The source region comprises a second, different semiconductor material and is doped with a second dopant species of a second, different conductivity type. The gate stack comprises at least a gate dielectric and a gate conductor. When the heterojunction TFET is an n-channel TFET, the drain region comprises n-doped silicon, while the source region comprises p-doped silicon germanium. When the heterojunction TFET is a p-channel TFET, the drain region comprises p-doped silicon, while the source region comprises n-doped silicon carbide.

Abstract: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

Abstract: A method and resulting electronic device utilizing a periodic multi-layer (ML) and/or superlattice (SL) structures in the base of a SiGe heterojunction bipolar transistor (HBT) is disclosed. The SL is a special case of an ML, in which layers that are chemically different from adjacent neighbors are successively repeated. The use of the ML in electronic and photonic devices is enables strategic engineering of the energy band gap and carrier mobilities. Principles disclosed herein relate to npn- and pnp-type SiGe HBTs as well as HBTs made with other compound semiconductor materials (e.g., other Group III-V or II-VI materials). Additionally, technology and methods disclosed herein benefit other devices types such as, for example, metal oxide semiconductor field effect transistors (MOSFETs), high electron mobility transistors (HEMTs), high hole mobility transistors (HHMTs), bipolar junction transistors (BJTs), and FINFETs.

Abstract: An objective of this invention is to solve the problem that in ALD film deposition using a vertical batch processing machine advantageous for improving a throughput, reliability in a dielectric body formed on the bottom of a hole such as a capacitor formed on a semiconductor substrate is reduced as the hole is finer and deeper. A dielectric body is formed by an ALD film deposition process comprising a gas flow sequence where a purging step after supplying a source and a reactant gases is a two-stage purging of vacuum purging and gas purging and the step of supplying a reactant gas is further divided. The process allows a highly reliable dielectric body to be formed in the bottom of a deep hole, contributing to improvement in reliability of a capacitor and a semiconductor device.

Abstract: There is provided a system and method for fabricating a fin field effect transistor. More specifically, in one embodiment, there is provided a method comprising depositing a layer of nitride on a substrate, applying a photolithographic mask on the layer of nitride to define a location of a wall, etching the layer of nitride to create the wall, removing the photolithographic mask, depositing a spacer layer adjacent to the wall, etching the spacer layer to create a spacer adjacent to the wall, wherein the spacer and the wall cover a first portion of the substrate, and etching a second portion of the substrate not covered by the spacer to create a trench.

Abstract: A method of producing a semiconductor device according to the present invention comprises steps of: (A) forming trenches (13) on the front surface (FS) of a semiconductor substrate (11) on the back surface (BS) of which a nitride film (12b) is formed; (B) depositing an insulating film (15) to bury the trenches (13); (C) removing the nitride film (12b) on the back surface (BS) of the semiconductor substrate (11) after the step (B); and (D) annealing before the insulating film (15) is etched after the step (C).

Abstract: A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed.

Abstract: A method of separating a sheet of coated brittle material comprises the steps of providing a sheet of layered brittle material comprising a brittle layer and a coating material adhered to a surface of the brittle layer and applying a laser along a separation line in the sheet, thereby cutting the coating material and separating the brittle layer by inducing a stress fracture therein.

Abstract: Systems and methods to suppress the formation of parasitic particles during the deposition of a III-V nitride film with, e.g., metal-organic chemical vapor deposition (MOCVD) are described. In accordance with certain aspects of the invention, a hotwall reactor design and methods associated therewith, with wall temperatures similar to process temperatures, so as to create a substantially isothermal reaction chamber, may generally suppress parasitic particle formation and improve deposition performance.

Abstract: A semiconductor structure with an insulating layer on a silicon substrate, a plurality of electrically-isolated silicon-on-insulator (SOI) regions separated from the substrate by the insulating layer, and a plurality of electrically-isolated silicon bulk regions extending through the insulating layer to the substrate. Each of one number of the SOI regions is oriented with a first crystal orientation and each of another number of the SOI regions is oriented with a second crystal orientation that differs from the first crystal orientation. The bulk silicon regions are each oriented with a third crystal orientation. Damascene or imprinting methods of forming the SOI regions and bulk silicon regions are also provided.

Abstract: In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) providing a substrate; and (2) forming a first silicon-on-insulator (SOI) region having a first crystal orientation, a second SOI region having a second crystal orientation and a third SOI region having a third crystal orientation on the substrate. The first, second and third SOI regions are coplanar. Numerous other aspects are provided.