Abstract: Provided are a method of manufacturing a thin film structure, a method of manufacturing a storage node having the same, a method of manufacturing a phase-change random access memory device having the same and a thin film structure, storage node and phase-change random access memory device formed using the same. The method of manufacturing the thin film structure may include the operations of obtaining a seed layer formed of a chalcogenide alloy, by supplying one or two selected from the group consisting of a Group IV-precursor, a Group V-precursor, and a Group VI-precursor to an upper surface of an amorphous material layer, and forming the thin film by supplying a Group IV-precursor, a Group V-precursor, and a Group VI-precursor to an upper surface of the seed layer.

Abstract: A method of manufacturing a display device to improve the quality of a polycrystal silicon upon dehydrogenating and polycrystallizing an amorphous silicon at the outside of a display region of a substrate, by forming a plurality of pixels having TFT devices using an amorphous silicon in the display region of the substrate, and forming a plurality of driving circuits having semiconductor devices using a polycrystal silicon at the outside of the display region, the method including irradiation of a first continuous oscillation laser only to the amorphous silicon in the region for forming the driving circuit and the peripheral region thereof to conduct dehydrogenation and then irradiation of a second continuous oscillation region only to the dehydrogenated region to polycrystallize the amorphous silicon, wherein the region to which the first continuous oscillation laser is irradiated is wider than the region to which the second continuous oscillation laser is irradiated.

Abstract: The invention concerns a monocrystalline coating crack-free coating of gallium nitride or mixed gallium nitride and another metal, on a substrate likely to cause extensive stresses in the coating, said substrate being coated with a buffer layer, wherein: at least a monocrystalline layer of a material having a thickness ranging between 100 and 300 nm, preferably between 200 and 250 nm, and whereof crystal lattice parameter is less than the crystal lattice parameter of the gallium nitride or of the mixed gallium nitride with another metal, is inserted in the coating of gallium nitride or mixed gallium nitride with another metal. The invention also concerns the method for preparing said coating. The invention further concerns electronic and optoelectronic devices comprising said coating.

Abstract: In a manufacturing process of a semiconductor device, a manufacturing technique for reducing the number of lithography processes using a photoresist and simplifying the process is provided, and the throughput is improved. An etching mask for forming a pattern of a layer to be processed such as a conductive layer or a semiconductor layer is manufactured without using a lithography technique that uses a photoresist. The etching mask is formed of a stacked layer structure of a light absorption layer and an insulating layer utilizing laser ablation by laser beam irradiation through a photomask.

Abstract: A silicon layer with high resistance is provided. The silicon layer with high resistance is positioned on a substrate. Also, the silicon layer with high resistance includes a plurality of silicon material layers, and an interface layer between every two of the silicon material layers, wherein, the silicon material layers and the interface layer have dopants therein. The amount of implanted dopants is about 1*1014˜5*1015 ions/cm2, and the silicon material layers have different grain boundaries.

Abstract: A method for doping a multi-gate device is disclosed. In one aspect, the method comprises patterning a fin in a substrate, depositing a gate stack, and doping the fin. The process of doping the fin is done by depositing a blocking mask material at least on the top surface of the fin after the patterning of the gate stack. After the deposition of the blocking mask material dopant ions are implanted whereby the blocking mask material partially or completely blocks the top surface of the fin from these dopant ions.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a workpiece, disposing a gate dielectric material over the workpiece, and disposing a gate material over the gate dielectric material. Cl or F is introduced to the gate material, wherein introducing the Cl or F to the gate material affects a work function of the gate material. The gate material and the gate dielectric material are patterned, forming at least one transistor.

Abstract: A process for manufacturing a semiconductor device having a polymetal structure includes patterning a bottom electrode layer by using a sacrificial layer pattern oxidizing the side surface of the patterned bottom electrode layer, forming a sidewall oxide film on both the patterned bottom electrode layer and the sacrificial layer pattern, removing the sacrificial layer pattern, and forming a top electrode layer on the exposed bottom electrode layer and the side surface of the sidewall oxide film.

Abstract: Methods and apparatus for providing a memory array fabrication process that concurrently forms memory array elements and peripheral circuitry. The invention relates to a method for fabricating memory arrays using a process that concurrently forms memory array elements and peripheral circuitry and results in a reduction in pitch.

Abstract: Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes placing a plurality of first interconnect elements on a side of a semiconductor workpiece, forming a layer on the side of the workpiece, reshaping the first interconnect elements by heating the first interconnect elements, and coupling a first portion of a plurality of individual second interconnect elements to corresponding first interconnect elements with a second portion of the individual second interconnect elements exposed.

Abstract: A method is provided for making a semiconductor device, which comprises (a) providing a semiconductor structure comprising a top gate (228) and a bottom gate (240); (b) creating first (251), second and third (252) openings in the semiconductor structure, wherein the first opening exposes a portion of the bottom gate; (c) filling the first, second and third openings with a conductive material, thereby forming source (258) and drain (260) regions in the second and third openings and a conductive region (253) in the first opening; and (d) forming an electrical contact (278) to the conductive region.

Abstract: Electrically programmable fuse structures and methods of fabrication thereof are presented, wherein a fuse includes first and second terminal portions interconnected by an elongate fuse element. The first terminal portion has a maximum width greater than a maximum width of the fuse element, and the fuse includes a narrowed width region where the first terminal portion and fuse element interface. The narrowed width region extends at least partially into and includes part of the first terminal portion. The width of the first terminal portion in the narrowed region is less than the maximum width of the first terminal portion to enhance current crowding therein. In another implementation, the fuse element includes a restricted width region wherein width of the fuse element is less than the maximum width thereof to enhance current crowding therein, and length of the restricted width region is less than a total length of the fuse element.

Abstract: Methods for attaching microfeature dies to external devices are disclosed. The external devices can include other microfeature dies, support members or other suitable devices. A particular method includes attaching the solder to the at least one of the microfeature die in the support member by changing a phase of the solder. The method can further include contacting the solder with the other of the microfeature die and the support member and urging the microfeature die and the support member toward each other to provide a first bond between the die and the support member via the solder. The method can still further include changing a phase of the solder to provide a second bond between the microfeature die and the support member, with the second bond being stronger than the first bond.

Abstract: A semiconductor device is fabricated by making first and second UBM films on an external terminal, the first under bump metal film having no wettability to a bump electrode and the second UBM film having wettability to the bump electrode; placing the bump electrode on the second UBM film; patterning and side-etching the second UBM film using the bump electrode as a mask; filling a resist in a space defined by the side-etched part of the second UBM film; and patterning the first UBM film using the bump electrode and the resist as a mask.

Abstract: A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.

Abstract: A semiconductor component includes a plastic housing including: plastic outer surfaces; lower outer contact surfaces arranged on an underside of the housing; upper outer contact surfaces arranged on a top side of the housing that is opposite the underside; and outer interconnects electrically connecting the lower outer contact surfaces to the upper outer contact surfaces, the outer interconnects including a layer of solder arranged on conduction paths along an outer contour of the housing.

Abstract: A method of manufacturing a semiconductor device including forming two first gate electrodes along a first direction on a first surface of a semiconductor substrate and source/drain areas sandwiching a channel region under each of the first gate electrodes, forming a first interlayer insulating layer to fill a region between the first gate electrodes, lowering a top of the first interlayer insulating layer, depositing a second interlayer insulating layer on the first interlayer insulating layer and the first gate electrodes, planarizing a surface of the second interlayer insulating layer, and forming an interconnect layer in the second interlayer insulating layer and a contact plug in the first interlayer insulating layer and the second interlayer insulating layer so that the contact plug is in contact with the interconnect layer and one of the source/drain areas.

Abstract: A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.

Abstract: The invention is directed to preparing optical elements having a thin, smooth, dense coating or film thereon, and a method for making such coating or film. The coated element has a surface roughness of <1.0 nm rms. The coating materials include hafnium oxide or a mixture of hafnium oxide and another oxide material, for example silicon dioxide. The method includes the use of a reverse mask to deposit the coating or film on a rotating substrate.

Abstract: Microfeature workpieces having conductive vias formed by chemically reactive processes, and associated systems and methods are disclosed. A method in accordance with one embodiment includes disposing a conductive lining on walls of a via in a microfeature workpiece, so that a space is located between opposing portions of the lining facing toward each other from opposing portions of the wall. The method can further include chemically reacting the lining with a reactive material to form a chemical compound from a constituent of the reactive material and a constituent of the lining. The method can still further include at least partially filling the space with the compound. In particular embodiments, the conductive lining includes copper, the reactive material includes sulfur hexafluoride, and the chemical compound that at least partially fills the space in the via includes copper sulfide.

Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: A method for fabricating a semiconductor device according to the present invention includes: a step for forming a wiring layer on a semiconductor substrate; a step for patterning the wiring layer; and a step for covering the wiring layer with a protective insulating film. Moreover, after the step for forming the wiring layer, all required heat treatment steps to be performed prior to the step for covering the wiring layer with the protective insulating film are performed at a temperature lower than a temperature for plastic deformation of the wiring layer.

Abstract: In the method for manufacturing a semiconductor device relating to the present invention, first, a metal film is formed onto a substrate in the state where a silicide forming region is exposed onto the surface of substrate. Next, thermal processes at pressure higher than atmosphere are conducted to the substrate where the metal film is formed, and a silicide film is formed by reacting silicon contained in the silicide forming region with the metal film. Subsequently, after an unreacted metal film is removed during the thermal process, crystalline phase transition is initiated via the thermal process, and low resistance of the silicide film formed on the substrate is realized. These steps enable the stable formation of the silicide film with low resistance.

Abstract: Methods and an apparatus are disclosed for depositing tantalum metal films in next-generation solvent fluids on substrates and/or deposition surfaces useful, e.g., as metal seed layers. Deposition involves low valence oxidation state metal precursors soluble in liquid and/or compressible solvent fluids at liquid, near-critical, or supercritical conditions for the mixed precursor solutions. Metal film deposition is effected via thermal and/or photolytic activation of the metal precursors. The invention finds application in fabrication and processing of semiconductor, metal, polymer, ceramic, and like substrates or composites.

Abstract: A method of manufacturing a semiconductor device improves the cleaning efficiency by increasing a cleaning time and temperature, including a copper Chemical Mechanical Planarization process for a semiconductor wafer with a copper line. The method includes a main Cu CMP process to chemically and mechanically polish a surface of the semiconductor wafer. A touch-up CMP process chemically and mechanically polishes a barrier metal exposed on the surface of semiconductor wafer and a lower insulation film positioned below the barrier metal. A CMP cleaning process to remove defects occurring in the main Cu CMP process and the touch-up CMP process by supplying a chemical cleaner to the surface of semiconductor wafer.

Abstract: The disclosure relates to a method for producing a microelectronic device comprising one or more Si1-zGez-based semiconductor wire(s) (with 0<z?1), including the steps of: a) thermal oxidation of at least a portion of a Si1-xGex-based semiconductor layer (with 0<x<1) resting on a support, so as to form at least one Si1-yGey-based semiconductor zone (with 0<y<1 and x<y), b) lateral thermal oxidation of the sides of the second Si1-yGey-based semiconductor zone so as to reduce the second zone in at least one direction parallel to the main plane of the support and to form one or more Si1-zGez-based semiconductor wire(s) (with 0<y<1 and y<z).

Abstract: A method for patterning high aspect ratio vias is provided. More specifically a dry etching method is provided for patterning deep vias or vias with high aspects ratios thereby eliminating the hard mask undercut. A method is provided to create (pattern) deep vias in a substrate for use in three dimensional stacked semiconductor devices and/or structures. More specifically, a method is provided for patterning deep vias with an aspect ratio up to 10 into a Si substrate with smooth via sidewalls and sufficient slope to enable metallization.

Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present invention includes: forming a first insulating film on a semiconductor substrate; forming a mask with an opening of a predetermined pattern in the first insulating film; performing anisotropic etching on the semiconductor substrate with the mask used as an etching mask to form a trench; forming a second insulating film on a surface of an inner wall of the trench with the mask used as a selective oxidation mask; removing the mask; forming a conductive film on the semiconductor substrate to fill the trench with the conductive film; and etching back the conductive film until at least a surface of the semiconductor substrate is exposed.

Abstract: A first layer is formed over a substrate, a light absorbing layer is formed over the first layer, and a layer having a light-transmitting property is formed over the light absorbing layer. The light absorbing layer is selectively irradiated with a laser beam via the layer having a light-transmitting property. When the light absorbing layer absorbs energy of the laser beam, due to emission of gas that is within the light absorbing layer, or sublimation, evaporation, or the like of the light absorbing layer, a part of the light absorbing layer and a part of the layer having a light-transmitting property in contact with the light absorbing layer are removed. By using the remaining part of the layer having a light-transmitting property or the remaining part of the light absorbing layer as a mask and etching the first layer, the first layer can be processed into a desired shape.

Abstract: A chamber dry cleaning process particularly useful after a dielectric plasma etch process which exposes an underlying copper metallization. After the dielectric etch process, the production wafer is removed from the chamber and a cleaning gas is excited into a plasma to clean the chamber walls and recover the dielectric etching characteristic of the chamber. Preferably, the cleaning gas is reducing such as hydrogen gas with the addition of nitrogen gas. Alternatively, the cleaning gas may an oxidizing gas. If the wafer pedestal is vacant during the cleaning, it is not electrically biased. If a dummy wafer is placed on the pedestal during cleaning, the pedestal is biased. The cleaning process is advantageously performed every wafer cycle.

Abstract: A method for etching a bevel edge of a substrate is provided. A patterned photoresist mask is formed over the etch layer. The bevel edge is cleaned comprising providing a cleaning gas comprising at least one of a CO2, CO, CxHy, H2, NH3, CxHyFz and a combination thereof, forming a cleaning plasma from the cleaning gas, and exposing the bevel edge to the cleaning plasma. Features are etched into the etch layer through the photoresist features and the photoresist mask is removed.

Abstract: Object A substrate processing apparatus is provided, which comprises a processing vessel adapted to provide a process to a substrate, an ambient atmospheric carrying chamber, and a functional module located on a carrying route of the substrate to be carried by a carrying means in the ambient atmospheric carrying chamber, wherein bad effect on the functional module due to particles and/or corrosive gases to be generated due to contact of the ambient air with the substrate after having been processed can be avoided. solution The substrate processing apparatus, adapted to provide a process, such as etching, to a wafer, comprises the processing vessel, the ambient atmospheric carrying chamber, and the functional module, such as an orienter 4. With the process to be provided, matters having potential to generate corrosive gases or the like due to contact with the ambient air are attached to the wafer. In the ambient atmospheric carrying chamber, a first air stream creating means 15a, 15b, 15c is provided.

Abstract: A photoresist processing method includes treating a substrate with a sulfur-containing substance. A positive-tone photoresist is applied on and in contact with the treated substrate. The method includes selectively exposing a portion of the photoresist to actinic energy and developing the photoresist to remove the exposed portion and to form a photoresist pattern on the substrate. The treating with a sulfur-containing substance reduces an amount of residual photoresist intended for removal compared to an amount of residual photoresist that remains without the treating.

Abstract: In dry etching an insulating film containing silicon and carbon and formed on a wafer, plasma is generated from a mixed gas of a first molecule gas containing carbon and fluorine and a second molecule gas containing nitrogen. At this time, an RF bias of 2 MHz or lower is applied to an electrode on which the wafer is placed.

Abstract: A variable temperature and/or reactant dose atomic layer deposition (VTD-ALD) process modulates ALD reactor conditions (e.g., temperature, flow rates, etc.) during growth of a film (e.g., metallic) on a wafer to produce different film properties a different film depths.

Abstract: Some embodiments include methods of forming dielectric materials associated with semiconductor constructions. A semiconductor substrate surface having two different compositions may be exposed to a first silanol, then to organoaluminum to form a monolayer, and finally to a second silanol to form a dielectric material containing aluminum from the organoaluminum together with silicon and oxygen from the second silanol. Alternatively, or additionally, an organoaluminum monolayer may be formed across a semiconductor substrate, and then exposed to silanol within a deposition chamber, with the silanol being provided in two doses. Initially, a first dose of the silanol is injected the chamber, and then the first dose is flushed from the chamber to remove substantially all unreacted silanol from within the chamber. Subsequently, the second dose of silanol is injected into the chamber. Some embodiments include semiconductor constructions.

Abstract: A method of depositing layers on a plurality of semiconductor substrates simultaneously, comprising the steps: cleaning of at least one respective surface of the substrates in a first reactor at a first substrate temperature Tred, transport of the substrates from the first reactor into a second reactor, and subsequent deposition of at least one respective layer on the semiconductor substrates in the second reactor at a second substrate temperature Tdep, wherein the semiconductor substrates are moved or stored during the cleaning step and during transport from the first reactor into the second reactor in an interruption-free manner in a reducing gas atmosphere as long as the substrate temperature is above a critical temperature Tc which is dependent on the substrate material and the material of the at least one layer to be deposited.

Abstract: A method of forming an insulating film according to one embodiment of the present invention, which is a method of forming an insulating film for use in a semiconductor device, performs thermal oxidation of a tantalum nitride film at a temperature range of 200 to 400 degrees centigrade by a wet oxidation process, whereby a tantalum oxide film is formed as the insulating film.

Abstract: A silicon-on-insulator (SOI) device and structure having locally strained regions in the silicon active layer formed by increasing the thickness of underlying regions of a buried insulating layer separating the silicon active layer from the substrate. The stress transferred from the underlying thickened regions of the insulating layer to the overlying strained regions increases carrier mobility in these confined regions of the active layer. Devices formed in and on the silicon active layer may benefit from the increased carrier mobility in the spaced-apart strained regions.

Abstract: The present invention generally provides an apparatus and method for reducing defects on films deposited on semiconductor substrates. One embodiment of the present invention provides a method for depositing a film on a substrate. The method comprises treating the substrate with a first plasma configured to reduce pre-existing defects on the substrate, and depositing a film comprising silicon and carbon on the substrate by applying a second plasma generated from at least one precursor and at least one reactant gas.

Abstract: In a method for manufacturing a semiconductor device, including forming an insulator film including a material having Si—CH3 bond and Si—OH bond, and irradiating the insulator film with ultraviolet rays, the rate of decrease of C concentration by X-ray photoelectron spectroscopy is not more than 30%, and the rate of decrease of one or more bonds selected from the group consisting of C—H bond, O—H bond and Si—O bond of Si—OH is not less than 10%, as a result of ultraviolet ray irradiation. A low-dielectric-constant insulator film that has a high film strength and can prevent increase of dielectric constant due to moisture absorption, a semiconductor device that can prevent device response speed delay and reliability decrease due to parasite capacity increase, and a manufacturing method therefor are provided.

Abstract: An electrical connection element for providing an electrical connection to a porous material may include a first electrically conductive plate disposed on at least a portion of a first side of the porous material. A second electrically conductive plate may be disposed on at least a portion of a second side of the porous material, opposite to the first side. An electrically conductive material may impregnate the porous material in a region between the first and second electrically conductive plates, and an electrical connector may be attached to at least one of the first and second electrically conductive plates.

Abstract: On a holder (8) to be mounted on a vehicle body (b), there are formed a connector-holding portion (12a) for holding thereon a female connector (5) and a male connector (4) fitted in the female connector (5); and a cap-holding portion (12b) for holding thereon a female cap (84) and a male cap (81) that can be mounted on the male connector (4) and the female connector (5) respectively, with the male cap (81) fit in the female cap (84).

Abstract: A housing for a CATV filter includes an outer sleeve which is preferably made of stainless steel. A filter assembly and two headers are contained within the outer sleeve. Two engagement holes for a special pin spanner-type wrench are formed in a face of the outer sleeve instead of in a header. The engagement holes are preferably “drifted” holes, which in effect means that rims are created during the forming of holes which add to the strength of the holes.

Abstract: A sliding member is disposed on one wing of the concave portion to advance and retreat in directions parallel to insertion and ejection of a card, and formed a heart-shaped cam groove. The base-end side of the leaf spring is fastened to the sliding member; the other end projects toward the opening of the concave portion. A compressed-coil spring applies a biasing force on the sliding member in a direction of card ejection. One end of the guide rod is coupled to the heart-shaped cam groove; the other end is pivotably supported on the housing. The sliding member has an engaging piece that touches an oblique side formed on a side surface of the card, and the leaf spring has a semi-circular claw that moves in and out of a surface of the card at a substantially square concave portion, thereby resiliently engaging the concave portion.

Abstract: The invention concerns the use of an AMB component (25) in a memory installation with fully buffered Dimm memory modules connected in series, characterised in that the AMB component (25) is placed on a connecting line (30) from the memory modules (2) to a memory controller (1) of the installation in order to re-amplify the connecting line (30) between two consecutive FBD memory modules (21, 22). The invention also concerns a connection interface that includes such an AMB amplifier component (25) for the connection of a maincard (3) that includes at least one processor, to an auxiliary memory card of the type with a series of memory modules (2), where the maincard has at least one pair of channels connected to the processor. Two series of FBD memory modules (2) are connected to respective FBD channels in the auxiliary memory card using FBD connectors (200) in a daisy-chain arrangement.

Abstract: An electrical connector (1) includes an insulative housing (10) and a plurality of stamped contacts (12) resided therewithin. The conductive contact includes a central spring beam (122), a side spring beam (124) located at one side of the central spring beam, and a contact portion (121) formed between the central spring beam and the side spring beam for electrically mating with a mating component. The central spring beam extends inwardly of the contact portion and towards an end portion of the side spring beam. Such a configuration of the central spring beam will ensure that the conductive contact has a predetermined robustness thereof while possessing the required spring properties for the stamped contact.

Abstract: Disclosed an electrical connector (500) comprises an insulative housing (510) having a body (511) with a mating interface (512) and a mounting surface (513) opposite to the mating interface. A plurality of passageways (514) extend from the mating interface toward the mounting surface and with a first wall (516) and a second wall (517) opposite to each other. A plurality of conductive contacts (520) moveably arranged in the corresponding passageways. Each contact includes a base (521) retained in the passageway, and a upper contacting portion (522) extends from one side of the base in a direction toward the mating interface and a lower contacting portion (523) extends from another side of the base. The first free end (527) of the upper contacting portion abuts against the first wall of the passageway to prevent the contact from falling out of the passageway.

Abstract: An electrical connector adapted for connecting a camera module to a printed circuit board via a flexible printed circuit comprises a shield and a spring plate. The shield includes a pair of opposite rear and front walls, a pair of left and right walls adjacent to the rear and front walls, and a flat bottom wall connecting the walls together to enclose a cavity for receiving the camera module. The spring plate is mounted on the bottom wall of the shell and has a main portion and a number of elastic arms extending outward from the two opposite sides of the main portion. Each of the front and rear wall of the shield includes an upright base extending upwardly from the bottom wall, a retaining section extending upwardly from the center of the upright base, and a pair of fastening sections extending from both sides of the retaining section and bending toward the receiving cavity.