Abstract: Chip arrangement and method for producing a chip arrangement A chip arrangement comprises a first chip with an electrically operable structure on an active surface of the first chip. The first chip is applied on a carrier area in order to make electrical contact with the electrically operable structure via the carrier area. A second chip has a cutout and is arranged on the carrier area, the first chip being arranged in a cavity formed by the cutout and the carrier area.

Abstract: Systems and methods for assembling microelectronic devices that have a base die and a conventional wire-bond die stacked on the base die. In one embodiment of a method in accordance with the invention, a base die is placed on a substrate and then a first stacked die is subsequently stacked on the base die. The first stacked die is stacked on the base die in a single pass through a die attach machine without first storing or otherwise processing the base die/substrate assembly in a separate machine. The stacked die, moreover, can be stacked onto the base die before heating the base die to reflow a solder or otherwise attach the base die to the substrate. After stacking the first stacked die on the base die, the complete die assembly can be heated to (a) secure the base die to the substrate, and (b) secure the first stacked die to the base die.

Abstract: A method and structure are provided for implementing component placement suspended within electrical pin grid array packages for enhanced electrical performance. A solder column grid array is coupled between a printed circuit board and a first level package. A component is connected between a predefined pair of adjacent columns in the solder column grid array suspended between the printed circuit board and the first level package.

Abstract: Disclosed herein is a semiconductor device including: an insulating film configured to be provided on a substrate and be porosified through decomposition and removal of a pore-forming material; a covering insulating film configured to be provided on the insulating film; and conductive layer patterns configured to be provided in the covering insulating film and the insulating film and reach the substrate, wherein the insulating film includes a non-porous region in which the pore-forming material remains.

Abstract: A semiconductor package provides a ball grid array, BGA, formed on a package substrate. The apices of the solder balls of the BGA are all at the same height, even if the package substrate is non-planar. Different solder ball pad sizes are used and tailored to compensate for non-planarity of the package substrate that may result from thermal warpage. Larger size solder ball pads are formed at relatively-high locations on the package substrate. An equal amount of solder is formed on each of the solder ball pads to produce solder balls having different heights.

Abstract: A semiconductor package includes a semiconductor chip operatively attached to a conductive lead of a film circuit substrate by an indium-containing solder material and a silver-containing bump electrode, where the solder material is interposed between the conductive lead and the bump electrode.

Abstract: A semiconductor chip includes a silicon substrate, a first dielectric layer over said silicon substrate, a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, a passivation layer over said metallization structure and over said first and second dielectric layers, an opening in said passivation layer exposing a pad of said metallization structure, a polymer bump over said passivation layer, wherein said polymer bump has a thickness of between 5 and 25 micrometers, an adhesion/barrier layer on said pad exposed by said opening, over said passivation layer and on a top surface and a portion of sidewall(s) of said polymer bump, a seed layer on said adhesion/barrier layer; and a third metal layer on said seed layer.

Abstract: An electronic device includes bump electrodes that are formed of an elemental metal having a low melting point and electrically bond a first component and a second component and protective layers that are formed at least on sides of the bump electrodes and prevent penetration of a substance that deteriorates a characteristic of the bump electrodes.

Abstract: A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.

Abstract: A package structure with an area bump has at least a chip (also known as a die), a redistribution layer, a plurality of first bumps (normal bumps) and at least a second bump (area bump). The redistribution layer may reroute and integrate the bonding pads of the chip and incorporate the passive components therein.

Abstract: A wafer level chip scale package (WLCSP) includes a packaged semiconductor device with a plurality of solder bump pads, patterned passivation regions above each of the solder bump pads, a patterned under bump metallization (UBM) region on each of the solder bump pads and the passivation regions, a polyimide region over a portion of the UBM regions and the passivation regions, solder bumps formed on each of the UBM regions, and encapsulation material surrounding the semiconductor die except for at least a portion of each of the solder bumps.

Abstract: Provided is a printed circuit board having a bump interconnection structure that improves reliability between interconnection layers. Also provided is a method of fabricating the printed circuit board and semiconductor package using the printed circuit board. According to one embodiment, the printed circuit board includes a plurality of bumps formed on a resin layer between a first interconnection layer and a second interconnection layer. The second interconnection layer includes insertion holes corresponding to upper portions of the bumps so that the upper portions of the bumps protrude from the second interconnection layer. The upper portion of at least one of the bumps includes a rivet portion having a diameter greater that the diameter of the corresponding insertion hole to reliably interconnect the first and second interconnection layers.

Abstract: The semiconductor apparatus includes: a conductor section provided on a surface of a semiconductor chip so as to input and output an electric signal; and an external connection terminal provided on the surface of the conductor section so as to joint the conductor section to a package substrate, wherein the conductor section has a through hole provided on the surface of the conductor section and piercing a center of the surface of the conductor section, and the external connection terminal is formed along the through hole. As a result, it is possible to realize a semiconductor apparatus whose resistance against repetitive stresses and impulse is improved and which has high packaging reliability.

Abstract: In a semiconductor device including: an insulating film (6) formed over a substrate (1); a buried metal interconnect (10) formed in the insulating film (6); and a barrier metal film (A1) formed between the insulating film (6) and the metal interconnect (10), the barrier metal film (A1) includes a metal oxide film (7), a metal compound film (8) and a metal film (9) stacked in this order from a side in which the insulating film (6) exists to a side in which the metal interconnect (10) exists. Elastic modulus of the metal compound film (8) is larger than that of the metal oxide film (7).

Abstract: A semiconductor device including a fluorine diffusion barrier layer and a method for manufacturing the same are provided. The semiconductor device includes a specific pattern formed over a semiconductor substrate, a fluorine diffusion barrier layer formed over the specific pattern, and an interlayer insulating layer containing fluorine formed over the fluorine diffusion barrier layer. The fluorine diffusion barrier layer may be used to essentially prevent fluorine from being diffused into a specific pattern formed of a metal or tetra-ethyl-ortho-silicate (TEOS) layer and thus to prevent corrosion and void formation that might otherwise be caused by HF.

Abstract: In one aspect of the invention, a method of manufacturing a semiconductor device may include providing a first dielectric layer, providing a trench in the first dielectric layer and a wiring layer which has a Cu in the trench, providing a cap layer on a top surface of the wiring layer, the cap layer being conductive and having a Co, and providing a Cu silicide nitride layer on a part of the top surface of the wiring layer, on which the cap layer is not provided.

Abstract: A method for manufacturing a semiconductor device includes: the first step of forming, in an insulating film provided on a substrate, a recess that is porositized at least at inner walls; the second step of forming an alloy layer made of copper and a metal other than copper so as to cover the inner walls of the recess; the third step of burying a conductive layer made primarily of copper in the recess provided with the alloy layer; the fourth step of subjecting the thus treated substrate to thermal treatment to cause the metal in the alloy layer to react with a constituent component of the insulating film to form a barrier film made of a metal compound having Cu diffusion barrier properties.

Abstract: An example embodiment provides a method of forming a conductive pattern in a semiconductor device. The method includes forming one or more dielectric layers over a first conductive pattern formed on a substrate; forming an opening in the one or more dielectric layers to expose a portion of the first conductive pattern, forming a growth promoting layer over the exposed portion of the first conductive pattern and the one or more dielectric layers, forming a growth inhibiting layer over a portion of the growth promoting layer, and forming the second conductive layer in the opening.

Abstract: A method is provided for electroforming metal integrated circuit structures. The method comprises: forming an opening such as a via or line through an interlevel insulator, exposing a substrate surface; forming a base layer overlying the interlevel insulator and substrate surface; forming a strike layer overlying the base layer; forming a top layer overlying the strike layer; selectively etching to remove the top layer overlying the substrate surface, exposing a strike layer surface; and, electroforming a metal structure overlying the strike layer surface. The electroformed metal structure is deposited using an electroplating or electroless deposition process. Typically, the metal is Cu, Au, Ir, Ru, Rh, Pd, Os, Pt, or Ag. The base, strike, and top layers can be deposited using physical vapor deposition (PVD), evaporation, reactive sputtering, or metal organic chemical vapor deposition (MOCVD).

Abstract: The present invention provides a semiconductor device which is capable of enhancing adhesion at an interface between a wire-protection film and copper, suppressing dispersion of copper at the interface to avoid electromigration and stress-inducing voids, and having a highly reliable wire. An interlayer insulating film, and a first etching-stopper film are formed on a semiconductor substrate on which a semiconductor device is fabricated. A first alloy-wire covered with a first barrier metal film is formed on the first etching-stopper film by a damascene process. The first alloy-wire is covered at an upper surface thereof with a first wire-protection film. The first wire-protection film covering an upper surface of the first alloy-wire contains at least one metal among metals contained in the first alloy-wire.

Abstract: A semiconductor device according to an embodiment includes a first metal wiring formed on a semiconductor substrate; a first dielectric barrier layer formed on the first metal wiring; an inter-layer dielectric (ILD) layer formed on the first dielectric barrier layer; a plurality of second metal wirings formed on the ILD layer; and at least one hole formed in the ILD layer in regions between second metal wirings.

Abstract: A method of depositing a ruthenium(Ru) thin film on a substrate in a reaction chamber, includes: (i) supplying a gas of a ruthenium precursor into the reaction chamber so that the gas of the ruthenium precursor is adsorbed onto the substrate, wherein the ruthenium precursor a ruthenium complex contains a non-cyclic dienyl; (ii) supplying an excited reducing gas into the reaction chamber to activate the ruthenium precursor adsorbed onto the substrate; and (iii) repeating steps (i) and (ii), thereby forming a ruthenium thin film on the substrate.

Abstract: A metal wiring and method for forming the same are provided. A first conductive layer is formed on a semiconductor substrate, and an insulating layer is formed on the first conductive layer. A via and a trench are formed in the insulating layer, and a second conductive layer is formed by burying metal in the via and the trench.

Abstract: A semiconductor device and a fabricating method thereof are provided. A PMD layer and at least one IMD layer are formed on a semiconductor substrate. A through-electrode penetrates through the PMD layer and the IMD layer, and a connecting electrode connects to the through-electrode.

Abstract: In embodiments, when forming a metal line of the semiconductor device, a developer having an amine group may coated on the metal line layer such that the amine group remains on a surface of the metal line layer. Further, a method of fabricating a semiconductor device may include forming a metal line layer for interlayer connection of the semiconductor device, performing a first photo process by coating a first photoresist on the metal line layer, after performing the first photo process, removing the first photoresist for a rework, after removing the first photoresist, coating a developer having an amine group on the metal line layer, after coating the developer, coating a second photoresist on the metal line layer, and performing a photo process by employing the second photoresist.

Abstract: A circuitized substrate with a conductive layer which assures enhanced adhesion of the layer to selected dielectric layers used to form the circuitized substrate. The conductive layer includes at least one surface with the appropriate roughness to enable such adhesion and also good signal passage if the layer is used as a signal layer.

Abstract: A method for forming device features with reduced line end shortening (LES) includes trimming the device feature to achieve the desired sub-ground rule critical dimension during the etch to form the device feature.

Abstract: A semiconductor device and fabricating method thereof are disclosed. An adhesive layer is provided between a metal layer and a dielectric barrier layer. A dielectric layer having a low dielectric constant is formed on the dielectric barrier layer.

Abstract: A semiconductor device includes a semiconductor substrate having an internal circuit; an electrode pad electrically connected to the internal circuit; an insulating film having a through hole exposing the electrode pad; and a re-distribution wiring pattern formed on the insulating film and electrically connected to the electrode pad. The semiconductor device further includes a recess groove formed in the insulating film around and adjacent to the re-distribution wiring pattern.

Abstract: A semiconductor device includes a lower layer having an uneven region on a top surface, a dielectric barrier layer disposed on the lower layer and having an even top surface, and an interlayer dielectric layer disposed on the dielectric barrier layer and having an even top surface.

Abstract: A semiconductor structure is provided which eliminates the contact resistance traditionally associated with a junction between one or more contacts and a buried conductive structure formed in the semiconductor structure. The semiconductor structure includes a first insulating layer formed on a semiconductor layer and a conductive structure formed on at least a portion of the first insulating layer. A second insulating layer is formed on at least a portion of the conductive stricture. At least one contact is formed through the second insulating layer and electrically connected to the conductive structure. The contact and the conductive structure are formed as a substantially homogeneous structure in a same processing step.

Abstract: A semiconductor package is disclosed including a first capture pad isolated from an adjacent second capture pad by an insulator; a first plurality of electrically active vias connecting the first capture pad to the second capture pad; a third capture pad isolated from the second capture pad by an insulator; and a second plurality of electrically active vias connecting the second capture pad to the third capture pad. Each via of the first plurality of active vias is non-aligned with each via of the second plurality of active vias. The structure provides reduction of strain on the vias when a shear force is applied to a ball grid array used therewith while minimizing the degradation of the electrical signals.

Abstract: A semiconductor device structure includes staggered contacts to facilitate small pitches between active-device regions and conductive lines while minimizing one or both of misalignment during fabrication of the contacts and contact resistance between sections of the contacts. The contacts of one row communicate with every other active-device region and are staggered relative to the contacts of another row, which communicate with the remaining active-device regions. Each contact may include a relatively large contact plug with a relatively large upper surface to provide a relatively large amount of tolerance as a contact hole for an upper portion of the contact is formed. The contact holes may be formed substantially simultaneously with trenches for conductive traces, such as bit lines, in a dual damascene process. Intermediate structures are also disclosed, as are methods for designing semiconductor device structures.

Abstract: A method for protecting an alignment mark on a semiconductor substrate, includes forming a dielectric layer on the semiconductor substrate having the alignment mark, forming a cap oxide film on the dielectric layer, wherein the cap oxide film is formed to have a regular thickness and an additional thickness, etching a portion of the dielectric layer and the cap oxide film to expose the semiconductor substrate to thereby form a via hole, filling the via hole with a metal, and performing a chemical mechanical polishing process with the metal and the cap oxide film to form a via contact.

Abstract: A semiconductor device includes a semiconductor device formed with at least two holes to which devices can be inserted; a plurality of devices inserted into the holes of the semiconductor substrate; connecting electrodes electrically connecting the plurality of devices; and a pad part connecting signals between the plurality of connected devices and to external devices.

Abstract: A method for manufacturing a package which includes: an etching step of etching a silicon substrate, and forming a via hole penetrating through the silicon substrate; and a step of embedding an electrically conductive material in the via hole, and forming a via plug, characterized in that the etching step includes a first etching step of forming the via hole in a straight shape, and a second etching step of forming the via hole in a taper shape.

Abstract: In a first aspect, a first method of manufacturing a dielectric material with a reduced dielectric constant is provided. The first method includes the steps of (1) forming a dielectric material layer including a trench on a substrate; and (2) forming a cladding region in the dielectric material layer by forming a plurality of air gaps in the dielectric material layer along at least one of a sidewall and a bottom of the trench so as to reduce an effective dielectric constant of the dielectric material. Numerous other aspects are provided.

Abstract: An integrated circuit interconnection system is disclosed. The system can include a first integrated circuit die having a first electrode configuration and a second integrated die having the same or a substantially similar electrode configuration. The system can also include a multilayer flexible cable having a first side and a second side that has substantially parallel conductors running along the cable. At least a portion of one of the parallel conductors can be exposed on the first side and/or the second side, such that the first and second integrated circuit die can be connected to both the first side and the second side of the multilayer flexible cable. The cable can be folded to provide a dense interconnect for stacked memory configurations.

Abstract: Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be formed in one or more memory cell dice. The associated circuitry of the device may also be formed in one or more dice, optionally separated from the memory cell dice.

Abstract: The present disclosure relates to an improved integrated circuit package with a encapsulant retention structure located adjacent to a packaged integrated chip on a substrate. The structure allows for the placement and retention of a larger quantity of encapsulant to seep under the packaged integrated chip. The retention wall placed on the substrate alternatively serves as substrate stiffener able to maintain mechanical properties to be used with a more desirable thinner substrate. In one embodiment, the use of openings and recesses in a stiffener layer of an integrated circuit package houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units.

Abstract: A semiconductor device according to the present invention includes a substrate including a plurality of first pads thereon; at least one semiconductor chip including a plurality of second pads; and at least one wiring chip including a plurality of third pads. A part of the plurality of second pads of the semiconductor chip is electrically connected to a part of the plurality of third pads of the wiring chip, and another part of the plurality of third pads of the wiring chip is electrically connected to a part of the plurality of first pads of the substrate.

Abstract: A semiconductor device may include a metal wiring formed on a substrate; a Ti film formed on the metal wiring; a TiN film formed on the Ti film; and an ultra-fine Ti film formed on the TiN.

Abstract: A stackable die mounting system with an efficient interconnect is disclosed that can have a base chip carrier to interconnect a base integrated circuit die to a circuit board on a first side and to a second stacked integrated circuit on a second side. The second side can include a first region having a pad out configuration of a first input output (I/O) to transmit data to be stored by the stacked integrated circuit die. The base chip carrier can have a second region with a pad out of a second I/O that is configured to receive data transmitted by the stacked integrated circuit die wherein the pad out of the second port is translated and rotated about an axis from the pad out of the first region such that a busses with different functions can be vertically integrated from the circuit board.

Abstract: An IC package mainly includes a substrate having slot(s), a chip, a protective encapsulant, a stiffening encapsulant, and a plurality of external terminals. The Young's modulus of the stiffening encapsulant is greater than the one of the protective encapsulant and the curing shrinkage of the stiffening encapsulant is smaller than the one of the protective encapsulant. The protective encapsulant is formed on one of the surfaces of the substrate for encapsulating the chip. The stiffening encapsulant protrudes from the other surface of the substrate where the external terminals are disposed. Moreover, the stiffening encapsulant is formed inside the slot and is contacted with the chip. Since the stiffening encapsulant is embedded and formed inside the slot, therefore, the contact area of the stiffening encapsulant with the substrate is increased to enhance the warpage resistance of the IC package.

Abstract: A functional device in which the functional portion is not influenced by events in film forming, and thereby the reliability of the device can be improved is provided. The functional device includes a substrate, one or a plurality of functional portions formed on a surface of the substrate, a sealing layer that forms a space around the functional portion, and has one or a plurality of apertures sealed with a filling material, and one or a plurality of walls formed between the functional portion and the aperture without separating the space.

Abstract: The invention provides a semiconductor device that is thermally isolated from the printed circuit board such that the device operates at a higher temperature and radiates heat away from the printed circuit board. In another embodiment, the semiconductor is stacked onto a second device and optionally thermally isolated from the second device.

Abstract: A chamber-to-reservoir vented humidification system in which the reservoir is an inverted water bottle elevated above the humidification chamber. A vented cap is provided to couple water from the bottle to the chamber via a supply line coupled between a water port of the cap and a water inlet of the chamber, and to provide a vent between the chamber and the bottle via a vent line coupled between a vent port of the cap and a vent of the chamber. A straw couples the vent port to a space within the inverted bottle spaced from the cap, such as above the water line. The vented cap includes a duckbill valve in the vent port.

Abstract: An accelerator pump cover is provided. The accelerator pump cover includes a body having a cavity for receiving fuel, a first passageway for allowing passage of fuel into the cavity, a second passageway for allowing passage of fuel out of the cavity, and an adjustable member at least partially disposed within a portion of at least one of the first passageway and the second passageway.

Abstract: A variable fuel admission carburetor is provided comprising a piston and cylinder that are mated concentrically, and coexist in a carburetor chamber. The cylinder comprises a longitudinal slot which allows varying amount of fuel into the carburetor. Through the relative longitudinal movement of the piston in the cylinder, the exposed length of the slot is varied, thereby varying the amount and rate that the fuel enters the chamber.

Abstract: A float for a humidification chamber has formed-in-place conformable seal, which may be accomplished by overmolding a thermoplastic elastomeric material to the float. The float may be comprised of sections sealingly joined together at an elevation above the water level defined by the buoyancy of the float and also above the water level within the humidifier chamber when filled.