Abstract: A power semiconductor device and its manufacturing method are provided that enable reducing its on-state voltage and power loss. The semiconductor device includes a set of L-shaped trench gates 3 each formed, from the top-side surface of a p base layer 2, perpendicularly with respect to a first main surface of an n? layer 1, to reach into a location of the n? layer 1. At the lower ends of each of the trench gates 3, bottom portions 3d are provided to unilaterally extend a predetermined length in one direction parallel to the first main surface of the n? layer 1. In addition, the extending end of one of the bottom portions 3d opposes that of the other bottom portion, on the extending side of the bottom portions 3d, and the interspace between each pair of adjacent bottom portions 3d is set narrower than any other interspace between the trench-gate parts that are perpendicularly formed with respect to the first main surface of the n? layer 1.

Abstract: A semiconductor device including: a semiconductor region having a first semiconductor face and a second semiconductor face connected to the first semiconductor face and having an inclination with respect to the first semiconductor face; a gate insulating film formed on the first and on the second semiconductor faces; a gate electrode formed on the gate insulating film including a part on a boundary between the first semiconductor face and the second semiconductor face; a source impurity region formed in the semiconductor region so as to overlap the gate electrode within the first semiconductor face with the gate insulating film interposed between the source impurity region and the gate electrode; and a drain impurity region formed in the semiconductor region directly under the second semiconductor face at least.

Abstract: A semiconductor device includes a semiconductor substrate and recess trenches formed on the semiconductor substrate. The recess trenches are arranged to extend along a first direction. Terminal regions of adjacent ones of the recess trenches are offset relative to each other along a second direction substantially perpendicular to the first direction.

Abstract: A photo mask, a semiconductor integrated circuit, and a method of manufacturing the same are provided. The photo mask includes light transmitting rows and recess trenches, respectively, that include a short region in every other light transmitting row. In the semiconductor integrated circuit, the short region may include a dummy transistor so that short-circuiting bridges that may occur between adjacent recess trenches will not adversely affect the operations of the semiconductor integrated circuit.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed. The embodiment improves a snapback breakdown voltage and preventing a phenomenon of dashed curves, by forming a gate to be overlapped with first and second drift regions and first and second regions formed in source and drain regions.

Abstract: Under a sidewall formed over a side wall of a gate electrode, a low-concentration LDD region and a high-concentration LDD region which is extremely shallow and apart from a region under the gate electrode are formed. Further, a source/drain region is formed outside these LDD regions. Since the extremely shallow high-concentration LDD region is formed under the sidewall, even if hot carriers are accumulated in the sidewall, depletion due to the hot carriers can be suppressed. Further, since the high-concentration LDD region is formed apart from a region under the gate electrode, a transverse electric field in the channel is sufficiently relaxed, so that characteristic deterioration due to a threshold shift can be suppressed.

Abstract: A semiconductor structure including an nFET having a fully silicided gate electrode wherein a new dual stress liner configuration is used to enhance the stress in the channel region that lies beneath the gate electrode is provided. The new dual stress liner configuration includes a first stress liner that has an upper surface that is substantially planar with an upper surface of a fully silicided gate electrode of the nFET. In accordance with the present invention, the first stress liner is not present atop the nFET including the fully silicided gate electrode. Instead, the first stress liner of the present invention partially wraps around, i.e., surrounds the sides of, the nFET with the fully silicided gate electrode. A second stress liner having an opposite polarity as that of the first stress liner (i.e., of an opposite stress type) is located on the upper surface of the first stress liner as well as atop the nFET that contains the fully silicided FET.

Abstract: A method of manufacturing a thin film including the steps of: providing a film manufacturing apparatus including a first discharge electrode, a second discharge electrode placed opposed to the first discharge electrode and a high frequency power source, which supplies high frequency power between the first discharge electrode and a second discharge electrode; placing a substrate on which a conductive line pattern has been formed on the second discharge electrode; applying the high frequency power from the high frequency power supply while generating plasma by using discharged gas under an atmospheric pressure or a near-atmospheric pressure; and forming a thin film on the substrate, wherein a space ratio (W/L) of a line width W (W>0) of the conductive line pattern to a spatial distance L between the first discharge electrode and the substrate is set not more than 0.1.

Abstract: A three-dimensional integrated circuit includes a first device located over a substrate. The first device has a first structure that has a minimum linewidth. The first structure is laterally separated from a first alignment mark also located over the substrate. The three-dimensional integrated circuit also includes a second device located over the first device. The second device has a second structure that has the minimum linewidth. No second alignment mark is located laterally separated from the second structure. The first structure and the second structure are registered within the minimum linewidth.

Abstract: A method and apparatus for regulating photocurrents is described. A photocurrent regulator may include a transistor having an associated cross-sectional area. The photocurrent regulator is coupled between an integrated circuit and a voltage source. When a dose rate event occurs within the integrated circuit, the photocurrent regulator, via the cross-sectional area, regulates a recombination path to the voltage source. Consequently, photocurrents within the integrated circuit are regulated, preventing permanent damage within the integrated circuit.

Abstract: Some embodiments discussed relate to an integrated circuit and methods for making it, comprises a semiconductor substrate and a plurality of fins disposed on the semiconductor substrate and a gate insulator disposed on the plurality of fins and a gate stack disposed on the gate insulator and the plurality of fins are implanted by a dopant.

Abstract: The method of manufacturing a semiconductor device, including a first region where a transistor including a gate electrode of a stacked structure is formed, a second region where a transistor including a gate electrode of a single-layer structure is formed, and a third region positioned in a boundary part between the first region and the second region, includes: depositing a first conductive film, patterning the first conductive film in the first region and the third region so that the outer edge is positioned in the third region, depositing the second conductive film, patterning the second conductive film to form a control gate in the first region while leaving the second conductive film, covering the second region and having the inner edge positioned inner of the outer edge of the first conductive film, and patterning the second conductive film in the second region to form the gate electrode.

Abstract: A dual gate Complementary Metal Oxide Semiconductor (CMOS) device includes a gate electrode of PMOS transistor implanted with germanium and indium ions and formed on a gate insulating film; a gate electrode of NMOS transistor not implanted with germanium and indium ions and formed on the gate insulating film; a source/drain region formed in a substrate exposed at both sides of the gate electrodes of the PMOS and NMOS transistors; and metal silicides formed on the source/drain region and the gate electrodes. A method for manufacturing a dual gate CMOS device, the method includes forming a gate insulating film; forming a polycrystalline silicon layer; forming an ion implantation mask; implanting germanium (Ge) and indium (In) ions into a PMOS transistor region of the substrate; and removing the ion implantation mask, patterning the polycrystalline silicon layer, and forming gate electrodes for PMOS and NMOS transistors.

Abstract: A semiconductor device includes an n-channel MIS transistor and a p-channel MIS transistor. The n-channel MIS transistor includes a first source region formed in a semiconductor region on a substrate, a first drain region formed in the semiconductor region apart from the first source region, a first gate insulating film, and a first gate electrode formed on the first gate insulating film. The p-channel MIS transistor includes a second source region formed in the semiconductor region, a second drain region formed in the semiconductor region apart from the second source region, a second gate insulating film, and a second gate electrode formed on the second gate insulating film. The first and second drain regions are arranged to be connected to each other and made of the same material, and one of the first and second source regions is made of a material different from the first and second drain regions.

Abstract: A element isolation insulating film is formed around the device regions in the silicon substrate. The device regions are formed an n-type diffusion layer region, a p-type diffusion layer region, a p-type extension region, an n-type extension region, a p-type source/drain region, an n-type source/drain region, and a nickel silicide film. Each gate dielectric film is made up of a silicon oxide film and a hafnium silicon oxynitride film. The n-type gate electrode is made up of an n-type silicon film and a nickel silicide film, and the p-type gate electrode is made up of a nickel silicide film. The hafnium silicon oxynitride films are not formed on the sidewalls of the gate electrodes.

Abstract: A CMOS semiconductor device includes: an isolation region formed in the surface layer of a semiconductor substrate to define an NMOSFET active region and a PMOSFET active region adjacent to each other; an NMOSFET structure formed in the NMOSFET active region; a PMOSFET structure formed in the PMOSFET active region; a tensile stress film covering the NMOSFET structure; and a compressive stress film covering the PMOSFET structure, wherein a border between the tensile stress film and the compressive stress film is set nearer to the PMOSFET active region than the NMOSFET active region along a gate width direction. A performance of a CMOS semiconductor device can be improved by the layout of the tensile and compressive stress films.

Abstract: Embodiments relate to a method of forming a 90 nm semiconductor device, including forming an isolation film within a semiconductor substrate in which a pMOS region and an nMOS region are defined. A first mask is formed to shield the nMOS region by using a DUV photoresist having a thickness of approximately 0.7 to 0.75 ?m. Ions are implanted into the pMOS region to form a p type well. A second mask is formed to shield the pMOS region by using a DUV photoresist having a thickness of approximately 0.7 to 0.75 ?m. Ions are implanted into the nMOS region to form an n type well. A gate oxide film and a gate is formed over the semiconductor substrate. A low-concentration impurity may be implanted by using the gate as a mask. An LDD region may be formed. A sidewall spacer may be formed over both sidewalls of the gate. A high-concentration impurity is implanted by using the sidewall spacer as a mask, forming a source/drain region.

Abstract: In a first aspect, a first apparatus is provided. The first apparatus is a semiconductor device on a substrate that includes (1) a first metal-oxide-semiconductor field-effect transistor (MOSFET); (2) a second MOSFET coupled to the first MOSFET, wherein portions of the first and second MOSFETs form first and second bipolar junction transistors (BJTs) which are coupled into a loop; and (3) a conductive region that electrically couples a source diffusion region of the first or second MOSFET with a doped well region below the source diffusion region. The conductive region is adapted to prevent an induced current from forming in the loop. In another aspect, a design structure embodied in a machine readable medium for designing manufacturing, or testing a design is provided. Numerous other aspects are provided.

Abstract: Embodiments discussed herein relate to processes of producing a field stop zone within a semiconductor substrate by implanting dopant atoms into the substrate to form a field stop zone between a channel region and a surface of the substrate, at least some of the dopant atoms having energy levels of at least 0.15 eV below the energy level of the conduction band edge of semiconductor substrate; and laser annealing the field stop zone.

Abstract: A semiconductor device include an emitter layer, an emitter electrode containing a metal-semiconductor compound of a metal and a semiconductor, formed on a surface of the emitter layer, and a first reaction suppression layer formed between the emitter layer and the emitter electrode and suppressing permeation of the metal diffused from the emitter electrode.

Abstract: By performing a silicidation process on the basis of a patterned dielectric layer, such as an interlayer dielectric material, the respective metal silicide portions may be provided in a highly localized manner at the respective contact regions, while the overall amount of metal silicide may be significantly reduced. In this way, a negative influence of the stress of metal silicide on the channel regions of field effect transistors may be significantly reduced, while nevertheless maintaining a low contact resistance.

Abstract: The present invention discloses a small-pitch three-dimensional mask-programmable memory (SP-3DmM). It is an ultra-low-cost and ultra-high-density semiconductor memory. SP-3DmM comprises a mask-programmable memory level stacked above the substrate. This memory level comprises diodes but no transistors or antifuses. Its minimum line pitch is smaller than the minimum gate pitch of the substrate transistors.

Abstract: A power semiconductor device includes a semiconductor chip, a first conductive piece, a second conductive piece and an encapsulating resin. The semiconductor chip includes a first electrode and a second electrode. The first conductive piece is in contact with the first electrode of the semiconductor chip. The second conductive piece is in contact with the second electrode of the semiconductor chip. The encapsulating resin covers the semiconductor chip, a portion of the first conductive piece and a portion of the second conductive piece, such that a conducting current is transmitted through the first conductive piece and the second conductive piece to form a power diode. In an embodiment, the power semiconductor device further includes a conductive pin and a third electrode.

Abstract: A semiconductor device including fin-FETs capable of suppressing both OFF-current resulting from the short channel effect and junction leakage, and a manufacturing method thereof are provided. A semiconductor device comprises: an active region defined to have a crank shape by an STI region formed on a semiconductor substrate, the active region having an upper surface higher than an upper surface of the STI region; a source region and a drain region formed on both ends of the active region, respectively; a channel region formed between the source region and the drain region in the active region; and a gate electrode covering an upper surface and side surfaces of a central portion of the active region including the channel region.

Abstract: A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor includes a substrate with spaced-apart source and drain regions formed in the substrate and a channel region defined between the source and drain regions. A layer of gate oxide is formed over at least a part of the channel region with a gate formed over the gate oxide. The gate further includes at least one implant aperture formed therein with the channel region of the substrate further including an implanted region within the channel between the source and drain regions. Methods for forming the threshold voltage adjusted transistor are also disclosed.

Abstract: A semiconductor device and a method of fabricating same are provided. According to an embodiment, a gate insulating layer and a gate are sequentially formed on a substrate, and a pocket ion implant region is formed at sides and below a portion of the gate at a predetermined depth in the substrate. An LDD ion implant region can be formed between the pocket ion implant region and the surface of the substrate. A spacer is formed on sides of the gate, and a deep source/drain region is formed by ion-implanting BF2 within the substrate at sides of the spacer.

Abstract: A semiconductor device and a fabricating method thereof are provided. Barrier patterns are formed between a gate and spacers, and between LDD regions and the spacers, thereby inhibiting impurities of the LDD regions from diffusing into the gate.

Abstract: A semiconductor apparatus wherein a device formed on a semiconductor substrate comprises a gate insulating film including a high dielectric constant film formed on the substrate and an anti-reaction film formed on the high dielectric constant film, and a gate electrode formed on the anti-reaction film, the high dielectric constant film comprises a film containing at least one of Hf and Zr, and Si and O, or a film containing at least one of Hf and Zr, and Si, O and N, the anti-reaction film comprises an SiO2 film, a film containing SiO2 as a main component and at least one of Hf and Zr, a film containing SiO2 as a main component and N, a film containing SiO2 as a main component, Hf and N, a film containing SiO2 as a main component, Zr and N, or a film containing SiO2 as a main component, Hf, Zr and N.

Abstract: Input circuit ensuring a noise margin for a reference voltage. A semiconductor chip 11a comprises a pad 14 that inputs a reference voltage Vref, an input circuit 13, a resistance element R1 connected between an input terminal of the input circuit 13 and the pad 14, a capacitance element C1 connected between the input terminal of the input circuit 13 and a power supply VDD, and a capacitance element C2 connected between the input terminal of the input circuit 13 and a ground VSS within the semiconductor chip. A resistance value of the resistance element R1 is set based on an impedance characteristic of a network, for supplying the reference voltage Vref.

Abstract: A semiconductor device according to an embodiment includes device isolating layers having a top surface lower than a sheet height of a semiconductor substrate; a gate insulating layer and a gate electrode sequentially stacked on the upper surface of an active region of the semiconductor substrate between the device isolating layers; a spacer formed at the side wall of the gate electrode; a source/drain region formed in the semiconductor substrate between the spacer and the device isolating layers; and a silicide film formed on the source/drain region.

Abstract: A method of forming a gate electrode of a semiconductor device includes at least one of the following steps: Forming a gate oxide layer over a wafer substrate. Forming a polysilicon layer over the gate oxide layer. Forming a TiSiN layer over the polysilicon layer. Forming a WSix layer over the TiSiN layer.

Abstract: A universal microelectromechanical MEMS nano-sensor platform having a substrate and conductive layer deposited in a pattern on the surface to make several devices at the same time, a patterned insulation layer, wherein the insulation layer is configured to expose one or more portions of the conductive layer, and one or more functionalization layers deposited on the exposed portions of the conductive layer. The functionalization layers are adapted to provide one or more transducer sensor classes selected from the group consisting of: radiant, electrochemical, electronic, mechanical, magnetic, and thermal sensors for chemical and physical variables.

Abstract: A differential pressure sensor includes a micro-electromechanical sensor die fabricated as a plurality of sensor die sites on a semiconductor wafer, and then singularized, the sensor die having a top face surface including die electrical output pads exposed to a first test fluid source and a bottom side surface exposed to a second test fluid source. The differential pressure further has a sensor die support member having a die support member fluid access port with a support member port perimeter; wherein one of the top face surface or the bottom side surface is sealed fully around the support member port perimeter by a wafer scale seal formed on the plurality of sensor die sites before die singulation. Wafer scale seals may be formed by a photofabrication process, screen printing, stamp printing, or pressure transfer printing. Some embodiments may include a photofabricated seal formed by a photosensitive polydimethylsiloxane material, by a filled photofabricated mold, and by photopatterned glass frit.

Abstract: A lead frame which is disposed in an outer package is composed of three members. The lead frame is provided with contact electrodes, connector terminals, and conductive interconnections which are connected to the respective connector terminals. The arrangement order of the contact electrodes is such that contact electrodes are connected to the connector terminals, respectively; that is, the arrangement direction of the contact electrodes is the same as that of the connector terminals. On the other hand, the arrangement order of the contact electrodes is such that contact electrodes are connected to the connector terminals, respectively, that is, the arrangement direction of the contact electrodes is opposite to that of the connector terminals. Lead terminals of a resin cell package are connected to the contact electrodes.

Abstract: An arrangement of magnetic liners for the bit lines or word lines of an MRAM device that reduces or eliminates stray magnetic fields at the ends of the magnetic liners, thereby reducing the occurrence of offset fields over portions of the MRAM device due to the magnetic liners is described. The orientation of magnetization of adjacent magnetic liners is alternated, causing the end poles of the magnetic liners to cancel each other. The shapes of the ends of the magnetic liners are alternated to vary their switching fields. Methods are described that use this ability to vary the switching fields to alternate the orientation of magnetization of the magnetic liners.

Abstract: A recessed color filter array using patterned metal as an etch stop and a method of forming the same. In one embodiment, at least one metal etch stop is formed in a semiconductor dielectric layer at the same time as the formation of one or more layers of metal interconnect elements, thereby reducing the number of necessary process steps and reducing costs. The etch stop may be formed at any layer where other metal elements are present.

Abstract: An image sensor is provided. The image sensor includes a first passivation layer, a color filter layer, microlenses, an uppermost conducting layer, a second passivation layer, and a third passivation layer. The first passivation layer is formed on a substrate including a predetermined pixel portion and a logic pad portion. The color filter layer and the microlenses are formed on a portion of the first passivation layer corresponding to the pixel portion. The uppermost conducting layer is formed in a portion of the first passivation layer that corresponds to the logic pad portion. The second passivation layer is formed on the first passivation layer corresponding to the logic pad portion to expose a portion of the uppermost conducting layer. The third passivation layer is formed on the second passivation layer to expose the uppermost conducting layer.

Abstract: A photoelectric conversion device is disclosed. The photoelectric conversion device includes a semiconductor substrate having a plurality of photoelectric converters, a multilayer wiring structure arranged on the semiconductor substrate, and a planarized layer arranged on the multilayer wiring structure. The multilayer wiring structure includes a first wiring layer, an interlayer insulation film arranged to cover the first wiring layer, and a second wiring layer serving as a top wiring layer arranged on the interlayer insulation film. The planarized layer covers the interlayer insulation film and the second wiring layer. The second wiring layer is thinner than the first wiring layer.

Abstract: An image sensor formed using a method for manufacturing a planar layer in a process for forming microlenses may be used in a complementary metal oxide semiconductor (CMOS) image sensor. Embodiments provide a planar layer that can improve the operation performance of an image sensor, a manufacturing method thereof, and the image sensor including the planar layer. Embodiments relate to a planar layer located under microlenses, the planar layer including valleys of patterns having a predetermined size, which may eliminate optical cross talk between adjacent pixels.

Abstract: A system and method is disclosed for illuminating a plurality of emitters such as light emitting diodes (LEDs). The system comprises a plurality of LEDs and a circuit to provide a digital signal. An LED drive circuit is included comprising a first converter for converting the digital signal to one or more analog voltages. The LED drive circuit further comprises a second converter that converts the one or more analog voltages into corresponding one or more drive currents. Each of the drive currents is applied to at least one of the plurality of LEDs to cause the at least one of the plurality of LEDs to emit light. The intensity of emission of the LEDs is related to the level of the applied drive current.

Abstract: An integrated circuit, and method for manufacturing the integrated circuit, where the integrated circuit can include a phototransistor comprising a base having a SiGe base layer of a predetermined germanium composition and a thickness of more than 65 nm and less than about 90 nm. The integrated circuit can further include a transimpedance amplifier (TIA) receiving an output from the phototransistor. The phototransistor and the TIA can be built on a silicon substrate.

Abstract: A method and apparatus for forming connections within a semiconductor device is disclosed. The semiconductor device incorporates a contact bridge between transistor contacts in close proximity. The contact bridge comprises a plurality of metal pillars each having a lower end in electrical contact with first and second transistor elements, respectively; one or more intermediate metal pillars disposed between and in electrical contact with an upper end of the metal pillars; and one or more separation regions of dielectric disposed below the intermediate metal pillar and between the lower ends of the first and second metal pillars.

Abstract: Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

Abstract: A resistance type memory device disposed on a substrate including a first conductive layer, a second conductive layer and a variable resistance material layer is described. These conductive layers are composed of single or separate electrodes. The variable resistance material layer is disposed between the first conductive layer and the second conductive layer.

Abstract: A semiconductor device is provided with a conductor wire and a fuse wire formed in an insulating film over a semiconductor substrate, a first under-pad-wire insulating film formed above the insulating film, a second under-pad-wire insulating film formed on the first under-pad-wire insulating film, a pad wire formed in an area above the conductive wire, in the first and second under-pad-wire insulating films and an opening formed by leaving a part of the first under-pad-wire insulating film in an area above the fuse wire, in the first and second under-pad-wire insulating films, wherein the second under-pad-wire insulating film comprises an element different from that of the first under-pad-wire insulating film.

Abstract: A semiconductor device and a fabrication method thereof are provided. An inductor device provided with an inductor cell and a second device having a RF device circuit unit are provided next to each other in the same plane and are electrically connected to each other through a connecting electrode.

Abstract: A method for manufacturing an inductor according to the embodiment comprises the steps of: forming a first photoresist pattern; forming an impurity region forming the inductor by implanting an impurity ion to the substrate by means of the first photoresist pattern and a pad region applying current across the impurity region; forming a second photoresist pattern so that a position spaced by a predetermined interval from the impurity region is opened; and forming a guard impurity region in the position spaced from the impurity region by implanting the same impurity ion as the impurity ion by means of the second photoresist pattern.

Abstract: A new method and structure is provided for the creation of a semiconductor inductor. Under the first embodiment of the invention, a semiconductor substrate is provided with a scribe line in a passive surface region and active circuits surrounding the passive region. At least one bond pad is created on the passive surface of the substrate close to and on each side of the scribe line. A layer of insulation is deposited, a layer of dielectric is deposited over the layer of insulation, at least one bond pad is provided on the surface of the layer of dielectric on each side of the scribe line. At least one inductor is created on each side of the scribe line on the surface of the layer of dielectric. A layer of passivation is deposited over the layer of dielectric. The substrate is attached to a glass panel by interfacing the surface of the layer of passivation with the glass panel. The substrate is sawed from the backside of the substrate in alignment with the scribe line.

Abstract: A semiconductor device including a capacitor and a proximate high-voltage gate having a boron-barrier layer that ideally serves as part of both the capacitor dielectric and the (high voltage) HV gate oxide. The boron-barrier layer is preferably formed over a poly oxide layer that is in turn deposited on a substrate infused to create a neighboring wells, and N-well over which the capacitor will be formed, and P-well to be overlaid by the HV gate. The boron-barrier helps to reduce or eliminate the harmful effects of boron diffusion from the P-well during TEOS deposition of the gate oxide material.

Abstract: Example embodiments relate to a capacitor including p-type doped silicon germanium and a method of manufacturing the capacitor. The capacitor may include a lower electrode, a dielectric layer, an upper electrode, a barrier layer and a capping layer. The lower electrode may have a cylindrical shape. The dielectric layer may be on the lower electrode. The dielectric layer may have a uniform thickness. The upper electrode may be on the dielectric layer. The upper electrode may have a more uniform thickness. The capping layer may be on the upper electrode. The capping layer may include a silicon germanium layer doped with p-type impurities. The barrier layer may be between the upper electrode and the capping layer to prevent (or reduce) the p-type impurities from infiltrating into the dielectric layer.