Abstract: The present invention provides recombinant expression cassettes comprising a fungal 3? termination sequence which is functional in a plant. The recombinant expression cassettes comprise a plant promoter operably linked to a coding sequence having a stop codon, and the fungal 3? termination sequence. The fungal 3? termination sequence is heterologous to the coding sequence. The fungal 3? termination sequence comprises structural features including a cleavage site, a positioning element, and an upstream element. The present invention also comprises methods for construction of the plant expression cassettes and introducing the cassettes into plant cells.

Abstract: The invention relates to modified neomycin phosphotransferase genes and their use in a selection method for high-producing recombinant cells. The invention further relates to expression vectors which contain a modified neomycin phosphotransferase gene and a gene of interest functionally linked to a heterologous promoter and a method of preparing heterologous gene products using these expression vectors.

Abstract: This invention is predicated on the present applicants' discovery that nanostructures comprising discrete regions of different composition can be used to deliver to a biological cell a desired combination of molecules in close proximity. Different molecules can be selectively bonded to discrete regions of different composition in sufficiently close physical relationship to enhance delivery or effectiveness within the cell. The preferred nanostructures are multicomponent nanorods. Important applications include delivery of missing DNA sequences for gene therapy and delivery of antigens or DNA encoding antigens for vaccination.

Abstract: A nucleic acid sequence of the blueberry red ringspot virus is disclosed. Also disclosed are putative promoter regions of the sequence and promoter regions capable of directing transgene expression in plants, including tissue-specific expression. Also disclosed are expression vectors, transformed plant cells and plants containing a blueberry red ringspot virus promoter and an encoded product for expression. Methods for diagnosis of blueberry red ringspot virus infection are also provided.

Abstract: A method of predicting the composition of hydrocarbon products of a complex carbonaceous material when exposed to specific time and temperature conditions is disclosed. In one embodiment, the material is characterized to obtain elemental, chemical and structural parameters. A representative chemical structure of the material is constructed based on the characterization information. The representative chemical structure is then stochastically expanded to a molecular ensemble chemical structural model that includes heteroatoms. The chemical structural model is coupled to a compositional yield model and the composition of the material products is determined using kinetic modeling.

Abstract: A method for discriminating and quantifying platelets within an analyzed blood sample involves initially diluting the blood sample with a ghosting reagent that causes a change in the index of refraction of the red blood cells. Owing to the change in the index of refraction, light scattered from the ghosted red blood cells will be substantially reduced relative to light scattered from platelets. This results in locations of platelets within a scatterplot of the analyzed blood sample to fall within a region distinguishable from those containing normal red blood cells, fragmented red blood cells, and microcytic red blood cells.

Abstract: A process vessel containing both an evaporation zone for evaporating a liquid feed and a treatment zone for treating the resulting vapor comprises an injector having an orifice, the orifice being in the evaporation zone, at least one evaporation surface for evaporating feed and generating vapor, the evaporation surface being located in the evaporation zone, wherein the injector orifice and the evaporation surface are positioned to prevent the formation of a drop at the orifice, a treatment zone for treating the vapor and at least one heater associated with at least a portion of the process vessel.

Abstract: The invention relates to methods and compositions for identifying subjects having, or predisposed to having, gestational diabetes, preeclampsia, and gestational hypertension. The methods are applicable to urine and/or blood samples and can be conducted prior to the third trimester of pregnancy.

Abstract: A chromatographic lateral-flow assay system for rapid, high sensitivity method of detecting low levels of ligands in body fluids, with few false positives and few false negatives. The lateral-flow assay may have a membrane strip in ribbon form, which increases detection on the order of 2 to 10 fold over the conventional chromatographic specific binding assay techniques by placing a dried or lyophilized conjugate in colloidal spheres opposite side of the lateral flow membrane strip. A chromatographic specific binding assay strip device, comprising: a laminate strip having a first side and an opposite second side; a conjugate pad or membrane disposed on said first side of said laminate; a sample receiving pad or membrane strip and reservoir pad or membrane disposed on said second side of said laminate; and a detection pad or membrane strip disposed between the sample pad or membrane and the reservoir pad or membrane on said second side of said laminate.

Abstract: A method and miniature analytical device with thermal regulation of reactant using a localized heat source capable of emitting electromagnetic radiation, such as light emitting diodes (“LED”s) and vertical cavity surface emitting lasers (“VCSEL”s), generating internal heat, such as resistive, inductive and Peltier heaters, or external heating. The miniature analytical device comprises of array of temperature-controlled zones to restrict the volume heated and localize the heating by having the localized heat source comprise an array of emitters or heaters.

Abstract: A process for synthesizing nanoparticles, in particular metal salt nanoparticles. To the synthesis mixture is added a modifying reagent which binds, by means of a first functional group, to the nanoparticle surface and which carries a second functional group for binding to molecules which are specifically selected in dependence on the subsequent use of the nanoparticles. This dispenses with a postsynthetic, separate, application-specific modification step. A new substance class, the pentaalkyl iminobis(methylenephosphono)carboxylates, are particularly suitable for this purpose.

Abstract: Methods of forming ferromagnetic liners on the top surface and sidewalls of conductive lines of magnetic memory devices. The ferromagnetic liners increase the flux concentration of current run through the conductive lines, reducing the amount of write current needed to switch magnetic memory cells. In one embodiment, an in-bound pole is formed at the bottom edge of conductive lines, further concentrating the flux.

Abstract: A ferroelectric polymer memory device and its method of formation are disclosed. In accordance with one embodiment, lower electrode memory device portions are formed using a damascene patterning process and upper electrode memory device portions are formed using a subtractive patterning process.

Abstract: After a bottom electrode film is formed, a ferroelectric film is formed on the bottom electrode film. Then, a heat treatment is performed for the ferroelectric film in an oxidizing atmosphere so as to crystallize the ferroelectric film. Then, a top electrode film is formed on the ferroelectric film. In the heat treatment (i.e., annealing for crystallization), a flow rate of oxidizing gas is set to be in a range of from 10 sccm to 100 sccm.

Abstract: A method for forming a die on a wafer is provided. The method includes forming on a wafer a die having an active portion that includes integrated circuitry. The method further includes forming at least one input bond pad on the active portion and at least one test pad on the die. A conductive path is formed between the input bond pad and the test pad. A portion of the conductive path is formed on the die outside of the active portion of the die.

Abstract: Disclosed are a semiconductor wafer (10) having a front side laser scribe (22) and the methods for manufacturing the same. The methods of the invention include the formation of a scribe foundation (12) on the front side of the semiconductor wafer (10) designed to accept laser scribing (22), and laser scribing the scribe foundation (12). Disclosed embodiments include a semiconductor wafer (10) having a scribe foundation (12) of layered dielectric (30) and metal (34) on the front side. According to disclosed embodiments of the invention, the formation of a scribe foundation (12) is performed in combination with the formation of a top level metal layer (34) on the semiconductor wafer (10) methods for manufacturing.

Abstract: A method and apparatus for forming a hermetic seal between two substrates includes providing an electromagnetic absorbent sealing material perimetrically about a surface of one of the substrates. Furthermore, the illustrative method includes heating the sealing material. In addition, a package having a hermetic seal and apparati for disposing a sealing material are described.

Abstract: One or more LED dice are mounted on a support structure. The support structure may be a submount with the LED dice already electrically connected to leads on the submount. A mold has indentations in it corresponding to the positions of the LED dice on the support structure. The indentations are filled with a liquid optically transparent material, such as silicone, which when cured forms a lens material. The shape of the indentations will be the shape of the lens. The mold and the LED dice/support structure are brought together so that each LED die resides within the liquid silicone in an associated indentation. The mold is then heated to cure (harden) the silicone. The mold and the support structure are then separated, leaving a complete silicone lens over each LED die. This over molding process may be repeated with different molds to create concentric shells of lenses.

Abstract: Light-emitting devices, and related components, processes, systems and methods are disclosed.

Abstract: Provided is a method of fabricating a laser diode.

Abstract: Semiconductor substrate is disclosed having quantum wells having first bandgap, and quantum wells having second bandgap less than second bandgap. Semiconductor structure is disclosed comprising substrate having quantum wells having given bandgap, other quantum wells modified to bandgap greater than given bandgap. Semiconductor substrate is disclosed comprising wafer having quantum wells, section of first bandgap, and section of second bandgap greater than first bandgap. Method for forming semiconductor substrate is provided, comprising providing wafer having given bandgap, depositing dielectric cap on portion and rapid thermal annealing to tuned bandgap greater than given bandgap. Semiconductor structure is disclosed comprising substrate having quantum wells modified by depositing cap and rapid thermal annealing to tuned bandgap greater than given bandgap.

Abstract: A method and structure for forming a spring structure that avoids undesirable kinks in the spring is described. The method converts a portion of a release layer such that the converted portion resists etching. The converted portion then serves as an anchor region for a spring structure deposited over the release layer. When the non-converted portions of the release layer are etched, the spring curls out of the plane of a plane.

Abstract: Apparatus and methods are provided for enabling wafer-scale encapsulation of microelectromechanical (MEM) devices (e.g., resonators, filters) to protect the MEMs from the ambient and to provide either a controlled ambient or a reduced pressure. In particular, methods for wafer-scale encapsulation of MEM devices are provided, which enable encapsulation of MEM devices under desired ambient conditions that are not determined by the deposition conditions of a sealing process in which MEM release via holes are sealed or pinched-off, and which prevent sealing material from being inadvertently deposited on the MEM device during the sealing process.

Abstract: The present invention relates to an AFM (atomic force microscope) cantilever including a field effect transistor (FET) and a method for manufacturing the same; and, more particularly, to a method for manufacturing an AFM cantilever including an FET formed by a photolithography process, wherein an effective channel length of the FET is a nano-scale. Therefore, The present invention can easily implement a simulation for manufacturing the AFM cantilever including the FET by accurately controlling the effective channel length. And also, the present invention can manufacture the AFM cantilever including the FET having the effective channel ranging several tens to several hundreds nanometers by applying the low price photolithography device, thereby enhancing an accuracy and yield of the manufacturing process and drastically reducing process costs.

Abstract: A semi-conducting device has at least one layer doped with a doping agent and a layer of another type deposited on the doped layer in a single reaction chamber. An operation for avoiding the contamination of the other layer by the doping agent separates the steps of depositing each of the layers.

Abstract: A method for forming a photodiode that is self-aligned to a transfer gate while being compatible with a metal silicide process is disclosed. The method comprises forming a gate stack of gate oxide, polysilicon, and a sacrificial/disposable cap insulator over the polysilicon. The insulator may be a combination of silicon oxynitride and silicon dioxide. After formation of the photodiode, the cap insulator layer is removed.

Abstract: A CMOS image sensor and a method for fabricating the same are provided, in which an N type region of a photodiode is prevented from adjoining a device isolation film and a dark current is reduced. The CMOS image sensor includes an interlayer dielectric film formed between a gate poly and a power line, a contact formed in the interlayer dielectric film, and an epitaxial layer connected with the contact and formed only in a blue photodiode region.

Abstract: Disclosed are methods of fabricating a memory cell structure. More specifically, a copper substrate, including but not limited to copper contacts and/or bit lines, can be formed within a metal-containing layer, for example. Optionally, one or more via openings can then be formed in an overlying dielectric layer to expose one or more of the copper contacts and/or bit lines. Copper sulfide material can be formed thereon. Alternatively, a portion of the exposed copper can be converted to copper sulfide (e.g., Cu2S2 or Cu2S). The copper sulfide material can then be exposed to a vapor phase monomer to facilitate selective growth of a conducting polymer.

Abstract: A method of making organic memory cells made of two electrodes with a controllably conductive media between the two electrodes is disclosed. The controllably conductive media contains an active layer and passive layer. The active layer is formed using spin on techniques and contains an organic semiconductor doped with a metal salt.

Abstract: An organic semiconductor element having multi protection layers and process of making the same are provided. Firstly, forming a first protection layer on the thin film transistor. Next, forming a second protection layer which is thick enough to serve as the photo spacers on said first protection layer. The multi protection layers are then grown on said organic thin film transistor, so as to enable the second protection layer to have the additional function of the photo spacers by the patterning process. Thus the organic thin film transistor can be prevented from being damaged, and achieving the simplification of the manufacturing process and the reduction of the production cost.

Abstract: A method for manufacturing a semiconductor package with a laminated chip cavity is disclosed. A board and a metal foil having a layer of adhesive resin are provided. The metal foil is laminated with the board to make the adhesive resin be attached to the board. Next, a through opening is formed to pass through the board, the adhesive resin and the metal foil. Next, the metal foil is removed to expose an adhesive surface of the adhesive resin on the board so as to attach a carrier plate, thereby forming a chip cavity.

Abstract: A semiconductor device 39. The device includes an interposer 31 having two major surfaces. The first surface 311 includes patterned metal conductors and bond pads 351, and the second surface includes an array of solder balls 33. The device includes a semiconductor chip 30 having a top surface and a back surface, the back surface of the chip adjacent the interposer 31, and the top surface including a plurality of terminals. Also included is a layer of polymeric material 34 disposed on the first surface 311 of the interposer covering the area of the interposer over the solder ball array. At least a portion of the polymeric layer is between the chip 30 and the interposer 31. The device further includes a plurality of electrical connections 35 between the chip terminals and the bond pads 351 on the interposer.

Abstract: A method for packaging a semiconductor device includes forming through holes (12) in a base substrate (10) and depositing a conductive material (14) on a first side (16) of the base substrate (10) to form a conductive layer (18) such that the conductive material (14) fills the through holes (12). The conductive layer (18) is patterned and etched to form interconnect traces and pads (22). Conductive supports (24) are formed on the pads (22) such that the conductive supports (24) extend through respective ones of the through holes (12).

Abstract: In some example embodiments, an integrated circuit, electronic assembly and method provide a current path for supplying power to a processor. As an example, the integrated circuit includes a base having power contacts that extend from an upper surface of base. The integrated circuit further includes a substrate that is mounted to the upper surface of the base to electrically couple the substrate to the base. A die is mounted on a substrate such that the die is electrically coupled to the substrate. The power contacts on the upper surface of the base engage a daughterboard so that the die is able to receive power from a voltage source mounted on the daughterboard through the power contacts on the upper surface of the base.

Abstract: A MCM system board uses a stiffener arrangement to enhance mechanical, thermo and electrical properties by incorporating an LGA compression connector in a computer system. The present designs of large scale computing systems (LSCS) in IBM use a MCM that is attached to a system board and held together by a stiffening frame. Due to the nature of the manufacturing of the system board, there can be significant gaps formed in the mounting area of the MCM between the board and the stiffener. A method is described that not only fills the void, it also, in addition promotes thermo conduction of excess heat away from the MCM and at the same time promotes enhanced electrical properties of the LGA connections of the MCM to the system board.

Abstract: A process for fabricating an integrated circuit package includes: selectively etching a first side of a substrate thereby providing etched regions of the substrate to partially define at least a plurality of contact pads; adding a dielectric material to the etched regions of the substrate; selectively etching a second side of the substrate to further define at least the plurality of contact pads and thereby provide a package base of at least the contact pads and the dielectric; mounting a semiconductor die to the package base and connecting the semiconductor die to the contact pads; fixing a lid to the package base to cover the semiconductor die in a cavity between the lid and the package base; and singulating to provide the integrated circuit package.

Abstract: An integrated circuit device includes a semiconductor component coupled with a lead frame, and an integrated circuit package encompassing at least a portion of the semiconductor component. The package has a first surface and a second surface, and side surfaces, where the first surface is opposite the second surface. A parting line of the integrated circuit package is offset toward the second surface of the package, where the first surface optionally comprises the bottom surface of the package. The first surface of the package has one or more recessed areas.

Abstract: An NROM semiconductor memory device and fabrication method are disclosed. According to one aspect, a method for fabricating an NROM semiconductor memory device can include providing a plurality of u-shaped MOSFETs, which are spaced apart from one another and have a multilayer dielectric. The dielectric suitable for charge trapping along rows in a first direction and alone columns in a second direction in trenches of a semiconductor substrate. Source/drain regions are provided between the u-shaped MOSFETs in interspaces between the rows which run parallel to the columns. Isolation trenches are provided in the source/drain regions between the u-shaped MOSFETs of adjacent columns as far as a particular depth in the semiconductor substrate. The isolation trenches are filled with an insulation material. Word lines are provided for connecting respective rows of u-shaped MOSFETs.

Abstract: A fuse structure, an integrated circuit including the structure, and methods for making the structure and (re)configuring a circuit using the fuse. The fuse structure generally includes (a) a conductive structure with at least two circuit elements electrically coupled thereto, (b) a dielectric layer over the conductive structure, and (c) a first lens over both the first dielectric layer and the conductive structure configured to at least partially focus light onto the conductive structure. The method of making the structure generally includes the steps of (1) forming a conductive structure electrically coupled to first and second circuit elements, (2) forming a dielectric layer thereover, and (3) forming a lens on or over the dielectric layer and over the conductive structure, the lens being configured to at least partially focus light onto the conductive structure.

Abstract: An object of the present invention is to provide a semiconductor device formed by laser crystallization by which formation of grain boundaries in the TFT channel formation region can be avoided, and a method of manufacturing the same. Still another object of the present invention is to provide a method of designating the semiconductor device.

Abstract: A liquid crystal display device including first and second active layers over a substrate, a storage line over the second active layer, a first insulating layer over the storage line, a gate electrode on the first insulating layer and corresponding to the first active layer, a second insulating layer over the gate electrode, source and drain electrodes connected to the first active layer through the first and second insulating layers, a gate line connected to the gate electrode through the second insulating layer, a data line substantially perpendicularly arrange with respect to the gate line to define a pixel region, a pixel electrode connected to the drain electrode through the second insulating layer, and a connection line connected to one of the gate line and the data line through the second insulating layer.

Abstract: A method and an apparatus are provided for manufacturing an active matrix device including a top gate type TFT. A manufacturing process of the top gate type TFT includes the steps of forming an oxide film on the inner wall of a CVD processing chamber and arranging a substrate having source and drain electrodes formed thereon in the processing chamber. Additional steps include doping the source and drain electrodes with P, and forming an a-Si layer and a gate insulating film in the processing chamber. Furthermore, an apparatus is provided for manufacturing an active matrix device including a top gate type TFT having the inner surface of the processing chamber coated with the oxide film.

Abstract: A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.

Abstract: The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes forming a capping layer (210) over a transistor device having source/drain regions (150, 155) located over a substrate (110), the capping layer (210) having a degree of reflectivity, and annealing the transistor device through the capping layer (210) using photons (310), the annealing of the transistor device affected by the degree of reflectivity.

Abstract: To obtain a semiconductor device containing TFTs of different, suitable properties as display pixel TFTs and high-voltage, driver-circuit TFTs, the semiconductor device of the present invention includes: first and second islands-shaped polycrystalline silicon (p-Si) layers provided above an insulating substrate and having relatively large grain sizes; a third islands-shaped p-Si layer having relatively small grain sizes; a first gate insulating film provided on the first p-Si layer and having a first thickness; second and third gate insulating films provided on the second and third p-Si layers having second and third thicknesses which are not less than the first thickness; gate electrodes provided on the gate insulating films; n-type high-concentration source/drain regions formed by adding an n-type impurity to a high concentration outside channel regions; and second and third n-type low-concentration-source/drain regions provided between the channel regions and the n-type high-concentration source/drain regi

Abstract: The present invention is directed to a method of manufacturing a semiconductor device including a semiconductor layer having a heavily doped source region, a heavily doped drain region, a lightly doped source region, a lightly doped drain region and a channel region, and a gate electrode opposite to the semiconductor layer with an insulating layer interposed therebetween. The method includes forming a semiconductor film on a substrate, forming a resist on the semiconductor film such that a first portion of the resist corresponding to the heavily doped source region and the heavily doped drain region is thinner than a second portion of the resist corresponding to the lightly doped source region, the lightly doped drain region and the channel region.

Abstract: A technique for and structures for camouflaging an integrated circuit structure. A layer of conductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is not operable.

Abstract: A method is disclosed of forming an extension region for a transistor having a gate structure overlying a compound semiconductor layer. An anneal is used either before or after deep source/drain implantation to diffuse a dopant from a raised region adjacent the gate structure to a location underlying the gate structure. A non-diffusing activation process can be used to activate source/drain implants when the dopants from the raised region are diffused prior to deep source/drain implantation.

Abstract: A CMOS device with transistors having different gate dielectric materials and a method of manufacture thereof. An aluminum-based material is used as a gate dielectric material of a PMOS device, and a hafnium-based material is used as a gate dielectric material of an NMOS device. A thin layer of silicon a few monolayers or a sub-monolayer thick is formed over the gate dielectric materials, before forming the gates. The thin layer of silicon bonds with the gate dielectric material and pins the work function of the transistors. A gate material that may comprise a metal in one embodiment is deposited over the thin layer of silicon. A CMOS device having a symmetric Vt for the PMOS and NMOS FETs is formed.

Abstract: A method of manufacturing a semiconductor integrated circuit (IC) device that integrates a TLPM (trench lateral power MOSFET) and one or more planar semiconductor devices on a semiconductor substrate. In manufacturing the semiconductor IC device according to one embodiment, a trench etching forms a trench. A p-type body region, an n-type expanded drain region, and a thick oxide film are formed. A second trench etching deepens the trench. Gate oxide films and gate electrodes of the TLPM, an NMOSFET, and a PMOSFET are formed. P-type base regions of the TLPM and an NPN bipolar transistor are formed. An n-type source and drain region of the TLPM, and n-type diffusion regions of the NMOSFET and the NPN bipolar transistor are formed. P-type diffusion regions of the PMOSFET and the NPN bipolar transistor are formed. An interlayer oxide film, a contact electrode, and constituent metal electrodes are formed.