Abstract: A server-load-balancing program for establishing a permanent connection to a server in advance, and requesting the server to execute a processing request received from a client, by using the permanent connection. First, history information indicating conditions of use of at least one permanent connection in each of first time intervals into which each of at least one preceding period is divided is stored. Next, an optimum value of the number of at least one permanent connection to be established in each of second time intervals into which a coming period is divided is determined based on the history information. Then, the at least one permanent connection to the server in each of the second time intervals in the coming period is established so that the number of the at least one permanent connection in each of the second time intervals is equal to the optimum value.

Abstract: An architecture for customizing the amount of web page banner advertising content presented to a user. When a user accesses a server node (102) disposed on a network (104), the user computer (100) provides video resolution information to the server node (102). The server node (102) transmits a web page to the user node (100) which corresponds to the video resolution information of the user node (100). The web page increases the amount of banner advertising presented to the user based upon the user video resolution information provided by the user node (100). The amount of banner advertising is increased by either increasing banner object size or providing more banner advertisements.

Abstract: A method and apparatus for inserting and examining Cookies in the data streams of HTTP connections for the purpose of persistently directing HTTP connections to the same destination. A network device directs subsequent HTTP connections from the same client to the same server (destination) for accessing the requested resources. There are four modes for employing the Cookie to persistently direct HTTP connections. The associated mode inserts a Cookie that uniquely identifies the client into an HTTP response. The passive mode inserts Cookie information that uniquely identifies a previously selected destination into an HTTP response. In the rewrite mode, a network device manages the destination information that is rewritten over blank Cookie information generated by the destination producing the HTTP response. The insert mode inserts and removes Cookie information in the data packets for HTTP requests and response prior to processing by the destination.

Abstract: A system for limiting group access is provided. A representative system includes a group access management system operable to store a plurality of resource lists, the resource lists comprising at least one contact and at least one group comprising at least one member and further comprising a group class of service marker associated with the at least one group. The system further comprises a network service router coupled to the group access management system and being operable to route a service request, if the service request includes an adequate class of service marker with respect to the group class of service marker. Methods and other systems for limiting group access are also provided.

Abstract: A method and apparatus for providing computer network access points the capability for multiple-level accounting. A gateway device located at the access point is capable of generating Internet protocol accounting start and stop requests based on various events that need to be accounted for when a user accesses a network. These events include the user account logon, the service establishments and the Point to Point protocol (PPP) connections between the gateway device and public and private domains within the network. The counter is capable of tracking the duration of sessions and connections and the byte-count associated with the specified session or connection. The gateway device communicates with an accounting server which stores the accounting requests and matches start requests with subsequent stop requests.

Abstract: A method for time-based synchronization of multiple media streams transmitted over a communications network, such as the Internet, by multiple, independent streaming media sources. First and second media streams of data packets are received from first and second media sources. Timing data is parsed from the two media streams, and first and second transmission delay values are determined by comparing the timing data with a reference time. A synchronized media stream is created by combining the first and second media streams into a time-synchronized media stream with adjustments to correct for calculated transmission delay values. Feedback signals are sent to the media sources to control transmission variables such as stream length, transmission rate, and transmittal time to manage the variable delay at the media source. The first and second media streams are decoded into intermediate media streams compatibly formatted to allow mixing of the streams and data packets.

Abstract: A reliable multicast service is operated between a source device and multiple destination devices participating in a multicast group. The source device includes a first source application instance (AI) producing a first unit of work stream, and communication services (CS). Each destination device in the multicast group includes CS, and at least one destination AI which consumes units of work. Communication services/fabric provide communication between the source device and the multiple destination devices. Multiple source and destination resources (SDRs) implement corresponding multiple reliable transport services between the source device and corresponding multiple destination devices in the multicast group for delivery of the first unit of work stream to the corresponding destination devices and guaranteeing strong ordering of the first unit of work stream received at the corresponding destination devices.

Abstract: A system and method for managing e-mail traffic originating from a specific IP address. An outbound e-mail message is routed to an e-mail governor where the IP address of the computer from which outbound e-mail message originated is determined. A record associated with the originating IP address is created in a datatstore. Metrics useful to determine an e-mail message rate and an e-mail byte rate are stored in the e-mail record. An e-mail message rate is determined and compared with an e-mail message rate threshold. If the e-mail message rate threshold is exceeded, the originating IP address is sending spam e-mail (spam) and redial action is taken. An e-mail byte rate is also determined and compared with an e-mail byte rate threshold. If the e-mail byte rate threshold is exceeded, the originating IP address is using excess network resources to send e-mail and redial action is taken.

Abstract: Aspects of the invention may comprise receiving an incoming TCP packet at a TEEC and processing at least a portion of the incoming packet once by the TEEC without having to do any reassembly and/or retransmission by the TEEC. At least a portion of the incoming TCP packet may be buffered in at least one internal elastic buffer of the TEEC. The internal elastic buffer may comprise a receive internal elastic buffer and/or a transmit internal elastic buffer. Accordingly, at least a portion of the incoming TCP packet may be buffered in the receive internal elastic buffer. At least a portion of the processed incoming packet may be placed in a portion of a host memory for processing by a host processor or CPU. Furthermore, at least a portion of the processed incoming TCP packet may be DMA transferred to a portion of the host memory.

Abstract: In some embodiments of the present invention, a system includes one or more server computers having multi-channel reliable network hardware and a proxy. The proxy is able to receive packet-oriented traffic from a client computer, to convert a session of the packet-oriented traffic into transactions, and to send the transactions to one of the server computers. The transactions include remote direct memory access messages.

Abstract: A user's sequence of Web Browser requests when navigating within a single Web site are tracked. Requests for access to resources within the Web site are compared with redirection criteria and, if matching, are redirected to a request tracker which determines a session identifier (generating a new session ID if required), then logs the request and redirects the request back to the Web server for processing. A request tracker outside the scope of the Web server program is used and thus addresses the inability of many Web servers to support cookies and avoid's major rewriting of the Web site.

Abstract: An emergent network is autonomous at the service level. Network nodes have policies that enable them to process different types of service requests, with the processing earning the nodes ‘rewards’. Successful nodes can pass some or all of their policies to other nodes using the evolutionary biology of bacteria as a model.

Abstract: Methods, systems and machine readable media for synchronising three or more electronic devices. In one exemplary method of synchronising three or more electronic devices, said method comprises: a) selecting at least one category of record for synchronisation; b) storing an original value and a changed value of each changed record from a selected record category; c) establishing an electronic connection between at least two devices; d) comparing the records of the selected record categories; e) determining any changed record; f) identifying the updated device with the changed record having an original value the same as the value of the record in the other previous device; and g) changing the value of the record in the previous device to the changed value.

Abstract: A method and associated device for selecting one of a number of equivalent paths in forwarding a network message from a node of a communication network. A source and destination address is provided for the network message. The addresses are formed of individual bit values, and these values have a relative mapping between them. The relative mapping is decorrelated to obtain a decorrelated address pair. A randomized selection function is applied to the decorrelated address pair to produce an index which is derived from the relative sequence of bit values of the decorrelated address paid. The index is then used to select one of the equivalent paths. The associated device provides an address reader, a decorrelation module and a randomized selection module for performing the method previously described.

Abstract: A channel adapter includes a work queue entry table having entries configured for storing work queue entries awaiting respective acknowledgements. Each entry includes a work queue entry field for storing a corresponding work queue entry, and first and second link fields for respective linked lists. The channel adapter also includes a table manager configured for creating the linked lists, based on prescribed network conditions, for example for storage of a first list specifying a transmission order of the work queue entry fields and a second list specifying an acknowledgement order. Hence, the multiple link fields enable the work queue entry table to be shared for respective linked lists specifying respective attributes relative to the stored work queue entries.

Abstract: In an access point high-speed connecting method using presence service, when a wireless terminal for presence service moves into a service area of a wireless LAN or is powered, the terminal can be connected to an access point of the network at a high speed. When a presence subscription request is received from a first wireless terminal as a request source, a second wireless terminal registers a group ID and a user ID to a data storage. At connection to an access point, the second terminal determines the request source, i.e., a transmission destination according to information of access points to which a connection is already once established. The second terminal creates presence information including new network interface support information, i.e., an MAC address, a service set ID, and a group ID of the access point and transmits the presence information.

Abstract: A method for managing nodes in a network includes assigning to a cycle set a cycle having a size of n, the preferred maximum nodes per cycle, or smaller. If this cycle set does not include the all of the nodes in the network, the method includes increasing n by one and assigning to the cycle set a cycle that accesses at least one of the nodes not currently in the cycle set and has a size n, until the cycle set includes all of the nodes in the network. The method further includes moving from the cycle set to a final set a cycle that accesses a node that is accessed by only that particular cycle. If this final set does not include all of the nodes in the network, the method includes moving a remaining cycle from the cycle set to the final set wherein the remaining cycle carries a largest intracycle traffic among cycles in the cycle set, until the final set includes all of the nodes in the network.

Abstract: An apparatus for expanding I/O is described in which no additional strobes or enable lines are necessary from the host controller. By sequencing data in a specific way when output to two existing data or select lines, an expansion I/O device can generate a strobe or enable signal internally. This internal strobe or enable signal is then used to store output data or enable input data. The host controller needs software or firmware to perform the data sequencing, but no additional wires are needed, and no changes are needed to existing peripheral devices. Thus, an existing system can be expanded when there are no additional control lines available and no unused states in existing signals.

Abstract: Methods, systems, and computer readable mediums provide for the detection of IDE drives connected to intelligent drive electronics channels within a computer. Detection may be obtained by reading a status register destination and detecting whether data read from the status register destination has a predefined value. Based on the data read from the status register destination, an indication that an IDE drive is connected to the intelligent drive electronics channel is returned. Detection of enhanced IDE or ATAPI drives connected to an intelligent drive electronics channel is also provided. Enhanced IDE drives may be detected by reading a cylinder high register destination and a cylinder low register destination to detect a predefined signature. Based on the data read from the cylinder high and the cylinder low register destinations, an indication that an enhanced IDE drive is connected to an intelligent drive electronics channel is returned.

Abstract: A semiconductor integrated circuit apparatus capable of reading out semiconductor information stored therein is provided. A semiconductor information storage section has semiconductor information unique to a semiconductor integrated circuit apparatus stored therein. The unique semiconductor information includes, for example, an identification number for identifying the semiconductor integrated circuit apparatus and information for identifying the time of manufacture such as a lot number. An externally provided storage apparatus has a readout program stored therein for reading the semiconductor information of the semiconductor integrated circuit apparatus as required.

Abstract: In a first aspect, a first method is provided for servicing commands. The first method includes the steps of (1) receiving a first command for servicing in a memory controller including a plurality of memory ports, wherein the first command is of a first priority; (2) receiving a second command for servicing in the memory controller, wherein the second command is of a second priority that is higher than the first priority; (3) determining whether the first and second commands will be serviced through the same memory port; and (4) if the first and second commands will not be serviced through the same memory port, servicing the first and second commands during the same time period. Numerous other aspects are provided.

Abstract: It is an object of this invention to expand an SBP-3 protocol such that two data buffers can be independently controlled. To achieve this object, a target sends responses to status blocks corresponding to two commands included in one ORB in the SBP-3, and an initiator receives these responses to the commands independently of each other. The number of times of execution and time interval are designated for each command. The target repeats a command the designated number of times at the designated time interval.

Abstract: Loss of data to be transmitted from a peripheral device to a host before a software hierarchy of the host side completely starts is prevented. In a time period before a host completely reached a normal operation mode from a sleep mode, data outputted from a receiver is stored in second buffer memory of a communication control device. When the host reaches the normal operation mode, an application hierarchy in the host transmits a transmission approval command to a control unit, and then the data is transferred from the second buffer memory to first buffer memory. Since communication between the host and the communication control device of the receiver is resumed and then the data stored in the first buffer memory is sent to the host through a USB line, loss of the data can be prevented.

Abstract: Machine-readable media, methods, and apparatus are described to stream data between a codec and a buffer in system memory and to maintain a value in system memory that is indicative of a current position in the buffer. In some embodiments, an audio controller streams the data across an isochronous channel having relaxed ordering rules to the buffer in the system memory and updates the value indicative of current position via a write across the isochronous channel to the system memory.

Abstract: A control board includes a main-board and a plurality of sub-boards which control loads. The sub-boards each include a providing unit which provides a board type ID, a read unit which reads an installation location ID, and a transmission unit which transmits the board type ID and the installation location ID to the main-board. The main-board includes a communication control unit, a configuration information acquisition unit which acquires configuration information expressed by a combination of the board type ID and the installation location ID, an analysis unit which analyzes the configuration information, and a control unit which controls the sub-unit on the basis of information analyzed by the analysis unit.

Abstract: An autonomous integrated circuit card includes a logic external communication interface which directly communicates with a communication device connected to an integrated circuit card terminal main body via a network, in addition to a host device interface connected to an integrated card reader/writer via a physical layer. A communication control unit includes a software module which directly communicates with the communication device via the external communication interface. A central processing unit performs authentication via the communication control unit and reads value information stored in a nonvolatile memory. Further, the central processing unit encrypts the read value information by use of an encryption processing unit and directly transmits the encrypted value information to the communication device via the communication control unit and the external communication interface.

Abstract: The present invention provides systems, methods, and bus controllers (12) for monitoring an event of interest via a network bus (14) and creating an asynchronous event trigger on the network bus indicating that the event occurred. Importantly, the systems, methods, and bus controllers (12) of the present invention use either one or several network devices (16, 18) that are connected to the network bus (14) and monitor the occurrence of an event of interest. These network devices (16, 18) are configure through commands from the bus controller (12) to indicate on the network bus (14) typically by a pulse signal, when the event of interest has occurred. The indication from the network device (16, 18) that the event has occurred is used by the bus controller (12) and other network devices (16, 18, 20) on the network bus (14) to configure timing for commands or to perform desired actions in synchronization with the occurrence of the event of interest.

Abstract: The systems and methods manage concurrent access requests to a shared resource. The systems and methods utilize an access management algorithm that permits multiple processes to concurrently obtain shared locks on the shared resource, but also limits access to only one process when an exclusive lock is granted. In doing so, the systems and methods avoid the problems of starvation and deadlock.

Abstract: A method of connecting a storage device to a host computer has a first connection processing for enabling a host interface in advance even when the storage device is not ready yet, and a second connection processing for enabling the host interface after the storage device is ready. The first connection processing is carried out when a power supply to the storage device is turned on, and the second connection processing is carried out when the storage device is at a hot plug time.

Abstract: Apparatus for use in a computer system comprises a bus architecture, a plurality of modules connected to the bus architecture, at least one module being latency tolerant and at least one module being latency intolerant. The bus architecture comprises a primary bus (3) having latency intolerant modules connected thereto, a secondary bus (4) having latency tolerant modules connected thereto, and a primary to secondary bus interface module (5) interconnecting the primary and secondary buses.

Abstract: A slave device may be configured to receive at least one bus interface clock and bus interface signals from a bus coupled to the at least one bus interface unit. The slave device may also be configured to operate independently of at least one main function clock.

Abstract: Embodiments of the invention include a bus bridge that is capable of communicating with more than one MSC device coupled to it. In some embodiments, the bridge includes a LUN processor that translates different LUN numbers received from the bus into different addresses and LUNs for devices connected to the bridge. The bridge masks the fact that multiple MSC devices are coupled to it by reporting to the host that only a single device having multiple LUNs are coupled to the bridge.

Abstract: A system to monitor performance of a computing device includes a first bridge to interface with a first set of devices, and a second bridge to interface with a second set of devices. Configuration registers store configuration data associated with the second set of devices, and are accessible through the second bridge. A hub interface allows data to transfer downstream from the first bridge to the second bridge, and allows data to transfer upstream from the second bridge to the first bridge. A controller, external to the first and second bridges, accesses the configuration registers via the second bridge. A logic device allows the second bridge to send data to, and receive data from, the controller.

Abstract: An integrated circuit comprising a plurality of modules (M1 to M5, CPU) for processing applications, a global memory (GM), which can be shared by said plurality of modules (M1 to M5, CPU), an interconnect means (IM) for interconnecting said modules (M1 to M5, CPU) and said global memory (GM) based on a plurality of communication services (C1, C2) is provided. Said integrated circuit further comprises at least one communication managing unit (CMU) for managing the communication between said plurality of modules (M1 to M5), wherein said communication managing unit (CMU) receives a request for a communication between at least two of said modules (M1 to M5, CPU) and dynamically selects one of said plurality of communication services (C1, C2) as basis for the requested communication between said modules (MI to M5, CPU).

Abstract: A system includes a first device; an Integrated Drive Electronics (IDE) bus; and a data storage device having a first task file register, the data storage device being coupled to the first device via the IDE bus for storing data within the data storage device as received from the first device via the IDE bus, or for passing the data stored within the data storage device to the first device via the IDE bus according to commands passed from the first device via the IDE bus. The data storage device is further for controlling predetermined operations of the first device by storing different values within the first task file register, and the first device is for reading the first task file register of the data storage device via the IDE bus and performing the predetermined operations according to the different values.

Abstract: Method and apparatus are described for improving information transfer over USB. In one approach, hub-based extension is realized wherein power is distributed using auxiliary wiring distinct from signal and power wiring present in conventional USB cabling. Additional signals allow optimization of power distribution for powering attached devices, and for detecting and handling illegal connection configurations. In another approach, improvements are realized through use of alternative signaling techniques which eschew reflective and high-speed common-mode signaling. Described are various configuration, media and signal-protocol combinations, including implementations containing embedded hubs. Methods ensuring reliable system behavior are also described, including determination of extension path delay and use of topology-enforcement hubs.

Abstract: A peripheral for notifying a USB-connected upper apparatus of a device descriptor and allowing the upper apparatus to specify a communication partner destination by the function information shown in the device descriptor has: a peripheral function information holding unit which holds function information showing functions of the peripheral; a dependent peripheral function information holding unit which holds function information showing functions of a USB-connected dependent peripheral; and a USB control unit which reads out one of the function information held in those holding units by a selecting instruction and notifies the upper apparatus of the device descriptor in which the read-out function information is shown. A peripheral which can realize a multi-function without developing a dedicated driver and installing it into a PC is provided.

Abstract: In a memory, first and second data areas are set as an area which stores one data item and a management area which stores determination information used to determine which one of the first and second data areas stores the newest data is additionally set. In the process of writing data into the memory, data is written into one of the data areas which stores data determined not to be the newest data based on the determination information and identification information is updated when the data writing process is correctly terminated.

Abstract: A technique that provides highly scalable width expansion architecture for cascading CAMs to facilitate searching of increased wordlengths. In one example embodiment, this is achieved by combining a plurality of CAM devices in a serial cascade arrangement. Each CAM device of the serial cascade arrangement receives a portion of the search word. Each of the CAM devices in the serial cascade arrangement includes a CAM, a plurality of GMAT lines, a dummy match line, and a GMAT interface circuitry. The GMAT interface circuitry facilitates driving the match signals from a substantially previous CAM to a substantially adjacent CAM. The last CAM device is coupled to a match latch and a priority encoder.

Abstract: The storage system includes a disk controller for receiving write commands from a computer, and a plurality of disk devices in which data is written in accordance with the control of the disk controller. The size of the first block which constitutes the data unit handled in the execution of the input/output processing of the data in accordance with the write command by the disk controller is different from the size of the second block which constitutes the data unit handled in the execution of the input/output processing of data by the plurality of disk devices. The disk controller issues an instruction for the writing of data to the disk devices using a third block unit of a size corresponding to a common multiple of the size of the first block and the size of the second block.

Abstract: An apparatus and method for a storage system for storing data on an object basis, where the object has attribute information and data. The storage system has a plurality of (N) data storage devices and at least one redundant data storage device. When the storage system receives a write request with an object, the object is divided into N sub-objects each of which have the same size. Thereafter, each of the N sub-objects is written to the data storage devices. Further, the parity is calculated from each of the sub-objects. In one embodiment the parity is stored in a redundant data storage device.

Abstract: Cluster storage collection-based data management is described. In one aspect, and in a distributed system for storing data across a network to multiple data storage nodes, a bounded bandwidth available for data repair in the distributed system is determined. A specific number of stripes are then created on each data storage node of the multiple data storage nodes. The stripes are for placement and replication of data objects across respective ones of the data storage nodes. The specific number of stripes created on each data storage node is a function of the determined bounded data repair bandwidth.

Abstract: A memory addressing technique using load buffers to improve data access performance. More particularly, embodiments of the invention relate to a method and apparatus to improve cache access performance in a computer system by exploiting addressing mode information within an instruction accessing a cache memory or other memory device within the computer system.

Abstract: One embodiment of the present invention provides a system that selects bases to form a regression model for cache performance. During operation, the system receives empirical data for a cache rate. The system also receives derivative constraints for the cache rate. Next, the system obtains candidate bases that satisfy the derivative constraints. For each of these candidate bases, the system: (1) computes an aggregate error E incurred using the candidate basis over the empirical data; (2) computes an instability measure I of an extrapolation fit for using the candidate basis over an extrapolation region; and then (3) computes a selection criterion F for the candidate basis, wherein F is a function of E and I. Finally, the system minimizes the selection criterion F across the candidate bases to select the basis used for the regression model.

Abstract: A cache system has a branch target address cache, including a storage unit for storing branch target address cache (BTAC) access bits each corresponding to cache lines of an instruction cache. The BTAC access bits represent a presence of a branch instruction on the next cache line of a cache line corresponding to the instruction cache. The BTAC is selectively accessed in accordance with values of the BTAC access bits corresponding to I'th (I is a positive integer) cache lines presently accessed in the instruction cache.

Abstract: An information distribution system includes an interconnect and multiple data processing nodes coupled to the interconnect. Each data processing node includes mass storage and a cache. Each data processing node also includes interface logic configured to receive signals from the interconnect and to apply the signals from the interconnect to affect the content of the cache, and to receive signals from the mass storage and to apply the signals from the mass storage to affect the content of the cache. The content of the mass storage and cache of a particular node may also be provided to other nodes of the system, via the interconnect.

Abstract: First-in-first-out (FIFO) memory system and method for providing the same is described. In one example, a dual-port memory circuit includes first storage locations for defining a plurality of FIFOs, second storage locations for storing status information for each of the FIFOs, a first port, and a second port. The first port includes a write data terminal for receiving write data and a write address terminal for receiving write addresses. Each of the write addresses includes a first portion for selecting a FIFO of the FIFOs and a second portion for selecting a storage location in the dual-port memory circuit. The second port includes a read data terminal for providing read data and a read address terminal for receiving read addresses. Each of the read addresses includes a first portion for selecting a FIFO of the FIFOs and a second portion for selecting a storage location in the dual-port memory circuit.

Abstract: Method and apparatus for transferring speculative data in lieu of requested data in a data transfer operation. First data are transferred in response to an execution of a first pending command. Speculative data are transferred instead of second data associated with a second pending command during a next available latency period for the second data, preferably when the speculative data are adjudged as having a utility greater than a utility of the second data. The first and second commands are preferably received in a queue and a command execution algorithm identifies the second command as a next best command to be executed after execution of the first command. The above steps are preferably carried out by a controller of a data storage device.

Abstract: A method and apparatus for retrieving instructions to be processed by a microprocessor is provided. By pre-fetching instructions in anticipation of being requested, instead of waiting for the instructions to be requested, the latency involved in requesting instructions from higher levels of memory may be avoided. A pre-fetched line of instruction may be stored into a pre-fetch buffer residing on a microprocessor. The pre-fetch buffer may be used by the microprocessor as an alternate source from which to retrieve a requested instruction when the requested instruction is not stored within the first level cache. The particular line of instruction being pre-fetched may be identified based on a configurable stride value. The configurable stride value may be adjusted to maximize the likelihood that a requested instruction, not present in the first level cache, is present in the pre-fetch buffer. The configurable stride value may be updated manually or automatically.

Abstract: Methods and associated structures for bypassing virtual memory and memory mapping management features provided in a memory controller applied to simpler computing applications. In one aspect hereof, simpler, embedded computing applications may utilize standard memory controllers including cash management and memory component interfacing features but may bypass virtual memory management features within the same memory controller component. Rather, features and aspects hereof intercept memory accesses generated by the memory controller for address translation features and perform simpler address substitution to apply an appropriate translated address to the system bus.