Abstract: A web-based system, method and program product are provided for adding content to a content object stored (e.g., a custom compilation or prepublished work) in a data repository as a group of hierarchically related content entities. Each noncontainer content object is preferably stored as a separate entity in the data repository. Each content entity is also stored as a row in a digital library index class as a collection of attributes and references to related content entities and containers. As the user selects desired objects for inclusion in a content object, the system arranges the objects hierarchically, e.g., into volumes, chapters and sections according to the order specified by the user. The system then creates a file object (e.g., a CBO) defining the content object that contains a list or outline of the container and noncontainer entities selected, their identifiers, order and structure. This file object is stored separately in the data repository.

Abstract: Out of a lot of fonts, the desired font is quickly found. For this purpose, out of a plurality of portions constituting a character displayed in a partial image retrieval area, the desired portion is selected. A retrieval area is clicked by a user, to retrieve a font on the basis of the selected portion. A list of the results of retrieval is displayed in a retrieval result area. Even if a font name is not memorized, a desired font can be found.

Abstract: Help functionality is described for integrating help information into a primary application in a just-in-time fashion. The help functionality can perform this task by providing a see-through panel which is presented on top of an application interface provided by the primary application. A user can move a mark on the see-through panel to identify features of the application interface concerning which he or she may have questions. The help functionality responds by presenting potentially context-sensitive help information to the user in audio mode and/or visual mode. If the visual mode is selected, the help functionality can present the help information on the see-through panel itself, and/or can dynamically move parts of the application interface to accommodate the display of the help information. The help functionality can supply the help information from a local source and/or a remote source, in an automated manner and/or a manual manner (e.g., using a remote human assistant).

Abstract: A power tool control system allows a user to operate a power tool through a graphical user interface communicatively coupled with a non-contact measurement and alignment device. The graphical user interface correlates user engageable selectors with a logically related menu of power tool setting options displayed on a display screen in a high quality and easily readable format. The non-contact measurement and alignment device uses one or more lasers to determine power tool settings and establish proper alignment based on user needs. The power tool control system further enables stud detection and visual indication of stud location.

Abstract: A user interface (UI) in the form of a single navigable window enables a user to navigate to and between multiple different functionalities that are provided by a single application program. Novel use is made of a navigation model that manages the user's navigation activities to and between the different functionalities. Navigation instrumentalities enable the user to navigate among the different functionalities and include links to each of the different functionalities as well as browser-like navigation buttons. Context-sensitive command sets can also be provided along with the single navigable window. The context sensitive command sets include commands that automatically change as the user's computing context changes, e.g. as the user moves from functionality to functionality. The single application can be defined as a software platform that is extensible to receive and incorporate different functionalities.

Abstract: An apparatus, computer program, and method are disclosed for generating computer executable code. The code is compiled from a data set, and the data set is compiled by selecting a link within a comments portion of a text editor portion of a program. The data set can then be inserted into an applications program to form the computer executable code. The comments portion involves a line of text that is preceded by a comments designator and succeeded by at least one link word that is adapted for modification by an on-screen pointer. Any changes to the link word via a graphical user interface will correspondingly change fields within a data set, which preferably is also displayed within the same window as the comments portion. The fields of bits within the data set can be used to program a hardware device or system. One example of such a device is a programmable device, or general purpose interface circuit that is juxtaposed between, for example, a computer and a peripheral device.

Abstract: A method and system for storing, navigating and accessing files within an operating system through the use of a graphical thumbnail representing the video display of the active document within the active application, and organized chronologically by the most recent file ‘captured’. Filenames, application names and thumbnail filenames are stored in an indexed file. The indexed file can consist of every document and application used during a session or categorically defined by project or tasks or personal preference. This also stores the application name and path eliminating the need to remember which application last edited the file and where the application is located.

Abstract: A system and method for improved scroll mouse operation is presented. A user operates a computer mouse, which includes a scroll ring that functions as a middle mouse button. During operation, the user configures a scroll suppression manager to discard a particular number of scroll commands when the user moves the computer mouse's scroll ring. The user specifies a number of scroll commands to discard when the computer mouse's pointer location is positioned over particular mouse-over conditions, such as a web page link or a drop down menu. Once the scroll suppression manager has discarded the user-specified number of scroll commands, the scroll suppression manager processes subsequent scroll commands until the user stops scrolling or the user selects an object on the user's computer screen.

Abstract: A method of managing a casual storage field comprises the steps of: receiving a plurality of information elements from one or more application programs, each information element including one or more data items; retaining the received information elements in the casual storage field; displaying a state of the casual storage field and the retained information elements; and handing over, in response to a user request, one or more of the retained information elements to an application program. The casual storage field can receive an information element from another application program, display the received information element in the display region of the casual storage field, and hand over in response to a user instruction, the information element to yet another application program.

Abstract: Content is transferred from one computer resource to another computer resource by receiving a first insertion point or replacement area from a first user interface to a destination computer resource, receiving an enablement to perform automatic paste operation, switching to a user interface to a source computer resource, receiving a user selection of content from said source user interface, and automatically copying the selected content to a transfer buffer and to the designated insertion point(s) in the destination computer resource. Each time source content is selected, a number of source reference data items such as author, publication date, and source file name or network address are captured and stored. The stored source reference identifies may then be used to automatically generate a monitor report containing this information, which is then provided to an online learning administrator or instructor.

Abstract: A system and method for facilitating user entry of a manually-adjustable data setting in an aircraft cockpit normally presents an image of the data setting on the display at a predetermined size. When the user commences to manipulate a control for manually adjusting the data setting, the imaged data setting on the display is automatically enlarged to a predeterminately enlarged size to thereby unambiguously direct the user's attention to the imaged data setting to be adjusted. The imaged data setting on the display is returned from its enlarged size to its normal size when user manipulation of the control has ceased, preferably a predetermined time interval after such user manipulation has ceased.

Abstract: Generally described, a method is provided for use in a computer system that allows users to navigate quickly through multiple applications. In accordance with the method, when the computer receives a signal from the user, it extracts a preview representing a screen shot for each window open within the operating system. It then displays the preview, a description, and an icon for the next window in the activation hierarchy and a description and an icon for the remaining open windows. In other embodiments, the previews for all open windows with corresponding descriptions and icons are displayed utilizing several different arrangements. The computer then receives a designation from the user of the next window he or she wants to make active and brings to the foreground the top level window corresponding to the selection.

Abstract: A methodology for displaying a website on a hand held display device (HHDD) is disclosed. The present invention comprises an Image Modification Program (IMP) and a Navigation Program (NP). The IMP analyzes the webpage HTML to determine if an image is present and if the image exceeds the allotted image display space on the HHDD display screen. The IMP calculates the required number of x-axis and y-axis divisions and fragments the image accordingly. The IMP displays the reduced web page on the HHDD, but replaces the reduced image with a fragment from the fragmented image. The fragment is displayed at the intended resolution allowing the user to view a portion of the image at full size, as opposed to the whole image at a reduced size. The NP of the present invention allows the user to move from one fragment to another. An alternative embodiment utilizing a proxy is also disclosed.

Abstract: A system and process for providing adaptable controls to computing applications to facilitate interaction by an operator with computing application content is provided. The present invention provides a system to update the control parameters remote to the computing application to reflect changes in operator's preferences. In an illustrative implementation, these dynamic controls may take the form of an add-on toolbar having drop down menus that have the form of panes. In operation, the computing application launches and retrieves the parameters of these controls through messaging from a remote server computer. When launched, the computing application will display the add-on toolbar, maintaining Web-in-Web panes, having the latest updated parameters (i.e. content, look, and feel of the toolbar and panes) as found on the remote server computer. These parameters may be changed by the operator to reflect changes in their content or feature preference.

Abstract: A data display comprises a window that shows a tree map display having menu information surrounding a field array of differently sized and colored or shaded areas that represent product offering possibilities that conform with user criteria entered through the surrounding menu windows. A Web site that uses the display technique may receive user criteria and retrieve a portion of collected data and display it to the user, so that the retrieved data describes a data subset that is responsive to the user criteria. The retrieved Web pages may be viewed to facilitate review of product offering information, and to facilitate purchase decisions that are transmitted from the Web site visitors.

Abstract: Administration of keyboard input in a computer having a display device supporting a graphical user interface (“GUI”), including storing keyboard input intended by a user for a second widget when keyboard focus is on a first widget, wherein the first widget receives no keyboard input; changing keyboard focus to the second widget; and providing the stored keyboard input to the second widget.

Abstract: An interface for a programmable logic device having a non-volatile memory where a portion of the non-volatile memory is user accessible is provided. A megafunction provides the electronic circuit designer with interface protocol options for the user accessible portion of the non-volatile memory block. The circuitry associated with the user selected interface is then programmed into the programmable logic device.

Abstract: Programmable logic circuitry includes level-sensitive latches as at least some of the data storage elements. At least some of the latches are enabled by one phase of a clock signal, and at least some others of the latches are enabled by the other phase of the clock signal. Accordingly, these latches collectively have two-phase operation. These two-phase latches may replace at least some single-phase, edge-triggered flip-flops in a user's logic design, and may thereby increase the speed at which the user's logic can be operated. Methods for converting a single-phase, edge-triggered flip-flop design to a logically equivalent design using at least some two-phase latches are disclosed.

Abstract: One embodiment of the present invention provides a system that optimizes a logic network. During operation, the system receives a first logic network which defines a logical function, wherein the first logic network cannot be efficiently optimized by directly using an optimization process that preserves the logical function. Next, the system creates an intermediate logic network based on the first logic network, wherein the intermediate logic network defines an intermediate logical function which is different from the logical function, wherein the intermediate logic network can be efficiently optimized using the optimization process. The system then optimizes the intermediate logic network using the optimization process to create an optimized intermediate logic network. Next, the system creates an optimized first logic network based on the optimized intermediate logic network. In this way, the system indirectly uses the optimization process to efficiently optimize the first logic network.

Abstract: Methods and apparatus are provided for implementing a programmable device including a processor core, a hardware accelerator, and secondary components such as memory. A designer efficiently selects one or more code sequences for acceleration. A hardware accelerator is generated with multiple master ports to allow efficient access to memory. Profiling information can be provided to allow efficient selection of code sequences.

Abstract: A logic design development tool including a converting unit configured to convert a plurality of different circuit design languages into a common intermediate format, and an executing unit configured to execute the common intermediate format so as to perform a design simulation of a circuit defined by the circuit design languages.

Abstract: Method and apparatus for approximating the average critical area of a layout or layout region, involving summing, over all the object segments of interest, respective critical area contribution values that are dependent upon particular layout parameters of the objects, each of the contribution values being representative of a plurality of defect sizes, and being defined such that for each defect size in the plurality of defect sizes, and for a particular defect type, the contribution values collectively count all critical areas arising due to the object segments of interest only once.

Abstract: A method, a computer program, and an apparatus are provided for generating circuit energy models for a macro using clock gating inputs. Circuit energy models are used to estimate system power consumption. The present invention enables circuit energy models to be created for macros that contain clock gating inputs. Power tables are created based upon the macro's input switching factor percentage and the clock activation percentage. These power tables are generated from a minimum number of power simulations. By using clock activation percentage as a parameter accurate energy tables are produced.

Abstract: A system and method for estimating propagation noise that is induced by a non-zero noise glitch at the input of the driver circuit. Such propagation noise is a function of both the input noise glitch and the driver output effective capacitive load, which is typically part of the total wiring capacitance due to resistive shielding in deep sub-micron interconnects. The noise-driven effective capacitance solution provided herein also estimates the propagation noise induced by a non-zero noise glitch at the input of the driving gate. Gate propagation noise rules describing a relationship between the output noise properties and the input noise properties and the output loading capacitance are used within the noise-driven effective capacitance process to determine the linear Thevenin model of the driving gate. The linearized Thevenin driver model is then employed to analyze both the propagation noise and the combined coupling and propagation noise typically seen in global signal nets.

Abstract: Method and system for evaluating design costs of an integrated circuit are disclosed. The method includes choosing a design point for evaluation, dividing circuit specifications of the design point into at least two groups comprising a first group of specifications and a second group of specifications, computing a first set of design costs for the first group of specifications, estimating a second set of design costs for the second group of specifications using a predetermined set of reference costs, and determining a design cost of the design point using the first set of design costs and the second set of design costs.

Abstract: A design of an integrated circuit device, in which locations of power wires and memory/logic circuitry are known, is analyzed by at least: identifying intersections of power wires with one another, for power wires that are electrically connected to one another through vias; segmenting power wires, at their intersections; preparing estimates of conductance of vias and wire segments in the form of conductance matrix G; and preparing estimates of current I at each intersection based on power consumed by surrounding circuitry, and current vector “I” and conductance matrix “G” are used to solve for voltage drop ?V, in a matrix equation G?V=I, and the voltage drop is displayed, to allow a human to make changes in the design. Pins of unconnected hard macros are temporarily connected to their closest wires, and current therethrough is included in the estimates.

Abstract: A method for verifying trace widths of a printed circuit board (PCB) layout includes the steps of: loading a PCB layout document from a database; defining a verifying area for a PCB layout specified in the PCB layout document; receiving preset design rules; creating a data structure, and loading information on traces in the verifying area into the data structure; selecting an unverified trace from the data structure; selecting an unverified segment from the selected trace; verifying the selected segment by comparing a width of the selected segment with the rules, and determining whether the selected segment satisfies the rules according to the comparison result; and annotating design rule check (DRC) information if the segment does not satisfy the rules. Other segments of the selected trace and other traces are verified by repeating appropriate of the above-described steps. A related system for implementing the method is also disclosed.

Abstract: A method of estimating a wiring complexity degree in a semiconductor integrated circuit with a multi-layered wiring, which has a wiring structure including at least two layers or more, in laying signal wirings, includes a step of predicting a power-supply wiring space used in the semiconductor integrated circuit, a step of dividing the predicted power-supply wiring space onto respective wiring layers, and a step of estimating a complexity degree at a time of laying signal wirings, based on the predicted power-supply wiring space and a wiring specification in respective wiring layers every wiring layer.

Abstract: A system and method for performing a timing analysis on virtual component blocks or other circuit models is provided wherein functional information obtained from the circuit's control inputs and their useful combinations is used to improve accuracy. The control inputs and data inputs for a circuit block are identified. Each functionally meaningful or useful control input combination is applied to the circuit block, and the topological delay for the data inputs are determined only along the paths that are not blocked by the control inputs. The delays along paths that are blocked are ignored. The analysis is further augmented by determining the topological delay for all paths originating at control inputs, without regard to blocking of paths, so as to reduce the chance for possible underestimation of delays from the data inputs.

Abstract: A digital storage medium for storing electronic data for use with a clock tree design tool to design a clock distribution network within an integrated circuit. The electronic data implements a library of shim cells, wherein each of the shims cells represents a physical embodiment of a different clock driver cell such that all of the shim cells in the library are interchangeable in the clock distribution design without requiring any change in the placement or routing within the integrated circuit to maintain compliance with design requirements for the integrated circuit. Each cell within a library represents a structure that introduces a particular delay time in the clock signal. The library contains cells having a range of delays that span a range that is sufficiently large to deal with the range of clock skews typically encountered during integrated circuit design.

Abstract: Electronic Design Automation tools are used to aid in the design and verification of integrated circuits. As part of the verification process, circuit designs are analyzed with respect to their timing performance. Timing analysis is susceptible to variation in circuit components due to fabrication process variation. Process variation is introduced as worst-case conditions or statistical probabilities. More accurate process variation is modeled by for timing sensitivity with Parametric Elmore Delay. Parametric Elmore Delay introduces effects on circuit components as parameters in the conventional Elmore Delay definition to model fabrication process variation in the timing analysis. Delay variance demonstrates sensitivities to process and design factors. Parametric timing analysis is used to anticipate fabrication yield and identify potential improvements in the design or fabrication process.

Abstract: An electrical wiring structure and method of designing thereof. The method identifies at least one wire pair having a first wire and a second wire. The second wire is already tri-stated or can be tri-stated. The wire pair may have a same-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum same-direction switching probability. Alternatively, the wire pair may have an opposite-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum opposite-direction switching probability. The first wire and the second wire satisfy at least one mathematical relationship involving: a spacing between the first wire and the second wire; and a common run length of the first wire and the second wire.

Abstract: A method is disclosed whereby an inexpensive integrated circuit is provided for use in high volume electronic consumer devices of different makes, wherein each different make must perform a different special function. A common function required in all the different makes is realized in a substantially non-customizable portion. A dense mask-programmable portion is provided for realizing a special function. Interface circuitry is provided that enables an external FPGA to perform the special function at system operating speeds during system development. After system development, the circuitry implemented in the external FPGA is technology-mapped to the mask-programmable portion. A single mask is fashioned such that versions of the integrated circuit are produced with their mask-programmable portions customized to perform the special function.

Abstract: This method for decoupling capacitance analysis improves upon existing techniques to attempt to give a more accurate representation of the power supply fluctuations on a chip while keeping runtime comparable. This method employs the following techniques; a) a method for descending through hierarchy and dividing the design into a variable sized grid; b) an algorithm to determine which grid locations of a design don't have enough decoupling capacitors for all of the devices in that grid location; c) an algorithm to determine which grid locations are subject to harmful neighboring effects; and d) a method to display the results of the calculations in a graphical manor to allow easy identification of problem areas.

Abstract: Disclosed are techniques and apparatus for providing metrology or inspection targets in-chip. That is, targets are integrated within the product device or die area. In general terms, the present invention provides techniques for enabling inspection or metrology on targets within the die or active area. Said in another way, target structures are inserted within the die or active area. In one embodiment, a set of rules are provided for integrating test structures within the die. For example, these rules may be implemented by one or more design engineers or by place-and-route tools which automatically generate the die layout pattern and thereafter insert the target structures into the die layout pattern based on these rules. Location data of each target is then retained during the layout generation and provided to one or more inspection or metrology tools and/or metrology engineers so that each target may be found and then inspected or measured.

Abstract: The present invention provides a method and apparatus for managing a large number of associated interconnects within an integrated circuit involving a modular approach to the macro cell layout. In particular, internal signal paths are created within each macro cell that permit connections to other macros by abutting these macros adjacent to one another. Moreover, these internal signal paths permit efficient distribution of a common source signal to each of such connected macros. The layout of the internal macro cell signal paths of the present invention also permits each of these macros to be reflected about its Y-axis, thereby increasing its versatility in being utilized in various circuit designs.

Abstract: Methods and arrangements to gang differential clock signals to attenuate pin-to-pin output skew for a clock driver are disclosed. Embodiments may comprise a pattern of conductors to interconnect output pins for differential clock signals with termination resistors. The pattern of conductors comprises a group of conductors for a positive clock (p-clock) signal and a group of conductors for a negative clock (n-clock) signal. The conductors for the p-clock signal intersect at a gang point between the output pins and pads for the termination resistors. Similarly, the conductors for the n-clock signals intersect at a gang point between the pins and the pads. In many embodiments, the distance between the pins and pads may be approximately 120 mils. In further embodiments, the distance may be longer or shorter than 120 mils. Other embodiments are disclosed and claimed.

Abstract: A system for adding advanced instructions to a microprocessor includes a language for formally capturing the new instructions and a method for generating hardware implementations and software tools for the extended processors. The extension language provides for additions of VLIW instructions, complex load/store instructions, more powerful description styles using functions, more powerful register operands, and a new set of built-in modules. The method is capable of generating fully-pipelined micro-architectural implementations for the new instructions in the form of synthesizable HDL descriptions which can be processed by standard CAD tools. The method is also capable of generating software components for extending software development tools for the microprocessor with new instructions.

Abstract: A pattern forming method includes the steps of checking a wide range size change characteristic for each device in a case of using a device group used for forming a pattern; dividing a design pattern size into a smaller area than a standard distance to which a predetermined size change is caused, when the pattern is formed on a sample by using the device group; acquiring correction information of the size of the pattern of each the small area by using the size change characteristic; and forming a desired pattern based on the acquired correction information.

Abstract: A system for the integrated archiving, restoring, purging, importing and exporting of semiconductor wafer data, the system including a data acquisition system for acquiring scan data from differing types of semiconductor wafer scanning tools such as wafer dimensional tools, wafer inspection tools, and wafer nanotopography tools, a buffer system for providing temporary storage for scan data transmitted over a network from the data acquisition system and for providing fault tolerance, a server system for providing storage for the scan data transmitted from the buffer system and converting the scan data into a format used by and stored in a database management system; and an analysis system client station including a display and communicating with the server system over the network, the analysis system and the server system managing the purging, archiving, restoring, importing and exporting of scan data.

Abstract: An integrated circuit (IC) having an IC floorplan silhouette-like power supply net, and a computer executable Sea of Supply (SoS) Electronic Design Automation (EDA) tool for automatically designing same. An IC floorplan silhouette-like power supply net preferably includes both a Sea-of-Supply (SoS) power net and a Sea-of-Supply (SoS) ground net each exclusively occupying different layers of the two lowermost metal layers of an interconnect structure overlying its underlying transistor embedded silicon based structure. The SoS nets are the logical complement of preferably all the exempt areas of an IC floorplan.

Abstract: A final mask layout (20?) is produced by producing a provisional auxiliary mask layout in accordance with a predefined electrical circuit diagram and converting it into the final mask layout (20?) with the aid of an OPC method. Before carrying out the OPC method, with the provisional auxiliary mask layout (100), firstly a modified auxiliary mask layout (100?) is formed by arranging at least one optically non-resolvable auxiliary structure (130) between two mask structures (110, 120) of the provisional auxiliary mask layout (100). The optically non-resolvable auxiliary structure (130) is positioned between the two mask structures (110, 120) in a manner dependent on the structure size (B1, B2) of the two mask structures, (110, 120). An eccentric offset (V) of the optically non-resolvable auxiliary structure (130) between the two mask structures is effected in the case of differing structure sizes (?B) of the two mask structures.

Abstract: In determining a relative position between a chip lattice including rectangular cells, each of which has a size of a chip to be formed on a substrate and an effective area on the substrate, one representative cell in the chip lattice is divided into a plurality of partial areas in accordance with an existing area, of a representative point of the effective area, in which chip sets trimmed from the chip lattice with the effective area are identical. A partial area corresponding to a chip set including a maximum number of chips is specified from the plurality of partial areas, and the representative point is set in the specified partial area.

Abstract: The present invention is directed to a method for conversion of an integrated circuit design into a set of masks for fabrication of an integrated circuit that optimizes use of an edge based image transfer mask process.

Abstract: A system for building software use cases and related state diagrams based on a model of business activities is provided. The system comprises the model of business activities and a computer based modeling tool that is used to compose the use cases and the related state diagrams. The system includes an integration component, which maps the business activities to use cases, and a graphical user interface, which illustrates the relationships among use cases and the relationships between use cases and business requirements. A state diagram component maps business activities to assist in the preparation of state activity diagrams. The model of business activities enumerates business activities and associates each business activity with the business domain in which the business activity is normally conducted. The integration component provides a list of selectable business activities to the graphical user interface from which to compose use cases and state activity diagrams.

Abstract: Shown is an improved method and system for implementing and building messages, such as HL7-based messages. Messages are constructed in a format-independent manner, in which a message is built by instantiating and linking Java classes. Metadata for the message specifications are used to construct the Java class libraries. Signature of the classes automatically cause the messages to be constructed with correct syntax, structure, and restrictions. Thus, the correctness of the constructed messages can be enforced at compile time. Moreover, a developer can construct a specification-specific message without having to know XML.

Abstract: A method and system for creating reusable software components in the form of linkable programming languages. Linkable programming languages enable programmers to model the natural syntaxes of different domains and extend these languages in a distributed manner. In this way, the present invention brings many of the properties of natural language to the engineering of software.

Abstract: An application software generator automatically generates an application software unit. The application software generator includes an application composer that combines components extracted from a component repository with an application framework to generate the application software unit. Each component in the component repository includes a component shell, a component interface and a component core. The application framework includes configurable parameters that determine how the application software unit is generated and operates. The configurable parameters can be entered by a user using a graphical user interface. The user can be assisted using a wizard format. The application framework also provides connectivity between components so that they can pass messages to one another. The connectivity can be, for example, by a message bus or event registry and event dispatch. Components themselves can be automatically generated using the application software generator.

Abstract: A system, method and computer-readable medium supports a feature that predicts a selection based on history of use and uses this information to pre-select an item in a list for syntax completion in a source program editor.

Abstract: An exchange infrastructure for message-based exchange and integration of a collection of heterogeneous software components is disclosed. The exchange infrastructure includes a repository for storing design-time collaboration descriptions of a plurality of software components, and a directory for storing configuration-specific collaboration descriptions of a runtime system landscape. The exchange infrastructure further includes a runtime engine configured for message-based exchange of information based on the configuration-specific collaboration descriptions. At runtime, the runtime engine receives messages, and resolves intended or required receivers based on message content and parameters provided by the configuration-specific collaboration descriptions from the directory.