Abstract: A method and apparatus for providing clock phase alignment in a transceiver system are disclosed. Circuits are provided for providing clock phase alignment to adjust and align the phase between clock domain boundaries and for maintaining alignment of multiple outputs signals.

Abstract: In some embodiments an apparatus and method may comprise a plurality of lanes between two clock domains, each lane comprising circuitry to generate a first signal when the lane may lose cycle coherency with other of the plurality of lanes, generate a second signal to signify a lane has been delayed, and a control circuit coupled with the plurality of lanes to add latency only to lanes that did not generate a second signal if the control circuit detects a first signal from any of the plurality of lanes.

Abstract: Methods and apparatus are provided for configuring and generating a sequence of discrete output signal values. A microcontroller writes output signal values to memory and provides address and timing information to a streaming output peripheral. The streaming output peripheral uses the address and timing information to read output signals values from memory and provide the output signal values in a clock cycle accurate manner.

Abstract: An apparatus and method are disclosed or producing a network of composite clocks with optimized stability characteristics from individual clocks that are part of a network wherein not all clocks are in communication with each other. By communicating information among the clocks in the network, each clock can construct its best estimate of composite time based upon all clocks in the network. The clocks that do not directly communicate with a specific clock are partitioned into disjoint groups for which the interclock measurements are compressed by a neighboring clock into a single composite clock. Each clock measures its time against the raw time of the clocks with which it is in direct communication and also inputs to its filter correction data for each of these composite clocks. The composite clock algorithm employed is dependent on the stability characteristics of the clocks in the network.

Abstract: A circuit and a method for aligning transmitted data by adjusting transmission timing for a plurality of lanes. The method includes utilizing different initial values to reset a count value corresponding to a lane when a plurality of COM symbols are detected on the lane, utilizing an increment value to increase the count value corresponding to the lane when a COM symbol is not detected on the lane, and utilizing a plurality of count values corresponding to the lanes to align transmitted data of the lanes when a COM symbol is not detected on the lanes within a predetermined period of time.

Abstract: Systems and methods for recovering data from a backup copy and for backing up data. When a recovery operation is initiated, recovery items are selected from backup groupings of the client. The recovery items can include backup groupings, writers, and writer components. After the recovery items are selected, backed up metadata for each selected writer is retrieved from the backed up data. The backed up metadata is then queried to identify the restore method of the writer. The data of the client is then recovered by implementing the restore method included in the backed up metadata of the writer. During a backup operation, some of the backup groupings, as well as the content of the backup groupings, can be individually selected for backup. In both backup and recovery, a visual indication may be provided to identify individual selectability.

Abstract: When a primary server executing a task fails in a computer system where a plurality of servers are connected to an external disk device via a network and the servers boot an operation system from the external disk device, task processing is taken over from the primary server to a server that is not executing a task in accordance with the following method. The method for taking over a task includes the steps of detecting that the primary server fails; searching the computer system for a server that has the same hardware configuration as that of the primary server and that is not running a task; enabling the server, searched for as a result of the search, to access the external disk device; and booting the server from the external disk device.

Abstract: A method for sharing a storage device amongst a plurality of computers while providing data integrity in the storage device is presented. A computer is registered for a reserved access type with the storage device by storing a computer identifier in the storage device. Access to the storage device is provided to the registered computer dependent on the registered computer's stored identifier and the reserved access type. Upon loss of knowledge of the stored identifier in the shared storage device by the registered computer, the computer replaces the previous identifier for the computer stored in the shared storage device with a new identifier. The registered computer may be a currently registered computer or a previously registered computer.

Abstract: Systems, methods, and machine-readable media are disclosed for routing communications to a storage area network (SAN). In one embodiment, the machine-readable media includes first program code to determine a route path through a gateway to a SAN for each of a plurality of addresses of an interface of a server. The first program code determines the route path by applying an algorithm to one or more numerical values associated with the address. The machine-readable media includes second program code to configure the gateway with the route paths.

Abstract: A system such as a Web-based system in which a plurality of computers interact with each other is monitored to detect online an anomaly. Transactions of a service provided by each of a plurality of computers to another computer are collected, a matrix of correlations between nodes in the system is calculated from the transactions, and a feature vector representing a node activity balance is obtained from the matrix. The feature vector is monitored using a probability model to detect a transition to an anomalous state.

Abstract: Method, system and computer program product for reporting and recovering from uncorrectable data errors in a data processing system using the Advanced Technology Attachment (ATA) or the Serial ATA (SATA) protocol. The invention utilizes the data scrubbing functionality of SCSI hard drives to provide a higher level of data integrity in an operating system implemented RAID environment. If an uncorrectable data error is found on a hard drive during a background data scrubbing operation, information concerning the data error is logged in a S.M.A.R.T. (Self Monitoring Analysis and Reporting Technology) error data structure. When the host operating system identifies the uncorrectable data error during normal operation, a Host Array Manager issues a Write Command to write the data from a redundant drive after the defective Logical Block Address (LBA) has been reassigned.

Abstract: A method for storing data includes writing the data to a temporary storage location and buffering a mirror request to copy the data from the temporary storage location to a mirror. Once all the data is present, the validity of the data is determined. If the data is valid, the mirror request is executed. Otherwise, the mirror request is deleted.

Abstract: A system, method, and computer program product for recovering from data errors. In a SCSI hard drive system, when a unrecoverable data error condition is encountered, the logical block address is reassigned using information provided by the data scrubbing functionality of the SCSI hard drive.

Abstract: A system to load test a computer system is provided. The system comprises a test script to generate transactions including a basis transaction, the basis transaction operable to initiate a conversation with a stateful enterprise java bean, and a non-basis transaction. The system also comprises a forecast and a transaction iteration calculator, the transaction iteration calculator operable to determine how often the non-basis transaction executes relative to the basis transaction. For a non-basis transaction having a forecast less than the forecast of the basis-transaction, the non-basis transaction executes once if the number given by a randomly selected number between zero and the basis transaction forecast is less than the forecast of the non-basis transaction forecast and zero times otherwise. For a non-basis transaction having a forecast more than the forecast of the basis-transaction, the non-basis transaction may execute according to another calculation. A script controller is also provided.

Abstract: An automated method, system, and computer program for troubleshooting the inability of programs installed upon two computers interconnected by wired or wireless linkages to share or manipulate sharable information includes the following steps: On a first computer, tests are performed to see if hardware or software elements on that computer and essential to sharing or manipulating sharable information is properly installed or configured and also to see if information can actually be sent between the two computers; then, if possible, testing is initiated or performed to see if hardware or software elements on the second computer essential to sharing or manipulating sharable information are also properly installed or configured; and then the results of this testing is reported.

Abstract: A method, apparatus, and computer instructions for analyzing data from a crash of the data processing system. A portion of the memory in the data processing system is preserved in response to the crash of the data processing system. The data processing system is rebooted with an environment suited for analyzing trace data in the portion of the memory.

Abstract: A storage controller for a storage system in which there are multiple storage devices and a method for recording diagnostic information are provided. The storage controller includes a storage device manager which has means for allocating a storage device in the storage system for storing diagnostic data. The storage controller also includes means for generating diagnostic data regarding the operation of the storage controller. Two buffers are used for alternately recording and writing batches of diagnostic data to the allocated storage device. The allocated storage device may be a storage device which is normally reserved for disaster recovery in the storage system.

Abstract: A method and system are provided for use in a computer collaboration environment. In one example, the method includes identifying that a resource should be failed over from one computer to another computer within the environment. A history of the resource's execution within the cluster is examined, and the resource is failed over only if a risk assessment based on the history indicates that a risk level of loading the resource does not exceed an acceptable risk threshold.

Abstract: A method and apparatus using a set of registers for indicating multiple error levels in a data processing system, wherein a register allows software to reprogram or redefine the error level to another desired error level. One embodiment of the invention involves a method for indicating errors in a data processing system with multiple error levels, indicating that an error corresponds to one of the multiple error levels, representing the error with a set of memory cells, and changing the error level of the error to another error level of the multiple error levels. A second embodiment of the invention involves a data processing system or an error log system, having an associated error level chosen from a plurality of error levels for an error. The data processing system or error log system includes a set of memory cells, with a primary error log to record the error, at least one error enable register that can be read and written to redefine the error level of the error to one of said plurality of error levels.

Abstract: In one embodiment, an apparatus comprises a plurality of core logic blocks, a plurality of first event blocks, and a second event block. Each of the plurality of core logic blocks is configured to generate one or more indications of one or more events. Each first event block of the plurality of first event blocks is coupled to a respective core logic block of the plurality of core logic blocks to receive the one or more indications from the respective core logic block. Each first event block comprises at least one register configured to record which events have been indicated by the respective core logic block. Coupled to the plurality of first event blocks, the second event block is configured to initiate one or more actions responsive to one or more events detected in one or more of the plurality of first event blocks.

Abstract: A system for controlling power sources of motherboards under test through networks includes a central server (1), a serial device server (3), a bus distributor (4), a number of power controllers (5), and a number of testing computers (8). The central server sets testing parameters, and transmits instructions regarding turning on or off power sources of the testing computers to the serial device server, in order to control the power sources of the testing computers. The serial device server converts the instructions into serial instructions, and generates corresponding serial signals. The bus distributor distributes an address for each power controller, receives the serial signals, and transmits the serial signals to corresponding power controllers. Each power controller turns on power sources of corresponding testing computers in which motherboards under test are installed according to the received serial signal. A related method is also disclosed.

Abstract: In some embodiments, an apparatus to implement redundancy for failure masking in memory is disclosed. The apparatus comprises a built-in self test (BIST) log to store BIST data representing faulty columns of a memory, a redundancy configuration logic to generate one or more select signals based on the BIST data, an input shifter to map input data to one or more redundant columns of the memory, based on the one or more select signals, to avoid the faulty columns, and an output shifter to map output data from the one or more redundant columns of the memory, based on the one or more select signals, by bypassing the faulty columns. In one embodiment the memory is a static random access memory (SRAM). Other embodiments are also described.

Abstract: A method for testing a memory includes a test pattern generated by a hash algorithm. The test pattern is written into the memory and then is read from the memory. Next, the hash algorithm generates a signature using the test pattern read from the memory. Subsequently, the memory is verified by comparing the signature to a reference signature.

Abstract: A method and apparatus for determining the characteristics of a communications channel within a high speed memory system includes generating a first signal having a known and repeating pattern and generating a second signal having a pseudo-random pattern. The first and second signals are combined to produce a combined signal. The combined signal is transmitted over a communications channel of a memory system and is received by the memory devices of the memory system. Each memory device removes the second signal from the received combined signal to produce a received first signal. Parameters associated with transmitting and receiving may be adjusted by examining the pattern of the received first signal to determine if it has the known pattern of the first signal. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: A method and apparatus for identifying defective cells in a memory array includes receiving a request for accessing an address and analyzing the address to determine when the address matches an address stored in a temporary memory array. When the address does not match any address stored in the temporary memory array, a wait instruction is sent to a processor and the address is analyzed to determine which portion of compressed data stored in a map memory array to decompress. The map memory array stores data containing compressed addresses of defective cells in a first memory array. The portion of compressed data is then decompressed to provide expanded data when the address does not match any address stored in the temporary memory array. The expanded data are then written to the temporary memory array, and the expanded data are compared to the address to determine when the address corresponds to an expanded datum of the expanded data.

Abstract: An integrated circuit device having a test sequence generator, first and second transceivers and a test sequence analyzer. The test sequence generator generates a test data sequence in response to a test mode selection. The first transceiver receives the test data sequence from the test sequence generator and is configured in a loopback mode to transmit and receive the test data sequence. The second transceiver receives the test data sequence received by the first transceiver and is configured in a loopback mode to transmit and receive the test data sequence. The test sequence analyzer determines whether the test data sequence received by the second transceiver matches the test data sequence generated by the test sequence generator.

Abstract: A circuit device having data retention latches utilizes a test interface and system test controller to control one or more components of the circuit device to ensure proper conditions for testing the data retention latches. The data retention latches each include a scan component that is part of a scan chain, a first latching component that is powered in a first voltage domain and a second latching component that is powered in a second voltage domain, where one of the voltage domains can be effectively shut down when the circuit device is placed in a low-voltage mode. The system test controller can control a scan controller used to scan test data in and out of the scan chain. The system test controller further can control a power controller used to manage a power down sequence and a power up sequence so as to ensure that the data retention latches are not placed in spurious states.

Abstract: An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC.

Abstract: An integrated circuit including test circuitry, the test circuitry including a counter for counting clock signals and having an output for providing a control signal. The counter being arranged to have an internal state, and the counter being arranged to change the control signal on the internal state of counter reaching a predetermined value.

Abstract: Built-in self-test (BIST) devices and methods are disclosed. A BIST section (100) according to one embodiment can include a built-in seed value memory (150) that stores multiple seed values. In a BIST operation, a seed value can be transferred from a built-in seed memory (150) to a test pattern generator (106) to generate multiple test patterns for scan chains (104-0 to 104-n). Successive seed values can be transferred to generate multiple test patterns sets at a clock speed and/or to achieve a desired test coverage.

Abstract: A match circuit connected to a bus carrying data is described. In one embodiment, the match circuit comprises logic for activating a match_mm signal when a selected N-bit portion of the data matches an N-bit threshold for all bits selected by an N-bit match mask (“mmask”) and logic for activating a match_OR signal when at least one of one or more designated bits of the selected N-bit portion of the data is a logic 1 or if there are no designated bits.

Abstract: Error detection methods, systems and medium are provided. The error detection method may comprise processing error conditions associated with transactions in a manner that may enable error source identification. The system may comprise a plurality of nodes of components. The nodes may include storage elements to record an error condition indicative of whether a component provided an indication of detecting an error in response to processing the transaction.

Abstract: Disclosed is a method and erasure FEC decoder for correcting a pattern of errors by a two-dimensional decoding, the pattern of errors comprising at least two codewords in both a first and a second dimensions with a number of errors in common higher than the capacity of the code which is used for decoding. The method comprises the steps of: performing a full capacity decoding along the second dimension for removing possible false corrections introduced by a previous decoding performed along the first dimension; performing a reduced-capacity decoding along the first dimension, for identifying errored codewords along the first dimension; performing a full capacity decoding along the second dimension with disabled correction feature for identifying errored codewords along the second dimension; detecting the error coordinates from the information from steps b) and c); and correcting the detected pattern of errors.

Abstract: A method of providing forward error correction for data services uses a parallel concatenated convolutional code which is a Turbo Code comprising a plurality of eight-state constituent encoders wherein a plurality of data block sizes are used in conjunction with said Turbo Code. A variation uses the method in a cellular radio system. Another variation uses the method in both forward and reverse likes of a cellular radio system.

Abstract: A burst error-correcting capability is largely improved. At least the even-number row and at least the odd-number row of the data block which is a set of data sectors are separated. An outer parity is created for each column and an inner parity is created for each row. Then, the outer parity is scattered with respect to each of the sectors of the data block to be interleaved.

Abstract: A test method for a semiconductor device that is provided with an ECC circuit that uses product code that is composed of a first code and a second code for implementing error correction of a memory, the test method includes steps of: obtaining first pass/fail determination results and second pass/fail determination results that are realized by independent correction operations based on the first code and the second code, respectively; recording the results in a first fail memory and a second fail memory, respectively; executing a prescribed logical operation such as an AND operation relating to the contents of the first fail memory and the contents of the second fail memory; and based on the results of the logical operation, remedying both fail bits and potential fail bits.

Abstract: A method and arrangement for using Synchronous Dynamic Random Access Memory (SDRAM) as storage for correction and track buffering in front end ICs of optical recording or reproduction devices. Data to be stored or read is organized in appropriate bursts for accelerating the SDRAM (SDR) traffic. The SDRAM is built around two banks of memory, and are accessed using a pipelined address logic, thereby accelerating access speeds.

Abstract: A parity assignment technique enables parity declustering in a large, balanced parity (“super-stripe”) array of a storage system. The balanced array may be constructed by combining a plurality of unbalanced parity stripe arrays, each having parity blocks on a set of storage devices, such as disks, that are disjoint from the set of disks storing the data blocks. The technique distributes the assignment of disks to parity groups among the combined super-stripe array such that all disks contain the same amount of data or parity information. Moreover, the technique ensures that all surviving data disks of the array are loaded uniformly during a reconstruction phase after a single or double disk failure.

Abstract: A flexible and relatively hardware efficient LDPC encoder is described. The encoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the encoding process. Each command of a relatively simple microcode used to describe the code structure can be stored and executed multiple times to complete the encoding of a codeword. Different codeword lengths can be supported using the same set of microcode instructions but with the code being implemented a different number of times depending on the lifting factor selected to be used. The LDPC encoder can switch between encoding codewords of different lengths, without the need to change the stored code description information, by simply changing a code lifting factor used to control the encoding processes. When coding codewords shorter than the maximum supported codeword length some block storage locations and/or registers may go unused.

Abstract: A reduced complexity turbo decoding scheme combines elements from two MAP (Maximum a posteriori) algorithms, namely a LogMAP algorithm and a max-LogMAP algorithm. Forward and backward recursive metrics are computed in accordance with the max-LogMAP algorithm, while output extrinsic LLR (Log Likelihood Ratio) values are computed in accordance with the LogMAP algorithm.

Abstract: A system that produces one or more non-repeating randomizer sequences of up to 2m?1 or more m-bit symbols includes a randomizer circuit that is set up in accordance with a polynomial with primitive elements of GF(2m) as coefficients. The system combines the randomizer sequence with all the symbols of ECC code words that are encoded using a BCH code over GF(2m) to produce a randomized code word. The particular primitive elements used and/or an initial state of one or more registers in the system specifies the particular sequence produced by the system. The initial state of each of the one or more registers is a selected one of the 2m?1 elements of GF(2m), and thus, 2m?1 different sequences may be produced by selecting a different initial state for a given one of the registers. If the coefficients are also selected from, for example, a set of “p” possible values, the system produces p*(2m?1) different sequences.

Abstract: A method for adapting the data rate in a communication apparatus as provided, wherein the individual data blocks in a data stream are punctured in accordance with a specific puncturing pattern for adaptation of the data rate, with the puncturing pattern being designed such that it is has a puncturing rate which increase continuously from a central region of the individual data blocks toward at one end of the individual data blocks.

Abstract: An E2PR4 Viterbi detector receives a signal that represents a sequence of values, the sequence having a potential state. The detector includes a recovery circuit that recovers the sequence from the signal by identifying the surviving path to the potential state and simultaneously adding a modified branch metric to the path metric of the surviving path. By simultaneously identifying the surviving path and adding a modified branch metric to its path metric, such an E2PR4 Viterbi detector can operate faster than a conventional add-compare-select E2PR4 Viterbi detector.

Abstract: The present invention provides a relative position and/or posture measuring system for measuring relative positions and relative postures between a magnetic field generator and a magnetic field detector by detecting a change in a magnetic field, in which the magnetic field generator includes a clock generator, a plurality of M-sequential code generators, a plurality of spread code generators, a plurality of integrators, and a voltage to current converter, and transmission coils TX, TY, TZ generate magnetic fields according to driving currents based on spread code obtained by converting code sequences generated by the M-sequential code generators to spread code with the spread code generators. The magnetic field detector reversely spreads received magnetic field detection values to obtain a magnetic field amplitude, and computes relative positions and relative postures of the two from the magnetic field amplitude.

Abstract: A method for displaying metadata placed on a document, includes accepting a command to load a document file that corresponds to the document into a memory of a computing device. The method also includes a computer-aided design application accepting, by way of a command line interface, a command to assign a label to each of a plurality of metadata elements in the document file. The method further includes displaying at least one of the plurality of metadata elements in response to a command to display the label assigned to the at least one of the plurality of metadata elements, thereby allowing a user to verify a value of the at least one of the plurality of metadata elements.

Abstract: A system identifies a document and obtains one or more types of history data associated with the document. The system may generate a score for the document based, at least in part, on the one or more types of history data.

Abstract: An application server, configured for dynamically generating a web page (e.g., HTML) document based on execution of XML documents, dynamically generates an HTML page having selected form elements based on a stored XML document that defines available HTML form elements and respective attributes, and based on user attributes retrieved by the application server from an open network database server (such as LDAP). The application server, in response to a request from a user, accesses an XML document configured for specifying attributes associated with the request; the XML document may specify as form elements menus that are available for generation based on qualified user attributes, or may specify HTML fields that can be generated for display on the HTML page based on the qualified user attributes. The application server also retrieves the user attributes, and dynamically generates the HTML page based on identifying the user attributes matching the qualified user attributes of the accessed XML document.

Abstract: A system enables users at different locations (e.g. different geographic locations) to work collaboratively on a document, and to view each other's annotations to the document. Each user can work with a paper document, and make handwritten annotations to the paper document. The system includes a plurality of workstations communicating with a server. Each workstation comprises a document-imaging device, such as a camera, for generating a digital image of the document. Handwritten annotations are identified by image processing, and new annotations made by each user can be tracked in real time. Image bitmaps of the annotations are distributed by the server to each workstation so that each user can view other user's annotations. In one view, the annotations from different users are superimposed in a combined image.

Abstract: The invention relates to a method and apparatus for regenerating portions of the page that have changed and transmitting only those portions to the client for display. Executing only the necessary parts of the page generation code and transmitting only changes to the client improves the efficiency of using the resources of the network communication channel, the client node and the server node. Performing these operations only when required, when the data has changed, improves the efficiency of use even further. The invention also takes advantage of any portions of the page that are already on the client by reusing them and thus eliminates the need to regenerate or transmit those reusable portions. In one aspect, the invention relates to a method for incorporating a partial page into a transmitted page displayed on a client.

Abstract: Techniques are disclosed for incrementally rendering content in a content framework (such as a portal page provided by a portal system). Upon receiving a request for a portal page, a portal server immediately returns a response including the results from portlets which have acquired their content. If some portlets have not yet finished, subsequent content is delivered at a later time through use of one of several alternative programmatically-generated mechanisms. Capabilities of existing browsers are leveraged for several embodiments, including use of refresh headers, multipart MIME (“Multi-purpose Internet Mail Extensions”) types, and portal pages structured using frames.