Abstract: In a method and arrangement for manipulation of the contents of a data memory with which a processing device can be connected to manipulate (in at least one manipulation step at least one first memory range of the data memory, the processing device monitors a monitoring range of the first memory range, the state progression of which allowing the conclusion of the manipulation of the first memory range to be detected. A processing device with a buffer is used, into which buffer the data are read from the data memory. A sub-range of the data memory is established as a first exclusion range of the data memory. The first exclusion range not being read into the buffer. The first exclusion range is established in an establishing step preceding the manipulation step. The exclusion range includes the monitoring range.

Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for improving the accuracy of information available to a cache coherence controller are provided in order to allow the cache coherence controller to reduce the number of transactions in a multiple cluster system. Non-change probes and augmented non-change probe responses are provided to acquire state information in remote clusters without affecting the state of the probed memory line. Augmented probe responses associated with shared and invalidating probes are provided to update state information in a coherence directory during read and read/write probe requests.

Abstract: A system with multiple processors sharing a single memory module without noticeable performance degradation is described. The memory module is divided into n independently addressable banks, where n is at least 2 and mapped such that sequential addresses are rotated between the banks. A bank may be further divided into a plurality of blocks. A cache is provided to enable a processor to fetch from memory a plurality of data words from different memory banks to reduce memory latency caused by memory contention.

Abstract: A computer system uses transient blocking synchronization for performing operations on shared memory. When performing operations on more than one memory location, the computer system obtains transient exclusive access to a first memory location. The computer system then obtains transient exclusive access to a second memory location, where the transient exclusive access to the second memory location does not expire prior to an expiration of the transient exclusive access to the first memory location or until explicitly unleased.

Abstract: A method, apparatus, and computer program product for storage pools with write atomicity. An abstraction manager enforces write atomicity and disallows options which are inconsistent with write atomicity. The abstraction manager constructs through a physical device interface a logical continuous view of a storage pool in a manner consistent with write atomicity. Applications collect information specific to write atomicity from the abstraction manager through an application interface.

Abstract: The present invention relates to a method for storing register properties of a hardware device having heterogeneous memory in a datastructure. This hardware device is built according to a structure of modules and dependent sub-modules wherein the register properties correspond to register properties of the modules and sub-modules. This method comprises the step of storing the register properties in a data-structure according to the structure of the hardware device and the register properties are arranged in an array for each module or dependent sub-module.

Abstract: A memory interleave system includes M (M=2p, where p is a natural number) memory banks, M memory control units (MCU) corresponding respectively to the M memory banks, N (a natural number) CPUs, and N address generating units (AGU) corresponding respectively to the N CPUs. Each memory bank includes a plurality of memories. The CPUs output memory requests, each containing a first bank address (address of the memory bank) and a first intra-bank address (address of a memory in the memory bank). Each AGU receives a memory request from a corresponding CPU, and generates and outputs a second intra-bank address and a second bank address by using the first intra bank address and the first bank address. Each memory control MCU performs memory bank access control on the basis of the second intra-bank address. An MCU performing access control is selected on the basis of the second bank address.

Abstract: The present invention provides systems and methods for data storage. A hierarchical storage management architecture is presented to facilitate data management. The disclosed system provides methods for evaluating the state of stored data relative to enterprise needs by using weighted parameters that may be user defined. Also disclosed are systems and methods evaluating costing and risk management associated with stored data.

Abstract: In order to output an active command to an SDRAM, at time t0, output of a valid row address starts and a control signal ras# enters the active state. Thereafter, a control signal cs# enters the active state at time t1. At time t3, the signal cs# returns to the negative state. At time t4 when some period of time has passed after time t3, output of the valid row address stops and the signal ras# enters the negative state. Outputs of the address signal adr and the control signals ras#, cas# and we# are controlled in synchronization with a modulated clock S-clk, which is generated at the spread spectrum generator. This reduces the electromagnetic interference that is caused by the address signal adr and the control signals ras#, cas# and we#.

Abstract: A deque of a local process in a memory work-stealing implementation may use one or more data structures to perform work. If the local process attempts to add a new value to its deque's circular array when the data structure is full (i.e., an overflow condition occurs), the contents of the data structure are copied to a larger allocated circular array (e.g., a circular array of greater size than the original circular array). The entries in the original, smaller-sized circular array are copied to positions in the now-active, larger-sized circular array, and the system is configured to work with the newly activated circular array. By this technique, the local process is thus provided with space to add the new value.

Abstract: Control methods are provided for a storage device controller system including first and second storage device controllers. Each of the first and second storage device controllers includes an I/O control module for communicating with a respective storage device storing data in a Fixed Block Architecture recording format, and a respective communications control module for receiving data requests for a respective storage device. The first storage device controller transmits a command to the second storage device controller if a data read request is received for data stored on storage device for the second storage device controller, and subsequently transmits the data that are read out from the storage device by the second storage device controller.

Abstract: An example memory quality assuring system is provided. The system may include a memory mapping logic configured to facilitate accessing memory locations and redirecting memory accessing operations. The system may also include a memory quality assurance logic configured to logically replace a first memory location with a second memory location, to initiate testing logically isolated memory locations, and to selectively logically remove tested memory locations based on the testing. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the application. It is submitted with the understanding that it will not be employed to interpret or limit the scope or meaning of the claims 37 CFR 1.72(b).

Abstract: A system, computer readable medium, and method for multi-tiered data access. The method includes the steps of determining a first search parameter and a second search parameter in response to an operator initiated command, determining a physical location of a data unit corresponding to the first search parameter, identifying a data member corresponding to the second search parameter, and outputting the data member to an operator interface device.

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract: Disclosed herein are exemplary techniques for generating trace information streams to facilitate the reconstruction of the instruction execution history of a processing device for a given time period. The linear instruction pointers or other representations of the instructions executed by a processing device are output as a trace information stream. When one or more translation lookaside buffers (TLBs) used by the processing device are modified by the addition of a new linear-to-physical translation and/or the eviction of an old linear-to-physical translation, a representation of the newly added translation entry, or, alternatively the evicted translation entry, is inserted into the trace information stream. In this manner, the context for the address mapping of the instruction pointers of the trace information stream is provided and, consequently, the execution instruction history of the processing device may be more fully reconstructed.

Abstract: Method and apparatus for a decoder interface for a processor and a coprocessor is described. An input instruction register stores an input instruction from the processor. Configuration instruction registers store instructions. Comparison/pointer logic coupled to the input instruction register and the configuration instruction registers is configured to compare the input instruction from the processor with the instructions stored in the configuration registers to determine if there is a match, and configured to provide a pointer associated with a configuration instruction register of the configuration instruction registers having a instruction of the instructions matching the input instruction, where the pointer has fewer bits than the input instruction.

Abstract: When fetching an instruction from a plurality of memory banks, a first pipeline cycle corresponding to selection of a memory bank and a second pipeline cycle corresponding to instruction readout are generated to carry out a pipeline process. Only the selected memory bank can be precharged to allow reduction of power consumption. Since the first and second pipeline cycles are effected in parallel, the throughput of the instruction memory can be improved.

Abstract: An arithmetic and logic device as an integral part of a processing unit is provided to achieve code size and overhead reduction. The arithmetic and logic device contains several auxiliary computing units, each of which is capable of simple arithmetic and logical operation, under the control of a control unit. By configuring the auxiliary computing units along the data path, additional processing to the operands could be carried out within the same instruction cycle. As such, a processing unit incorporating such an arithmetic and logic device is able to achieve significant performance improvement both in terms of code size and memory access overhead.

Abstract: A method of executing program instructions may include receiving, in a processor, an instruction that causes the processor to read data from or write data to a portion of memory that is shared by one or more processes, at least one process of which manipulates data in a format that is different than a format of data in the shared portion of memory. The method may further include executing alternate instructions in place of the received instruction. The alternate instructions may effect transformation of data associated with the shared portion of memory from a first data format to a second data format.

Abstract: The present invention relates to a design of a computer system that processes instructions with a specific operation code causing the processor to execute a certain operation twice and a method for running such computer system in a time and register space saving manner. A method is provided for executing at least one computer instruction which defines at least a first source operand and an operation to be carried out on the operand, the instruction containing at least one address field of a predetermined bit length and at least one repeated execution bit related to the first operand. The method includes accessing the first source operand; accessing the repeated execution bit and deriving from that repeated execution bit a repeated execution code defining a repeated execution condition; and selectively carrying out the operation defined in the instruction once, twice or more times in dependence of the repeated execution code.

Abstract: A physical-layer unit carries out startup processing in response to a first reset signal delivered from a host, generates and outputs a second reset signal to a data control unit in consideration of time required for the startup processing, reads data for initial setting stored in a storage unit of the data control unit via a serial bus after a waiting time elapses, the waiting time being preset in consideration of the time required for the data control unit to start up in response to the second reset signal, and writes the read data for initial setting into a data register included in the physical layer unit.

Abstract: In one embodiment, a system and a method for facilitating computer system recovery includes identifying a desired delivery mechanism for performing a recovery, adapting a disk image for use with a particular type of recovery medium if a user communicated a desire to use that recovery medium, and writing the disk image to a target destination.

Abstract: A method and system for automatically transitioning configuration settings among computer systems. Multiple configuration settings comprising a computer “personality” are located on a source computing system using multiple transition rules from a personality object. The computer personality includes customization choices, data files, electronic mail, system preferences, application customization choices, the network environment, browser information, etc. The configuration settings are extracted from multiple locations on the source computing system. The multiple extracted configuration settings are stored in a pre-determined transition format. The multiple extracted configuration settings are manipulated. A transition package is created from the multiple manipulated configuration settings. The transition package includes the multiple manipulated configuration settings. The transition package is sent to a target computing system.

Abstract: A method and apparatus for configuring a plurality of computers, each of which requires interaction with at least one resource to advance a configuration state of the computer. A request for access to a resource may be received from at least one of the computers, and a resource needed may be determined. An availability of the resource needed may be determined, and the computer instructed to interact with the resource if the resource is available. If the resource is not available, the computer may be caused to not interact with the resource.

Abstract: Systems and methods for processing textual messages which are integrated with one or more digital attachments is described. These systems and methods are useful in the electronic filing and processing of, for example, image data, and of textual data associated with the image data. One particular application of these systems and methods would be for the electronic filing and processing of dental x-rays with patient claim forms.

Abstract: The present invention allows the user (author or creator) of a document to specify that certain portions of a document be selected for encryption while other portions of the document remain displayed as created. The user could employ a standard word processing editor technique to highlight (or swipe) portions of a document that the user desires to be encrypted. The highlighted portion would then be ‘tagged’ with a surrounding attribute indicating to the word processor that this highlighted portion of the document is to be encrypted. This process is similar to the existing word processor capability to highlight areas on a document and then assign rich text attributes, such as BOLD, ITALICS, etc., to those areas. With proper authorization, any encrypted portion of a document would be displayed as part of the document. Without proper authorization, the display of the document would only contain the unencrypted portions of the document.

Abstract: The invention uses a three phase IKE protocol main mode negotiation to implement a port float algorithm that permits UDP encapsulated ESP traffic to traverse an IPSec-aware NAT. The NAT is connected to a plurality of client computers on a private network and provides an interface between the client computers and a server connected to a public network. In a first phase, a client and the server determine whether both are capable of sending UDP encapsulated ESP packets. In a second phase, the client and server conduct NAT discovery and determine whether the client, server, or both operate behind a NAT. In a third phase, the client and server initiate a port float algorithm, moving a destination UDP port specified in IKE packets from a first port value to a second port value. The server maintains a data structure that allows the server to identify the client sending IKE packets after exiting the second phase and entering the third phase.

Abstract: Systems and methods are provided for managing and distributing keys between routers using protocol exchange messages between routers as key distribution vehicles. According to one embodiment of the invention, a router of an autonomous system uses its private key to send cryptographic information associated with another router to a peer router as part of its protocol exchange messages. The peer router is able to extract the cryptographic information and store it in a look-up table. Such protocol exchange messages may occur as part of an Interior Gateway Protocol or an Exterior Gateway Protocol. According to another embodiment of the invention, a chain authentication system is created as boundary routers of autonomous systems having a trust relationship share cryptographic information for other autonomous systems as part of protocol exchange messages for the exterior gateway protocol.

Abstract: A method wherein an access point authenticates itself with neighboring access points and establishes secure and mutually authenticated communication channels with its neighboring access points. When an access point learns of a neighboring access point, it initiates an authentication with an authentication server through the neighboring access point. Once access points have mutually authenticated each other, whenever a station authenticates itself with a first access point, the first access point communicates the station's authentication context information, for example session key and session identifier, to each neighboring access point. Thus, when the station roams to a neighboring access point, the neighboring access point presents the station with a reauthentication protocol, for example LEAP reauthentication, and if the reauthentication is successful, communication between the station and the neighboring access point takes place immediately and no new EAP authentication needs to occur.

Abstract: A method is disclosed for enabling stateless server-based pre-shared secrets. Based on a local key that is not known to a client, a server encrypts the client's state information. The client's state information may include, for example, the client's authentication credentials, the client's authorization characteristics, and a shared secret key that the client uses to derive session keys. By any of a variety of mechanisms, the encrypted client state information is provided to the client. The server may free memory that stored the client's state information. When the server needs the client's state information, the client sends, to the server, the encrypted state information that the client stored. The server decrypts the client state information using the local key. Because each client stores that client's own state information in encrypted form, the server does not need to store any client's state information permanently.

Abstract: A file that has been encrypted using a symmetric key and that has a corresponding access control entry with the symmetric key encrypted using the public key of a public/private key pair can be accessed. An encrypted key cache is also accessed to determine whether an access control entry to symmetric key mapping exists in the cache for the access control entry corresponding to the file. If such a mapping exists in the cache, then the mapped-to symmetric key is obtained form the cache, otherwise the encrypted symmetric key is decrypted using the private key of the public/private key pair. The encrypted key cache itself can also be encrypted and stored as an encrypted file.

Abstract: A system and method allows a user to authenticate a web site, a web site to authenticate a user, or both. When a user requests a web page from the web site, customization information that is recognizable to the user is provided to allow the user to authenticate the web site. A signed, encrypted cookie stored on the user's system allows the web site to authenticate the user.

Abstract: A method of authenticating a media signal and related software, systems and applications. The method transforms at least a portion of the media signal into a set of frequency coefficients in a frequency domain. For example, it applies a Fast Fourier Transform (FFT) or other frequency transform to blocks of a media signal, such as an image, audio or video signal. It adjusts a relationship between selected frequency coefficients to a reference value. This adjustment is selected so that an alteration to be detected, such as a re-sampling operation or digital to analog—analog to digital conversion, alters the relationship. To detect the alteration, a detector computes the relationship in a potentially corrupted version of the signal. It then compares the result with a threshold value to detect whether the alteration has occurred.

Abstract: An identification information apparatus detects first and second boundary position information representing boundary positions on a high-order bit side and a low-order bit side of codes formed of components, extracts a colluder group matching with a set of the first and second boundary position information among colluder groups including combinations of an arbitrary number of identification information which is not more than a predetermined maximum number, and detects identification information which is common to a plurality of the colluder groups.

Abstract: A method and system for protecting portable computer data from unauthorized transfer or using portable computers to download unauthorized data. The invention is applicable to any computer capable of transferring data, but in one embodiment a portable computer is described. Authorization is enabled by an interface permitting synchronization of the portable computer with a host computer by authentication of the particular portable computer identity. For instance, in one embodiment, when a portable computer is docked with a compatible interface connected to a host desktop computer, it is sensed and identified by the interface. If the particular portable computer identity is authenticated as authorized for that desktop, then synchronization will be enabled by the interface. The computers may then transfer data. However, if the identity is not an authorized one, then authentication will not occur, synchronization is correspondingly disabled, and data transfer is prevented.

Abstract: A method for securing an electronic document (22) comprising attaching a biometric characteristic (20) and the electronic document (22) to form a biometric characteristic-document combination and encrypting the biometric characteristic-document combination to form an encrypted data package (24).

Abstract: An implementation of a technology, described herein, for facilitating the protection computer-executable instructions, such as software. At least one implementation, described herein, may generate integrity signatures of multiple sets of computer-executable instructions based upon the output trace and/or an execution trace of such sets. With at least one implementation, described herein, a determination may be made about whether two or more of such sets are unaltered duplicates by comparing integrity signatures of such sets. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.

Abstract: When a user commands execution of a computer program to commence, a loader program 2 is first started. This loader program 2 reads an encrypted version of the computer program 6 and decrypts it using a public key. This generates an executable version of the computer program 9 which is written directly to the computer memory 8. When the loader program 2 has decrypted the whole of the computer program 9 it starts execution of the computer program 9 it has written into the computer memory 8 and terminates itself or is terminated by the computer program it started. The computer program 9 written into the computer memory 8 will be written into its own memory space and will have its own execution thread. The encryption used may be public key/private key encryption.

Abstract: A method for controlling an external storage device connected to a computer by accepting an operation by a user and issuing an ejection request to the external storage device connected to the computer, including encryption techniques, is provided.

Abstract: The invention describes a method for hardening a security mechanism against physical intrusion and substitution attacks. A user establishes a connection between a network peripheral device and a network via a security mechanism. The security mechanism includes read only memory (ROM) that contains code that initiates operation of the mechanism and performs authentication functions. A persistent memory contains configuration information. A volatile memory stores user and device identification information that remains valid only for a given session and is erased thereafter to prevent a future security breach. A tamper-evident enclosure surrounds the memory elements, which if breached, becomes readily apparent to the user.

Abstract: A separate program power input is provided to a programmable logic array's memory to permit it to be programmed independently of printed circuit board power. Means are provided to isolate the program power input from the array's programmable logic circuit. Means are further provided to isolate the memory from the programmable logic circuit. The program power is not connected directly or indirectly to the programmable logic circuit thereby permitting the use of low-power devices to program the memory without connecting the printed circuit board to a power supply.

Abstract: This invention discloses a local area network including a hub, a plurality of nodes, communication cabling connecting the plurality of nodes to the hub for providing data communication, and a power supply distributor operative to provide at least some operating power to at least some of the plurality of nodes via the communication cabling.

Abstract: A system and method adjusts the polarity of power provided over Ethernet cabling according to configuration information received.

Abstract: A disclosed method involves initializing a performance profiler of a processing system. The performance profiler may include performance profile parameters for a power management policy for the processing system. The method also involves retrieving performance metrics for the processing system from a performance monitoring unit (PMU) of the processing system, in response to a determination that performance details should be collected. A current performance state of the processing system may be determined, based at least in part on the performance profile parameters and the performance metrics from the PMU. The current performance state may then be communicated to a policy manager of the processing system. Other embodiments are disclosed and claimed.

Abstract: Methods and systems for monitoring operating status of a device are provided. Aspects of the method may include receiving within a chip, a signal indicative of a power information of an on-chip device. An output signal indicative of the power information may be generated from within the chip, while the chip is operating. The generated output signal may be communicated outside the chip via a serial bus, a plurality of pin connections on said chip, and/or a general purpose input/output connection. The generated output signal may be multiplexed on at least one pin on the chip and it may comprise a clock signal and/or a data signal. The data signal may comprise sequential power information for a plurality of on-chip devices.

Abstract: A multimedia reproducing apparatus having excellent operability and amenity. In the apparatus, a ROM contains an OS including a system program and a utility program. A control unit controls at suspend function by which data indicating the state of contents of display and contents of execution before interruption of a power supply to a CPU is stored as save data so that the power supply, after interrupted, can be resumed from the state before interruption. A main memory includes a first area for the save data to be written to when suspend is executed, and a second area for data of an external program to be written to when the external program is executed. The system program has the functions of writing the save data to the first area when suspend is executed, and writing the utility program from the ROM to the first area when suspend is not executed and the utility program is called from the external program.

Abstract: A method for remotely power cycling a peripheral data storage system (PDSS) from a host system. The method comprises powering-up the PDSS from the host system based on a host-scheduled backup operation; transmitting pre-selected data to the PDSS from the host system based on the host-scheduled backup operation; and powering-down the PDSS from the host system based on the host-scheduled backup operation. Another method is for operating a PDSS for use with a host system configured to perform scheduled backup operations to the PDSS, the PDSS comprising a peripheral data storage device, a PDSS controller, and a peripheral data storage controller host interface adapted for communication with the host system. The method comprises powering-up the PDSS based on a host-scheduled backup operation; receiving data from the host system for storing in the peripheral data storage device; and powering-down the PDSS based on the host-scheduled backup operation.

Abstract: A clock controller controls a clock generated by a clock generator to determine a clock frequency. A computing device executes software obtained from a storage in accordance with the clock supplied via the clock controller. An exclusive processing section detector detects the start and end of an exclusive processing section which is a section during which an exclusive processing is executed. A clock control judging device commands the clock controller to decrease the clock frequency if the exclusive processing section detector has detected the start of a specific processing section, while commanding the clock controller to decrease the clock frequency if the exclusive processing section detector has detected the end of the specific processing section.

Abstract: A method and system for managing peripheral connection wakeup signaling in a processing system supporting multiple virtual machines provides a mechanism by which ownership of a peripheral having system wakeup capability is transferred between virtual machines. The power management event signal is connected to a service processor input that in turn signals a hypervisor to direct the wakeup activity to a particular logical partition in which the virtual machine was last executing. The hypervisor can then determine whether or not to wake up the entire system, or portions thereof and can direct the power management event to the appropriate virtual machine. In particular the peripheral may be an Ethernet adapter supporting Wake-On-LAN capability. State initialization, which is typically ensured by system power cycling is provided instead by controlling power to the standby power source or in some instances by forcing an indication of a disconnect/reconnect of the wakeup signaling connection.

Abstract: A method for synchronizing frame clocks in a plurality of processors comprises the steps of sending data packets from each of the processors to each of the other processors wherein each of the processors receives the data packets and identifies two of the data packets having the largest phase difference. The largest phase difference is used to determine a target synchronization phase angle, and the period of a frame clock is adjusted so that the frame clock approaches the target synchronization phase angle.