Abstract: An interlayer is disposed on a pattern surface of a substrate. A buried hard mask may be provided on the interlayer. The buried hard mask includes a template opening having a template length along a line axis and a template width perpendicular thereto. The buried hard mask is filled with a fill material. A top mask is provided above the filled buried hard mask. The top mask includes a trim opening crossing the template opening and having a trim width along the line axis that is smaller than the template length. By etching the fill material and the interlayer using the top and buried hard mask a process section of the pattern surface may be exposed such that a target length and width of the process section result from the template and the trim widths. The planar dimensions of the process section may be decoupled from each other.

Abstract: High dielectric constant (high-k) materials are formed directly over oxidation-susceptible conductors such as silicon. A discontinuous layer is formed, with gaps between grains of the high-k material. Exposed conductor underneath the grain boundaries is oxidized or nitridized to form, e.g., silicon dioxide or silicon nitride, when exposed to oxygen or nitrogen source gases at elevated temperatures. This dielectric growth is preferential underneath the grain boundaries such that any oxidation or nitridation at the interface between the high-k material grains and covered conductor is not as extensive. The overall dielectric constant of the composite film is high, while leakage current paths between grains is reduced. Ultrathin high-k materials with low leakage current are thereby enabled.

Abstract: In the case of a chip (1) having an integrated circuit (2), a dielectric mirror coating (3) having at least two dielectric layers (6, 7, . . . H, I, H) is applied as light protection means for the at least one integrated circuit (2) on at least one portion of the surface of the chip (1).

Abstract: An integrated optical I/O and semiconductor chip with a direct liquid jet impingement cooling assembly are disclosed. Contrary to other solutions for packaging an optical I/O with a semiconductor die, this assembly makes use of a metal clad fiber, e.g. copper, which will actually enhance cooling performance rather than create a design restriction that has the potential to limit cooling capability.

Abstract: A semiconductor device and method of fabricating the same reduce the likelihood of the occurrence of electrical defects. The device includes a first interlayer insulating film on a semiconductor substrate; a contact pad spacer on the first interlayer insulating film; and a contact pad in the first interlayer insulating film and the contact pad spacer. The cross-sectional area of an upper portion of the contact pad in the contact pad spacer in a direction horizontal to the substrate is equal to or less than a cross-sectional area of an intermediate portion at an interface between the contact pad spacer and the first interlayer insulating film in a direction horizontal to the substrate.

Abstract: An interference interlock between leadframe features and a mold compound is provided in a packaged semiconductor device by exposing at least one predetermined surface area to an etching process prior to a molding step. This produces an etched recess with a recessed wall delimited by a step wall, generally perpendicular and adjacent to the recessed wall. The step wall is partially undercut by etching. During the molding step, the recessed wall and the step wall are both contacted by and embedded in the molding compound.

Abstract: A semiconductor device of the present invention includes a lead frame having an island portion having a roughened upper surface and side faces, and an unroughened lower surface, and also having a plurality of leads having roughened inner lead portions and unroughened outer lead portions; a semiconductor chip placed on the upper surface of the island portion of the lead frame; a plurality of electrode pads provided on the upper surface of the semiconductor chip; a plurality of wires connecting the plurality of electrode pads and the plurality of leads; and a resin molding the semiconductor chip.

Abstract: A leadframe of a leadless flip-chip package includes a plurality of inner leads, a nonconductive ink layer and a solder mask layer. The inner leads have a plurality of bump-connecting terminals, a plurality of outer terminals and a plurality of redistribution lead portions. A half-etched recession is formed on lower surfaces of the redistribution lead portions, and is filled with the non-conductive ink layer. The non-conductive ink layer fixes the redistribution lead portions onto the bump-connecting terminals. The solder mask layer is easily formed on the non-conductive ink layer and covers the inner leads.

Abstract: A semiconductor component having a semiconductor chip mounted on a packaging substrate and a method for manufacturing the semiconductor component that uses batch processing steps for fabricating the packaging substrate. A heatsink is formed using an injection molding process. The heatsink has a front surface for mating with a semiconductor chip and a leadframe assembly. The heatsink also has a back surface from which a plurality of fins extend. The leadframe assembly includes a leadframe having leadframe leads extending from opposing sides of the leadframe to a central area of the leadframe. A liquid crystal polymer is disposed in a ring-shaped pattern on the leadframe leads. The liquid crystal polymer is partially cured. The leadframe assembly is mounted on the front surface of the heatsink and the liquid crystal polymer is further cured to form a packaging assembly, which is then singulated into packaging substrates.

Abstract: A chip package structure including a chip, a leadframe, multiple bonding wires and an encapsulant is provided. The chip has an active surface and multiple contacts. The contacts are located on one side of the active surface. The chip is fixed under the leadframe. The leadframe has multiple first inner leads located on the active surface, and multiple second leads, wherein one end of each first inner lead and one end of each second inner lead are at near outside of one of the contacts. The bonding wires respectively connect the first inner leads and the second inner leads to the contacts. The encapsulant wraps the chip, the first inner leads, the second inner leads and the bonding wires. Because the contacts are located on one side of the active surface, the possibility of collapse of the bonding wires is reduced.

Abstract: A low-profile Universal-Serial-Bus (USB) assembly includes a modular USB core component that is retractably mounted into an external housing. The modular USB core component includes a PCBA in which all passive components and unpackaged IC chips are attached to a single side of a PCB opposite to the metal contacts. The IC chips (e.g., USB controller, flash memory) are attached to the PCB by wire bonding or other chip-on-board (COB) technique. The passive components are attached by conventional surface mount technology (SMT) techniques. The housing includes a retractable mechanism that facilitates selective exposure of metal contacts, either by sliding a front portion of the modular USB core component into and out of a front opening of the housing, or by providing a cover plate that slidably covers the front portion of the modular USB core component.

Abstract: A chip package for an image sensor includes a first semiconductor chip having a first surface where a photographing device and a first circuit pattern are formed and a second surface that is opposite to the first surface where a second circuit pattern is formed. The first and second circuit patterns are electrically connected. The chip package further includes a second semiconductor chip attached to a second circuit pattern on the second surface of the first semiconductor chip. A printed circuit board faces the second surface of the first semiconductor chip and transfers an electric signal between the first and second semiconductor chips and externally. A housing accommodates the first and second semiconductor chips. The housing allows light to pass through to the photographing device.

Abstract: An encapsulation type semiconductor device and a manufacturing method of the encapsulation type semiconductor device are disclosed. The encapsulation type semiconductor device includes a substrate provided with a concave portion which concaves in a direction from a first principal surface portion to a second principal surface portion. A first semiconductor chip using MEMS is mounted on the concave portion. A first principal surface portion of a second semiconductor chip faces at least the concave portion of the substrate with a space interposed between the first principal surface portion and the concave portion. An outer peripheral side of the concave portion of the first principal surface portion of the substrate is connected with the first principal surface portion of the second semiconductor chip facing the concave portion, by use of a connecting portion.

Abstract: A microelectronic assembly includes a first microelectronic device electrically coupled with a second microelectronic device via wire bond attachment, the first microelectronic device being structurally coupled with the second microelectronic device via a polymer adhesive, and one or more passive(s) coupled with the first microelectronic device wherein at least one or more passive(s) are enclosed in the polymer adhesive between the first and second microelectronic devices.

Abstract: The present invention provides a system and method for devising stackable assemblies that may be then stacked to create a stacked circuit module. One or more integrated circuit (IC) die are disposed on one or more sides of a redistribution substrate that is preferably flexible circuitry. In some preferred embodiments, the die and redistribution substrate are bonded together and wire-bond connected. Two or more stackable assemblies are interconnected through frame members to create low profile high density stacked circuit modules.

Abstract: Provided are a semiconductor package and a method of manufacturing the same. The semiconductor package includes a circuit substrate having a slit inside the circuit substrate, a semiconductor chip formed on an upper surface of the circuit substrate, a wire connecting the semiconductor chip and the circuit substrate through the slit, and a sealant partially covering the wire. According to the semiconductor package, by forming the sealant covering only a part of the wire, wire severing and warping of the semiconductor package can be prevented. In addition, the thickness of a stacked type semiconductor package can be reduced.

Abstract: A mechanism for continuously referencing signals over multiple layers in laminate packages provides a continuous path for signals from one layer to another while using the ideal voltage reference for all areas of the package and still avoiding discontinuities in the voltage reference. A reference plane adjustment engine analyzes a package design and identifies an ideal top plane for all areas of the package, including areas under particular chip die(s) and areas that are not under a chip die. The reference plane adjustment engine then modifies the package design to reposition ground planes, source voltage planes, signal planes, and vias between layers to maintain a continuous voltage reference regardless of the top layer. The reference plane adjustment engine provides the resulting mixed voltage plane package design to a design analysis engine. A package fabrication system fabricates the package.

Abstract: An embodiment of the present invention discloses a method for contacting at least one electrical contact surface on a surface of a substrate and/or at least one component arranged on the substrate, especially a semiconductor chip. The method includes the following steps: at least one insulating film consisting of an electrically insulating plastic material is laminated, under a vacuum, onto the surfaces of the substrate and the component including the contact surface; and the contact surface to be contacted on the surfaces is bared by opening a window in the insulating film. An embodiment of the present invention further comprises sheet contacting the bared contact surface with at least one metallisation on an insulating film.

Abstract: The invention relates to a semiconductor component (1) comprising a semiconductor chip (3) provided with a passivation layer (2), and to methods for producing the same. In this case, the passivation layer (2) covers the topmost interconnect structure (4) of the semiconductor chip (1) whilst leaving contact areas (5) free. The passivation layer (2) is in direct adhesive contact with the plastic housing composition (6) of the semiconductor component (1), wherein the passivation layer (2) comprises a polymer (7) with embedded mineral-ceramic nanoparticles (8).

Abstract: A semiconductor arrangement has a silicon body with a first surface and a second surface and a thick metal layer arranged on at least one surface of the silicon body. The thickness of the thick metal-layer is at least 10 micrometers (?m).

Abstract: Electrode plates (52, 54) acting as a heat sink are arranged to sandwich a power transistor (Q1) and a diode (D1). Electrode plates (52, 54) at their surfaces opposite cooling elements (62, 64) at a portion opposite power transistor (Q1) and diode (D1) are formed to be smaller in thickness at a portion adjacent to power transistor (Q1) and diode (D1) substantially at the center than at a periphery.

Abstract: The invention relates to an integrated circuit (1) having a plurality of substrate layers (2), active and/or passive components (3) embedded in the substrate layers (2), high-frequency lines conducted to the components (3) through the substrate layers (2), and cooling channels (6) for the dissipation of heat. The inventive circuit is characterized in that the cooling channels (6) are configured as high-frequency lines.

Abstract: A package for a semiconductor chip or other heat producing device has a supporting substrate to which the devices mount and electrically connect. An enclosure is formed over the heat producing devices and filled with a supercritical fluid that transports heat from the devices to a heat sink in thermal contact with the enclosure.

Abstract: A chip package including a carrier, at least one chip, a heat spreader, and a thermal interface material (TIM) is provided. The chip is disposed on the carrier and is electrically connected to the carrier. The heat spreader is disposed on the carrier, wherein the heat spreader and the carrier together form a closed space. The chip is located in the closed space. The closed space is filled with the TIM. In addition, a method of manufacturing the chip package is also provided.

Abstract: A system a method for assembling dual-die integrated circuit packages using thermocompression bonding or thermosonic bonding to bond a second die to a substrate opposite a first die bonded to the substrate. The second die is bonded using heat conducted through the first die to the substrate, and optionally through an underfill material. The first and second die are connected such that bumps are connected to common bonding pads on the substrate. Bumps on one of the die extend through openings in the substrate to connect to the common bonding pads. The bonding pads are within the perimeter of the first die.

Abstract: An integrated circuit device includes a die, a lead, and an electrically-conductive structure that is arranged to facilitate electrical communication between the die and the lead. The device also includes a potting material, in which the electrically conductive structure, the die, and at least part of the lead are embedded. An electrically-conductive housing encases the potting material and forms exterior packaging of the device. During manufacturing, the electrically-conductive structure, the die, and at least part of the lead may be arranged within the electrically-conductive housing either before or after the potting material is disposed in the housing. When the integrated circuit device is operating, heat is removable from the die via a thermal conduction path formed by the electrically-conductive structure, the potting material, and the electrically-conductive housing.

Abstract: A semiconductor die has a top surface and a bottom surface. A source contact, a gate contact and a gate finger are formed on the top surface. The source contact has a slit and the gate finger is disposed in the slit of the source contact. A drain contact is formed on the bottom surface. An insulation layer is formed on the top surface to cover the gate finger. A semiconductor device includes the semiconductor die and an electrically conductive sheet attached to the source contact with a conductive paste. The electrically conductive sheet has a concave portion disposed above the gate finger. An air gap is formed between the concave portion and the insulation layer. By including the air gap, the stress that occurs between the electrically conductive sheet and the insulation layer can be reduced, thus an occurrence of a crack in the insulation layer can be prevented.

Abstract: An integrated circuit with a reduced pad bump area and the manufacturing method thereof are disclosed. The integrated circuit includes a semiconductor substrate, an interconnection layer, a passivation layer, and at least a bump. The semiconductor substrate has a semiconductor device thereon. The interconnection layer is disposed on the semiconductor substrate and topped with a top metal layer which at least includes a bonding pad and a conductive line. The passivation layer is disposed on the interconnection layer and has at least an opening to expose the bonding pad. The bump is disposed on the passivation layer to connect the bonding pad through the opening and is extended to a coverage area not directly over the bonding pad.

Abstract: A chip structure including a substrate, at least one pad, at least one protruding pattern, a passivation layer, and at least one bump is provided. The substrate has a circuit unit. The pad and the protruding pattern are disposed on the circuit unit, and the pad is surrounded by the protruding pattern. The circuit unit, the pad, and the protruding pattern are covered by the passivation layer. The passivation layer has at least one opening exposing a part of the pad. The bump is disposed on the passivation layer and electrically connected to the pad. The bump overlaps the protruding pattern and the pad, and the top surface of the bump has a protrusion pattern corresponding to the protruding pattern.

Abstract: A semiconductor mounting substrate according to the present invention comprises: a substrate; a semiconductor device, mounted on this substrate; solder bumps, which connect the semiconductor device and the substrate; a first resin, filled in a space between the semiconductor device and the substrate; and electronic components, mounted on a face side of the semiconductor device where the semiconductor device is mounted, wherein bond strength reinforcing resin section is provided at least between a side face in the vicinity of a corner part of the semiconductor device and a substrate surface of the substrate in a position corresponding to the corner part.

Abstract: A capacitive semiconductor sensor includes a sensor chip, a circuit chip, a plurality of bumps, and a plurality of dummy bumps. The sensor chip includes a dynamic quantity detector, which has a detection axis in one direction. The circuit chip includes a signal processing circuit. The sensor chip and the circuit chip are coupled by flip-chip bonding through the plurality of bumps. Furthermore, the sensor chip and the circuit chip are mechanically coupled through the plurality of dummy bumps.

Abstract: In a semiconductor device and a method of fabricating the same, the semiconductor device includes a contact pad in a first interlayer insulating layer on a semiconductor substrate, a contact hole in a second interlayer insulating layer on the first interlayer insulating layer, selectively exposing the contact pad, a contact spacer on internal walls of the contact hole, a first contact plug connected to the contact pad exposed by the contact hole having the contact spacer on the internal walls thereof, the first contact plug partially filling the contact hole, a metal silicide layer on a surface of the first contact plug, and a second contact plug on the metal silicide layer and partially filling the remaining portion of the contact hole.

Abstract: A method for adding an additional layer to an integrated circuit, the method including providing an integrated circuit having an interconnect layer, depositing, over substantially all of an exposed surface of the integrated circuit, an additional layer of material whose conductivity can be altered, and selectively altering the conductivity of a first portion of the additional layer by selective annealing, to produce a sub-circuit in the additional layer, the sub-circuit being in operative electrical communication with the integrated circuit. Related apparatus and methods are also described.

Abstract: A method to form interconnect structures including nano-scale, e.g., sub-lithographic, lines and vias for future generation of semiconductor technology using self-assembly block copolymers that can be placed at a specific location using a pre-fabricated hard mask pattern is provided. The inventive method provides an interconnect structure in which the line is self-aligned to the via.

Abstract: Embodiments of anodization are disclosed.

Abstract: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.

Abstract: A semiconductor wafer having multi-layer metallization structures that are fabricated to include embedded interconnection structures which serve as low-resistance electroplating current paths to conduct bulk electroplating current fed to portions of a metallic seed layer at peripheral surface regions of the wafer to portions of the metallic seed layer at inner/central surface regions of the semiconductor wafer to achieve uniformity in metal plating in chip regions across the wafer.

Abstract: A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed.

Abstract: A semiconductor package mainly includes a chip, a substrate, an encapsulant, a plurality of external terminals and a stress release layer. The substrate has an upper surface and a lower surface. The chip is disposed on the upper surface of the substrate by a chip-attached layer and electrically connected to the substrate. The encapsulant is formed above the upper surface of the substrate. The external terminals are disposed on the lower surface of the substrate. The stress release layer is formed on the interface of the substrate and the encapsulant such that the external terminals are movable with respect to the encapsulated chip. In addition, a fabrication process of the semiconductor package is also disclosed.

Abstract: A solder ball pad that includes a substrate and a bonding pad attached to the substrate. The bonding pad has a bonding pad surface and a bonding pad edge. The solder ball pad also includes a solder mask attached to the substrate in which the solder mask at least partially surrounds, but does not substantially cover, the bonding pad. The solder ball pad also has an anchor pad coupled to the bonding pad and extending between the substrate and the solder mask.

Abstract: A water tank for a humidifier having a water passage in each of its top end and bottom end. The tank includes an actuator which is operable to open and close both of the passages. Operating the actuator opens the top passage while closing the bottom passage and opens the bottom passage while closing the top passage. Accordingly, the water tank may be filled through the top passage while placed in a humidifier tray.

Abstract: A chemical processing apparatus that utilizes randomly oriented ceramic packing elements having at least three openings therethrough that accommodate feedstock with combustible and/or noncombustible matter that accumulates in the openings is described. The openings occupy at least 10% of the surface area on one side of the packing element.

Abstract: The present invention provides a humidification system for a fuel cell, in which a plurality of membrane humidifiers employing hollow fiber membranes of different kinds having different diameters and pore sizes, or having different numbers of hollow fiber membranes is selectively used according to the amount of current generated from a fuel cell stack or a vehicle output, thus adjusting the humidification amount for dry air to be supplied to a fuel cell stack, and preventing the flooding phenomenon caused at a cathode and the starvation phenomenon in which the air supply is insufficient at the cathode.

Abstract: A low cost process of particular utility in manufacturing optical grade objects such as mirrors from a plastic sheet, comprising the steps of selecting a predefined three dimensional shape to be formed and machining a block of a microporous material, to provide the selected three dimensional shape on one surface thereof. A sheet of plastic is placed over the machined three dimensional shape and distanced therefrom. The sheet of plastic is heated a vacuum is applied through the microporous material to draw the heated plastic sheet to conform to the shape in the block. A surface of the conformed shape plastic is metallized to a form an optical mirror surface.

Abstract: An apparatus and method for fabricating the light guide panel reduces the thickness of the stamper and fixes it firmly in place. The apparatus and method for fabricating the light guide panel according to the present invention has a stamper for forming patterns on the light guide panel and first and second side mold frames which are separable so as to hold the stamper in place during the formation of the light guide and so as to easily eject the finished light guide after it has formed and hardened.

Abstract: This manufacturing device for an optical disc includes: a disc-supporting base on which a disc substrate is mounted; a pin-shaped member arranged at a center of the disc-supporting base, and is movable in the vertical in a center hole of the disc substrate; and a capping member which is slidably placed on a top of the pin-shaped member, and closes the center hole of the disc substrate, wherein when the capping member placed on the top of the pin-shaped member is lowered such that a back face of the capping member contacts an around of the center hole of the disc substrate mounted on the disc-supporting base, the capping member slides on the top of the pin-shaped member.

Abstract: An injection compression molding method of a lens is provided, where a toggle link mechanism (65) is actuated to close a molding die (50) and a movable die plate (64) is moved to a position establishing a cavity thickness of greater than a thickness of an article to be molded while the die is closed. After injecting a molten resin into the cavity, the molten resin is sealed in the cavity and the toggle link mechanism (65) is actuated to advance the movable die plate (64) toward a fixed die plate (61), the relative position of a rear die plate (62) and the movable die plate (64) is made constant at a position where extension of a tie bar (63) becomes a predetermined value, and the molten resin is cooled for a predetermined time after completion of pressurizing the resin.

Abstract: An apparatus is described for micron and submicron particles formation of a substance using the GAS process, comprising a particles formation vessel (22) and means for introducing a solution of the substance and a supercritical fluid into the particles formation vessel (22), wherein said means comprise a nozzle (27) having a central orifice (39) serving to carry a flow of solution, and a plurality of separate outer orifices (41) serving to carry a flow of pure supercritical fluid or a flow of supercritical fluid mixed with a modifier, such that the solvent is extracted from the solution by the supercritical fluid and precipitation of micron and submicron particles occurs. Also a process is described, carried out with such an apparatus.

Abstract: The invention relates to a device for production of dental molded parts from a polymerizable plastic, with a flask (16) and with a heating device (40) for heating the polymerizable plastic in the flask (16). The heating device (40) is movable relative to the flask (16).

Abstract: A molding lens with indentations for measuring eccentricity and a method for measuring eccentricity thereof are disclosed. At least one indentation concentric with an optical surface is respectively disposed on a front plane and a rear plane of the molding lens on area outside the optical surface while the indentation is observed by means of a measuring microscope. Moreover, the eccentricity of the molding lens is detected by eccentricity test function of the measuring microscope and the eccentric direction is defined so as to modify the lens mould and replace conventional eccentricity test that uses a transmission eccentric scale indicator in combination with a jig. Thus the cost of test equipment is reduced, test procedure is simplified and efficiency of mould modification is improved. Therefore, it's more convenient to manage manufacturing of the lens.