Abstract: An apparatus for connecting at least two components contains a lower die and an upper die. The lower die has the components which are to be connected, with the first component supporting the at least second component with an at least partial overlap relative to the first component. The lower die and the upper die can be moved relative to one another. The upper die carries at least two heatable plungers which are connected so as to be able to move relative to one another via a sealed pressure pad. The plungers and the pressure pad have a first flexible layer between them. A second flexible layer is arranged between the upper die and the lower die.

Abstract: Methods and apparatuses for improved thermal, electrical and/or mechanical performance in integrated circuit (IC) packages are described. An IC circuit package comprises a substrate having a central opening. An IC die, resides within the opening in the substrate. Wirebonds couples a plurality of bond pads on a top surface of the IC die to a plurality of bond fingers on a top surface the substrate. An encapsulating material encapsulates at least the IC die and the wirebonds such that at least a bottom surface of the IC die is left exposed. The encapsulating material suspends the die such that at least a portion of the die is held within the opening in the substrate.

Abstract: A projection system, a spatial light modulator, and a method for forming a MEMS device is disclosed. The spatial light modulator can have two substrates bonded together with one of the substrates comprising a micromirror array. The two substrates can be bonded at the wafer level after depositing a getter material and/or solid or liquid lubricant on one or both of the wafers. The wafers can be bonded together hermetically if desired, and the pressure between the two substrates can be below atmosphere.

Abstract: A ball grid array package includes a substrate, a chip, a plurality of pads, a solder mask, a plurality of partitioning walls, and a plurality of solder balls. The substrate has an upper surface and a lower surface opposite to the upper surface. The chip is disposed on the upper surface of the substrate. The pads are disposed on the lower surface of the substrate and electrically connected to the chip. The solder mask is disposed on the lower surface of the substrate. The partitioning walls are disposed on the solder mask and between the adjacent pads. The solder balls are respectively disposed on the pads.

Abstract: Provided is a stacked chip package and a method for forming the same. A spacer is formed on a side of an upper chip. A conductive line is formed on the spacer to electrically connect upper and lower chips. The reliability of the stacked chip package is improved because wire bonding is not used to electrically connect the upper and lower chips. Further, the overall size of the stacked chip package can be reduced as the height of bonding wire loops does not contribute to the overall stacked chip package height.

Abstract: Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.

Abstract: Improved techniques to produce integrated circuit products are disclosed. The improved techniques permit smaller and less costly production of integrated circuit products. One aspect of the invention concerns covering test contacts (e.g., test pins) provided with the integrated circuit products using printed ink. Once covered with the ink, the test contacts are no longer electrically exposed. Hence, the integrated circuit products are not susceptible to accidental access or electrostatic discharge. Moreover, the integrated circuit products can be efficiently produced in a small form factor without any need for additional packaging or labels to electrically isolate the test contacts.

Abstract: A method of connecting carrier tapes in the TCP mounting apparatus is provided, which makes it surer to form an interconnection between the end portion of a current carrier tape and the beginning portion of a new carrier tape, and which is easy to be carried out. The end portion of the current carrier tape is positioned and held by a movable first member and the beginning portion of the new carrier tape is positioned and held by a movable second member. The end portion is sandwiched between the first and second members and then, an unnecessary part of the end portion is cut off using the cutter on the first member. The remaining end portion and the beginning portion are overlapped and thereafter, they are interconnected in the overlapped section, and detached from the first and second members, respectively.

Abstract: In one embodiment of the invention, a lead-frame is designed for use in IC packages such as those conforming to the TO 220 standard or other standards for power packages. The device areas of the lead-frame are arranged in columns, and each column is molded so as to expose a portion of the leads. The device areas can then be singulated by sawing, as in conventional QFN packages. In this manner, packages conforming to power package standards such as the TO 220 standard can be produced much quicker and cheaper than they can in conventional trim and forming methods.

Abstract: Methods and devices for multi-chip stacks are shown. A method is shown that assembles multiple chips into stacks by stacking wafers prior to dicing into individual chips. Methods shown provide removal of defective chips and their replacement during the assembly process to improve manufacturing yield.

Abstract: A semiconductor chip package manufacturing method and a structure thereof are provided. The manufacturing method includes: providing a base having an image sensor chip and an encapsulant, in which the image sensor chip has pads and an active area; placing a transparent insulator on the active area; forming an insulation layer on an upper surface of the base; opening a plurality of openings to expose the pads; forming a plurality of through holes penetrating the insulation layer and the encapsulant outside of the image sensor chips; forming a metal layer on surfaces of the insulation layer, the openings, the pads and the through holes, and on a lower surface of the base, so as to extend the pads to the lower surface of the base; patterning the metal layer to expose a top area of the transparent insulator and remove a partial area of the metal layer on the lower surface of the base to form contacts; and sawing the base to form a package structure containing a single image sensor chip.

Abstract: The present invention provides a method of manufacturing a semiconductor chip formed with an adhesive film at a back surface thereof, comprising the steps of applying a die bond material onto a dummy wafer by a spin coat method to form a coating film, bonding a back surface of a semiconductor wafer onto the coating film of the die bond material formed over the dummy wafer, performing fractionalization for dividing the semiconductor wafer to form pieces, and peeling off the pieces from above the dummy wafer and transferring the coating film of the die bond material to back surfaces of the pieces to form adhesive films.

Abstract: A system may include a plurality of pliant conductive elements, a first end of one of the plurality of pliant conductive elements to be electrically coupled to a first electrical contact of an integrated circuit substrate and a second end of the one of the plurality of pliant conductive elements to be electrically coupled to a second electrical contact of an integrated circuit die.

Abstract: Embodiments relate to electronic assemblies and methods for forming electronic assemblies. One method includes providing a die and a copper heat spreader that are to be coupled to one another through a thermal interface material. A layer of tin is formed on the copper heat spreader. The heat spreader and the die are clamped together with the tin positioned between the heat spreader and the die. The assembly is heated so that the tin melts and forms at least one intermetallic compound with copper from the heat spreader. The heat spreader is then coupled to the die through the intermetallic compound.

Abstract: A chip packaging process is provided. First, a cavity is formed on a heat sink. A first encapsulant is formed on the bottom of the cavity. A circuit substrate is disposed over the heat sink. The circuit substrate has an opening that corresponds in position to the cavity. Thereafter, a chip is disposed on the first encapsulant and the chip is electrically connected to the circuit substrate. Finally, a compound is deposited over the first encapsulant and the chip to form a chip package. The chip package is warp resistant and the chip packaging process increases overall production yield.

Abstract: Advanced Smart Cards and similar form factors (e.g. documents, tags) having high quality external surfaces of Polyvinylchloride (PVC), Polycarbonate (PC), synthetic paper or other suitable material can be made with highly sophisticated electronic components (e.g. Integrated Circuit chips, batteries, microprocessors, Light Emitting Diodes, Liquid Crystal Displays, polymer dome switches, and antennae), integrated in the bottom layer of the card structure, through use of injection molded thermosetting or thermoplastic material that becomes the core layer of said Advanced Smart Cards. A lamination finishing process can provide a high quality lower surface, and the encapsulation of the electronic components in the thermosetting or thermoplastic material provides protection from the lamination heat and pressure.

Abstract: A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.

Abstract: A memory device includes a substrate having a cell region, a low voltage region and a high voltage region. A ground selection transistor, a string selection transistor and a cell transistor are in the cell region, a low voltage transistor is in the low voltage region, and a high voltage transistor is in the high voltage region. A common source contact is on the ground selection transistor and a low voltage contact is on the low voltage transistor. A bit line contact is on the string selection transistor, a high voltage contact is on the high voltage transistor, and a bit line is on the bit line contact. A first insulating layer is on the substrate, and a second insulating layer is on the first insulating layer. The common source contact and the first low voltage contact extend to a height of the first insulating layer, and the bit line contact and the first high voltage contact extend to a height of the second insulating layer.

Abstract: A method of manufacturing a thin film device includes: manufacturing a multi-layered structure in which a transfer layer including a thin film device is transferred to a first surface of the transfer-target substrate; and adhering a second surface of the transfer-target substrate, to which the transfer layer was transferred, to the other substrate provided with a thin film device while the second surface faces the other substrate.

Abstract: An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation. A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected. The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material is regrown on the exposed surface. Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on the regrown material.

Abstract: A method for fabricating strained silicon transistors is disclosed. First, a semiconductor substrate is provided, in which the semiconductor substrate includes a gate, at least a spacer, and a source/drain region formed thereon. Next, a precursor, silane, and ammonia are injected, in which the precursor is reacted with silane and ammonia to form a high compressive stress film on the surface of the gate, the spacer, and the source/drain region. Preferably, the high compressive stress film can be utilized in the fabrication of a poly stressor, a contact etch stop layer, and dual contact etch stop layers.

Abstract: A gate insulating layer, an active layer and a data metal film are sequentially formed on a substrate. A first photoresist pattern having a relatively small thickness in a channel forming area with respect to a thickness of the photoresist pattern not in the channel forming area is formed on the data metal film. The data metal film and the active layer are sequentially etched using the first photoresist pattern. The active layer is etched using the first photoresist pattern. The first photoresist pattern is dry etched using a gas mixture including a sulfur hexafluoride gas and an oxygen gas to form a second photoresist pattern with an opening formed in the channel forming area. The data metal film is then etched using the second photoresist pattern. Dry, wet or acid cleaning procedures used within the manufacturing method reduce formation of stringers in the substrate.

Abstract: A method of manufacturing a thin film transistor substrate includes forming a transistor thin layer pattern, forming a protecting layer, forming a photoresist film, forming a pixel electrode and a conductive layer that are separated from each other, stripping a photoresist pattern to remove the conductive layer using a stripping composition and dissolving the conductive layer. The method of manufacturing a thin film transistor substrate is capable of improving an efficiency of manufacturing process of the thin film transistor substrate. In addition, the stripping composition is recycled.

Abstract: Including a process for forming a fin 12a having a first height and a fin 12b having a second height lower than the first height, a process for forming a silicon oxide film on the upper and side faces of each of the fins 12a and 12b, a process for forming a conductive poly silicon film on the silicon oxide film, a process for forming a gate insulating film 15 and a gate electrode 16 on from the upper face to the side face of each of the fins 12a and 12b by patterning the silicon oxide film and the poly silicon film, and a process for forming a couple of diffusion regions 14 in two regions clipping a region underneath the gate electrode of each of the fins 12a and 12b. According to the present invention, a semiconductor device manufacturing method and a semiconductor device including a fin-type FET having capability of changing the design of the gate width corresponding to an application can be realized.

Abstract: A silicon carbide metal semiconductor field-effect transistor includes a bi-layer silicon carbide buffer for improving electron confinement in the channel region and/or a layer disposed over at least the channel region of the transistor for suppressing surface effects caused by dangling bonds and interface states. Also, a sloped MESA fabrication method which utilizes a dielectric etch mask that protects the MESA top surface during MESA processing and enables formation of sloped MESA sidewalls.

Abstract: An n-FET and a p-FET each have elevated source/drain structures. Optionally, the p-FET elevated-SOURCE/DRAIN structure is epitaxially grown from a p-FET recess formed in the substrate. Optionally, the n-FET elevated-SOURCE/DRAIN structure is epitaxially grown from an n-FET recess formed in the substrate. The n-FET and p-FET elevated-source/drain structures are both silicided, even though the structures may have different materials and/or different structure heights. At least a thermal treatment portion of the source/drain structure siliciding is performed simultaneously for the n-FET and p-FET elevated source/drain structures. Also, the p-FET gate electrode, the n-FET gate electrode, or both, may optionally be silicided simultaneously (same metal and/or same thermal treatment step) with the n-FET and p-FET elevated-source/drain structures, respectively; even though the gate electrodes may have different materials, different silicide metal, and/or different electrode heights.

Abstract: The invention provides, in one aspect, a method of forming a semiconductor device. The method includes forming a gate dielectric layer and a gate electrode layer over a substrate. A portion of the gate dielectric layer and gate electrode layer is etched to form a plurality of gate electrodes. A first dielectric material is formed over the substrate and the gate electrodes. A spacing layer comprising an organic material is deposited over the first dielectric material, and a portion thereof is removed to expose horizontal portions of the first dielectric material and form organic spacers on sidewalls of the gate electrodes. A first dopant is implanted through the first dielectric material into the substrate, after which the organic spacers are removed. An insulating layer is formed over the gate electrodes, and interconnects are fabricated within the insulating layer to connect the gate electrodes.

Abstract: A semiconductor device is fabricated having a metal stress inducing layer that facilitates channel mobility. A gate dielectric layer is formed over a semiconductor substrate. The metal stress inducing layer is formed over the gate dielectric layer. The metal stress inducing layer has a selected conductivity type and is formed and composed to yield a select stress amount and type. A gate layer, such as a polysilicon layer, is formed over the metal stress inducing layer. The gate layer and the metal stress inducing layer are patterned to define gate structures.

Abstract: The present invention relates to a method of fabricating a semiconductor substrate that includes forming at least first and second device regions, wherein the first device region includes a first recess having interior surfaces oriented along a first set of equivalent crystal planes, and wherein the second device region includes a second recess having interior surfaces oriented along a second, different set of equivalent crystal planes. The semiconductor device structure formed using such a semiconductor substrate includes at least one n-channel field effect transistor (n-FET) formed at the first device region having a channel that extends along the interior surfaces of the first recess, and at least one p-channel field effect transistor (p-FET) formed at the second device region having a channel that extends along the interior surfaces of the second recess.

Abstract: A method of fabricating a nonvolatile memory device includes forming a charge tunneling layer on a semiconductor substrate, forming a charge trapping layer on the charge tunneling layer, forming a charge blocking layer on the charge trapping layer by supplying sequentially a metal source gas and an oxidizing gas onto the charge trapping layer, such that a supplying time of the oxidizing gas is form about 0.1 second to about 1.0 second, and forming a gate electrode layer on the charge blocking layer.

Abstract: A method for manufacturing a memory device comprises patterning a dielectric layer and a conductive layer to align near the center of the top surface of a first contact drain plug and near the center of the top surface of a second contact drain plug. A first electrode is formed on the right sidewalls of the patterned dielectric layer and the conductive layer. A sidewall insulating member has a first sidewall surface and a second sidewall surface where the first sidewall surface of the sidewall insulating member is in contact with a sidewall of the first electrode. A second electrode is formed by depositing an electrode layer overlying the top surface of the sidewall insulating member and the second sidewall of the insulating member and isotropically etching the electrode layer to form the second electrode.

Abstract: The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits, as well as methods for forming such CMOS circuits. More specifically, the present invention relates to CMOS circuits that contain passive elements, such as buried resistors, capacitors, diodes, inductors, attenuators, power dividers, and antennas, etc., which are characterized by an end contact resistance of less than 90 ohm-microns. Such a low end resistance can be achieved either by reducing the spacer widths of the passive elements to a range of from about 10 nm to about 30 nm, or by masking the passive elements during a pre-amorphization implantation step, so that the passive elements are essentially free of pre-amorphization implants.

Abstract: A method of forming a metal-oxide-semiconductor (MOS) device is provided. The method includes the following steps. First, a conductive type MOS transistor is formed on a substrate. Then, a first etching stop layer is formed over the substrate to cover conformably the conductive type MOS transistor. Thereafter, a stress layer is formed over the first etching stop layer. Then, a second etching stop layer is formed over the stress layer.

Abstract: A method for manufacturing a resistor random access memory with a self-aligned air gap insulator. A high density plasma deposition on the stack of post-patterned layers produces a hard mask that is substantially near the center and overlying the cap layer of the stack of post-patterned layers. The high density plasma deposition is performed with small critical dimensions so that a small triangle is generated over the cap layer and located near the center of the cap layer. The hard mask serves to prevent the area directly underneath the base of the hard mask from etching, while the hard mask provides a self-aligned technique for etching the left and right sections of the stack of post-patterned layers because the hard mask overlies and positions near the center of the stack of post-patterned layers.

Abstract: A method is provided for forming a NanoElectroChemical (NEC) cell. The method provides a bottom electrode with a top surface. Nanowire shells are formed. Each nanowire shell has a nanowire and a sleeve, with the nanowire connected to the bottom electrode top surface. A top electrode is formed overlying the nanowire shells. A main cavity is formed between the top electrode and bottom electrodes, partially displaced by a first plurality of nanowire shells. Electrolyte cavities are formed between the sleeves and nanowires by etching the first sacrificial layer. In one aspect, electrolyte cavities are formed between the bottom electrode top surface and a shell coating layer joining the sleeve bottom openings. Then, the main and electrolyte cavities are filled with either a liquid or gas phase electrolyte. In a different aspect, the first sacrificial layer is a solid phase electrolyte that is not etched away.

Abstract: A method for preparing a trench capacitor structure first forms at least one trench in a substrate, and forms a capacitor structure in the bottom portion of the trench, wherein the capacitor structure includes a buried bottom electrode positioned on a lower outer surface of the trench, a first dielectric layer covering an inner surface of the bottom electrode and a top electrode positioned on the surface of the dielectric layer. Subsequently, a collar insulation layer is formed on the surface of the first dielectric layer above the top electrode, and a first conductive block is then formed in the collar insulation layer. A second conductive block with dopants is formed on the first conductive block, and a thermal treating process is performed to diffuse the dopants from the second conductive block into an upper portion of the semiconductor substrate to form a buried conductive region.

Abstract: An electronic device may include a substrate, a conductive layer on the substrate, and an insulating spacer. The conductive electrode may have an electrode wall extending away from the substrate. The insulating spacer may be provided on the electrode wall with portions of the electrode wall being free of the insulating spacer between the substrate and the insulating spacer, and portions of the electrode most distant from the substrate may be free of the insulating spacer. Related methods and structures are also discussed.

Abstract: A memory device includes a number of memory cells and a dielectric layer formed over the memory cells. The memory device also includes contacts formed in the dielectric layer and spacers formed adjacent the side surfaces of the contacts. The spacers may inhibit leakage currents from the contacts.

Abstract: A method of fabricating a nonvolatile memory device includes forming a charge tunneling layer on a semiconductor substrate, forming a charge trapping layer on the charge tunneling layer, forming a first charge blocking layer on the charge trapping layer by supplying a metal source gas and a first oxidizing gas onto the charge trapping layer, forming a second charge blocking layer on the first charge blocking layer by supplying a metal source gas and a second oxidizing gas onto the first charge blocking layer, wherein the second oxidizing gas has a higher oxidizing power as compared to the first oxidizing gas, and forming a gate electrode layer on the second charge blocking layer.

Abstract: Provided is a nonvolatile memory device and a fabrication method. The nonvolatile memory device includes an active region defined in a semiconductor substrate, a gate insulating layer formed on the active region and a plurality of gate patterns formed on the gate insulating layer, and crossing over the active region. The gate insulating layer includes a discharge region in a predetermined portion between the gate patterns, the discharge region having a lesser thickness than that of the gate insulating layer under the gate pattern, because a thickness portion of the gate insulating layer is removed to form the discharge region.

Abstract: A example embodiment may provide a memory device that may include an active pattern on a semiconductor substrate, a first charge trapping layer pattern on the active pattern, a first gate electrode on the first charge trapping layer pattern, a second charge trapping layer pattern on a sidewall of the active pattern in a first direction, a second gate electrode on the second charge trapping layer pattern in the first direction, and/or a source/drain region in the active pattern. The memory device may have improved integration by forming a plurality of charge trapping layer patterns on the same active pattern.

Abstract: Gate stacks of an array of memory cells and a plurality of select transistors are formed above a carrier, the gate stacks being separated by spacers. An opening is formed between the spacers in an area that is provided for a source line. A sacrificial layer is applied to fill the opening and is subsequently patterned. Interspaces are filled with a planarizing layer of dielectric material. The residues of the sacrificial layer are removed and an electrically conductive material is applied to form a source line.

Abstract: A semiconductor device, having a recessed gate and asymmetric dopant regions, comprises a semiconductor substrate having a trench with a first sidewall and a second sidewall, the heights of which are different from each other, a gate insulating layer pattern disposed on the semiconductor substrate, a gate stack disposed on the semiconductor such that the gate stack protrudes from the surface of the semiconductor substrate while the gate stack fills the trench, and first and second dopant regions disposed at the upper part of the semiconductor substrate adjacent to the first and second sidewalls of the trench, respectively, such that the first and second dopant regions have different steps.

Abstract: According to the invention, a transistor of vertical MOS type is produced in which an insulating assembly (28) formed above the drain (26) comprises insulating zones (42, 44) either side of the drain; cavities extend under the insulating assembly, either side of the channel (69); the gate (77a, 77b) is formed either side of this insulating assembly; and portions of the gate are located inside the cavities. The invention applies to microelectronics.

Abstract: A memory device includes an active area protruding from a semiconductor substrate. A recess is formed in the active area. A field oxide layer is formed on the semiconductor substrate. A gate electrode extends across the active area while being overlapped with the recess. A gate insulation layer is interposed between the gate electrode and the active area. Source and drain areas are formed in the active area. The transistor structure above defines a recessed transistor structure if it is sectioned along a source-drain line and defines a Fin transistor structure if it is sectioned along a gate line. The transistor structure ensures sufficient data retention time and improves the current drivability while lowering the back bias dependency of a threshold voltage.

Abstract: A method of fabricating a semiconductor device includes providing a region having doped silicon region on a substrate, and forming a silicon germanium material adjacent to the region on the substrate. A stressed silicon nitride layer is formed over at least a portion of the doped silicon region on the substrate. The silicon germanium layer and stressed silicon nitride layer induce a stress in the doped silicon region of the substrate. In one version, the semiconductor device has a transistor with source and drain regions having the silicon germanium material, and the doped silicon region forms a channel that is configured to conduct charge between the source and drain regions. The stressed silicon nitride layer is formed over at least a portion of the channel, and can be a tensile or compressively stressed layer according the desired device characteristics.

Abstract: A method for manufacturing a memory device that includes using a gap-filling material that inhibits charge coupling between memory devices. A semiconductor material is provided that has an active region and an isolation region. A charge trapping structure is formed over the active region and a layer of semiconductor material is formed over the charge trapping structure and the isolation region. A masking structure having sidewalls is formed on the layer of semiconductor material. Spacers are formed adjacent the sidewalls and the layer of semiconductor material is etched to form one or more conductive strips having opposing sides. The one or more conductive strips are formed over the active region. A dielectric material is formed adjacent to the opposing sides of each conductive strip. The dielectric material serves as a gap-filling material. A layer of semiconductor material is formed over the one or more conductive strips.

Abstract: Provided is a method for fabricating a semiconductor device having reduced contact resistance. In the method, gate patterns defining a narrow opening and a wide opening are formed having an upper portion of a predetermined region of a semiconductor substrate. After gate spacers are formed on sidewalls of the gate patterns, an ion implantation process that uses the gate patterns and the gate spacers as an ion mask is performed to form a plug doped region in a portion of the semiconductor substrate that is located below the wide opening. At this point, the gate spacers are formed to expose a portion of a bottom surface of the wide opening and to fill a lower portion of the narrow opening.

Abstract: A method includes directing an ion beam at a plurality of differing incident angles with respect to a target surface of a substrate to implant ions into a plurality of portions of the substrate, wherein each one of the plurality of differing incident angles is associated with a different one of the plurality of portions, measuring angle sensitive data from each of the plurality of portions of the substrate, and determining an angle misalignment between the target surface and the ion beam incident on the target surface from the angle sensitive data. A method of determining a substrate miscut is also provided.

Abstract: A method is provided of making a semiconductor wafer for a semiconductor junction diode device having a target forward voltage drop and a target reverse breakdown voltage. The method begins by doping a semiconductor substrate of a first conductivity type through the back surface with a first dopant of the first conductivity type in an amount sufficient to form a semiconductor junction diode device having a target forward voltage drop. Next, the substrate is doped through the front surface with a second dopant of the first conductivity type in an amount sufficient to form the semiconductor junction diode device such that it has a target reverse breakdown voltage.