Abstract: An integrated circuit structure in which a plurality of Schottky diodes and a capacitor are integrally formed. The integrated circuit structure includes a substrate including an N-type semiconductor doped with N-type impurities and a P-type semiconductor doped with P-type impurities; a first conductive layer laminated on the substrate so that the first conductive layer is electrically connected to the N-type semiconductor and the P-type semiconductor; a dielectric layer laminated on an upper surface of the first conductive layer; and a second conductive layer laminated on an upper surface of the dielectric layer so that the second conductive layer forms a capacitor together with the first conductive layer and the dielectric layer. Accordingly, when the integrated circuit structure is used in a rectification circuit, the size of an entire circuit can be reduced.

Abstract: A plasma display panel includes a sealing member that encloses a gas filled space, a first substrate and a second substrate that sandwich the gas filled space and the sealing member, a first insulator layer that is sandwiched between the first substrate and the sealing member, and a second insulator layer that is sandwiched between the second substrate and the sealing member. Materials and thicknesses of the first insulator layer and the second insulator layer are selected so that etching time of the two insulator layers until etching depth reaches the thicknesses of the insulator layers are the same time period under conditions that one side of each of the insulator layers in the thickness direction is exposed to etchant and that the same etching method is used for the insulator layers.

Abstract: An integrated circuit can be formed with a high-k dielectric layer. A first titanium oxide layer is deposited over a substrate using a first ALD process. A first metal oxide layer is also deposited over the substrate using a second ALD process. A second titanium oxide layer is deposited over the substrate using a third ALD process and a second metal oxide layer is deposited over the substrate using a fourth ALD process. The first and second metal oxides are preferably selected either SrO and/or Al2O3.

Abstract: Gap filling between features which are closely spaced is significantly improved by initially depositing a thin conformal layer followed by depositing a layer of gap filling dielectric material. Embodiments include depositing a thin conformal layer of silicon nitride or silicon oxide, as by atomic layer deposition or pulsed layer deposition, into the gap between adjacent gate electrode structures such that it flows into undercut regions of dielectric spacers on side surfaces of the gate electrode structures, and then depositing a layer of BPSG or P-HDP oxide on the thin conformal layer into the gap. Embodiments further include depositing the layers at a temperature less than 430° C., as by depositing a P-HDP oxide after depositing the conformal liner when the gate electrode structures include a layer of nickel silicide.

Abstract: A method for fabricating semiconductor devices at the wafer level, and devices fabricated using the method, are described. Wafer-level bonding using a relatively thick layer of electrically conducting bond medium was used to achieve void-free permanent wafer level bonding. The bond medium can be introduced to the pre-bonded wafers by deposition or as a preform. The invention provides a low cost, simple and reliable wafer bonding technology which can be used in a variety of device fabrication processes, including flip chip packaging.

Abstract: A separation layer is formed over a substrate having a depressed portion, using a silane coupling agent; a conductive layer and an insulating layer that covers the conductive layer are formed in the depressed portion over the separation layer; and a sticky member is attached to the insulating layer, then the conductive layer and the insulating layer are separated from the substrate. Alternatively, after these steps, a flexible substrate is attached to the conductive layer and the insulating layer.

Abstract: The invention relates to a method for dicing a substrate with a laser apparatus, comprising the steps of delivering a laser beam (15) from said laser apparatus to said substrate to dice said substrate (1) in at least two dies. A first assist gas is supplied at the substrate during a first phase of said dicing method and a second assist gas is supplied at the substrate during a second subsequent phase of said dicing method. The method results in a reduced street-width for dicing of the substrate and consequently costly substrate area is saved. The invention also relates to a laser dicing system, a computer program product for executing the method and a silicon die obtainable by the method.

Abstract: A water processing method for providing a gettering sink effect to a wafer having a plurality of streets which are formed in a lattice pattern on the front surface of a substrate and devices which are formed in a plurality of areas sectioned by the plurality of streets, comprising the steps of removing distortion produced on the rear surface of the substrate of the wafer whose rear surface of the substrate has been ground to a predetermined thickness; forming a gettering sink effect layer by applying a laser beam of a wavelength having permeability for the substrate of the wafer which has undergone the distortion removing step, with its focal point set to the inside of the substrate to form a deteriorated layer in the inside of the substrate; and dividing the wafer which has undergone the gettering sink effect layer forming step, into individual chips along the streets.

Abstract: The invention relates to a device for depositing at least one especially thin layer onto at least one substrate (9). Said device comprises a process chamber (1, 20, 11, 11?, 40, 21), housed in a reactor housing (2) and comprising a movable susceptor (20) which carries the at least one substrate (9). A plurality of gas feed lines (24) run into said process chamber and feed different process gases which comprise coat-forming components. Said process gases can be fed to the process chamber in subsequent process steps, thereby depositing the coat-forming components onto the substrate (9). In order to increase the throughput of said method, the process chamber is provided with a plurality of separate deposition chambers (11, 11?) into which different gas feed lines (24, 24?) run, thereby feeding individual gas compositions. The substrate (9) can be fed to said chambers one after the other by moving the susceptor (20) and depositing different layers or layer components.

Abstract: Disclosed is a method of manufacturing dual orientation wafers. A trench is formed in a multi-layer wafer to a silicon substrate with a first crystalline orientation. The trench is filled with a silicon material (e.g., amorphous silicon or polysilicon trench). Isolation structures are formed to isolate the silicon material in the trench from a semiconductor layer with a second crystalline orientation. Additional isolation structures are formed within the silicon material in the trench and within the semiconductor layer. A patterned amorphization process is performed on the silicon material in the trench and followed by a recrystallization anneal such that the silicon material in the trench recrystallizes with the same crystalline orientation as the silicon substrate. The resulting structure is a semiconductor wafer with isolated semiconductor areas on the same plane having different crystalline orientations as well as isolated sections within each semiconductor area for device formation.

Abstract: The Czochralski method is used for producing p?-doped and epitaxially coated semiconductor wafers from silicon, wherein a silicon single crystal is pulled, and during the pulling is doped with boron, hydrogen and nitrogen, and the single crystal thus obtained is processed to form p?-doped semiconductor wafers which are epitaxially coated.

Abstract: A method is provided for the patterning of a stack comprising elements that do not form volatile compounds during conventional reactive ion etching. More specifically the element(s) are Lanthanide elements such as Ytterbium (Yb) and the patterning preferably relates to the dry etching of silicon and/or germanium comprising structures (e.g. gates) doped with a Lanthanide e.g. Ytterbium (Yb doped gates). In case the silicon and/or germanium comprising structure is a gate electrode the silicon and/or germanium is doped with a Lanthanide (e.g. Yb) for modeling the work function of a gate electrode.

Abstract: A method for fabricating CCD imaging structures having single layer polysilicon gates and employing conventional photolithographic techniques and equipment is disclosed.

Abstract: A method is disclosed for the selective removal of rare earth based high-k materials such as rare earth scandate high-k materials (e.g. DyScO3) over silicon or silicon dioxide. As an example Dy and Sc comprising high-k materials are used as a high-k material in gate stacks of a semiconductor device. The selective removal and etch of this high-k material is very difficult since Dy and Sc (and their oxides) are difficult to etch. The etching could however be easily stopped on them. For patterning of the metal gates comprising TiN and TaN on top of rare earth based high-k layer a chlorine-containing gases (Cl2 and BCl3) can be used since titanium ant tantalum chlorides are volatile and reasonable selectivity to other material present on the wafer (Si, SiO2) can be obtained. The Dy and Sc chlorides are not volatile, but they are water soluble.

Abstract: A memory cell device, including a memory material element switchable between electrical property states by the application of energy, includes depositing an electrical conductor layer, depositing dielectric material layers and etching to create a first electrode and voids. A memory material is applied into a void to create a memory material element in contact with the first electrode. A second electrode is created to contact the memory material element.

Abstract: A method of reactively sputtering from a metallic zinc target a transparent conductive oxide electrode of zinc oxide from a metallic zine in a silicon photo diode device and the resultant product, such as a solar cell. The electrode in deposited on a transparent substrate in at least two steps. The oxygen partial pressure is reduced in the first step to produce an oxygen-deficient ZnO layer, which is highly conductive and has a textured surface, and is increased in the second step to produce a more stoichiometric ZnO, which has a refractive index more closely matched to the overlying silicon device. The second layer is substantially thinner than the first so the surface texture is transferred across it and the overall sheet resistance of the stack structure is reduced.

Abstract: In one embodiment a semiconductor device includes odd contacts and respective odd lines. Spacers are formed on sidewalls of the odd lines and even openings for even lines are formed by performing an etching process. Even contacts are formed in the even openings and then even lines are formed.

Abstract: In a method of forming a contact structure, first and second conductive structures may be formed on a lower structure to be spaced from each other. An insulating layer may be formed on the lower structure to cover the first and second conductive structures. A first hole exposing the first conductive structure may be formed through the insulating layer. A spacer may be formed on a sidewall of the first hole. A first contact electrically coupled to the first conductive structure may be formed in the first hole having the sidewall on which the spacer is formed. A portion of the insulating layer located between the spacers may be removed to form a second hole exposing the second conductive structure. A second contact electrically coupled to the second conductive structure may be formed in the second hole.

Abstract: Interconnect metallization schemes and devices for flip chip bonding are disclosed and described. Metallization schemes include an adhesion layer, a diffusion barrier layer, a wettable layer, and a wetting stop layer. Various thicknesses and materials for use in the different layers are disclosed and are particularly useful for metallization in implantable electronic devices such as neural electrode arrays.

Abstract: A method for forming an integrated circuit includes forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, forming a dielectric barrier layer covering at least sidewalls of the opening, performing a treatment to improve a wetting ability of the dielectric barrier layer, and filling the opening with a conductive material, wherein the conductive material is in contact with the dielectric barrier layer.

Abstract: An iridium barrier and adhesion layer for use with copper interconnects within integrated circuits is formed using an atomic layer deposition (ALD) process. The ALD process uses an organometallic iridium precursor and at least one co-reactant.

Abstract: A method for producing an integrated circuit is disclosed. One embodiment includes application of a barrier layer on the surface of the semiconductor body and in the trench, which barrier layer completely fills the trench and is at least partly deposited by using a CVD method. A metallization layer is produced onto a surface of the barrier layer that arose as a result of the application above the trench and the surface of the semiconductor body.

Abstract: A method of manufacturing a semiconductor device with at least a first dielectric material and a second dielectric material is disclosed. In one aspect, the method comprises providing a first dielectric material on a substrate. The method further comprises providing a patterned sacrificial layer covering the first dielectric material in at least a first region of the substrate. The method further comprises providing a second dielectric material covering the patterned sacrificial layer in the first region and covering the first dielectric material in at least a second region, the second region being different from the first region. The method further comprises patterning the second dielectric material such that the patterned second dielectric material covers the first dielectric material in the second region but not the patterned sacrificial layer in the first region. The method further comprises removing the patterned sacrificial material.

Abstract: A method of forming a semiconductor device. A first dielectric layer is deposited on and in direct mechanical contact with the substrate. A first hard mask is deposited on the first dielectric layer. A first and second trench is formed within the first dielectric layer and the first hard mask. The second trench is wider than the first trench. A first conformal liner is deposited over the first hard mask and within the first and second trenches, a portion of which is removed, leaving a remaining portion of the first conformal liner in direct physical contact with the substrate, the first dielectric layer, and the first hard mask, and not on the first hard mask. Copper is deposited over the first conformal liner to overfill fill the first and second trenches and is planarized to remove an excess thereof to form a planar surface of the copper.

Abstract: A method for manufacturing a semiconductor device with a slurry composition for forming a tungsten pattern. The method comprises: forming a trench in an insulating film formed on a substrate; depositing a tungsten film over the insulating film including the trench; first polishing a tungsten film with a first slurry for polishing metal to expose the insulating film, the polishing selectivity ratio of the first slurry onto tungsten/insulating film being range from 30 to 100; and second polishing the insulating film and the tungsten film with a second slurry, the polishing selectivity ratio of the second slurry onto insulating film/tungsten being range from 3 to 500. The method reduces a thickness difference of tungsten patterns, thereby improving a production yield of semiconductor devices.

Abstract: A phase-changeable layer and a method of forming the same are disclosed. In the method, a first hydrogen gas is introduced into a reaction chamber into which a substrate is loaded at a first flow rate to form first plasma. A primary cyclic CVD process is carried out using precursors in the reaction chamber to form a lower phase-changeable layer having a first grain size on the substrate. A second hydrogen gas is introduced into the reaction chamber at a second flow rate less than the first flow rate to form second plasma. A secondary cyclic CVD process is carried out using the precursors in the reaction chamber to form an upper phase-changeable layer having a second grain size smaller than the first grain size on the substrate, thereby forming a phase-changeable layer. Thus, the phase-changeable layer may have strong adhesion strength with respect to a lower layer and good electrical characteristics.

Abstract: A method for removing a photoresist layer is provided. The method is suitable for a dielectric layer, wherein the dielectric layer has a patterned photoresist layer formed thereon and a metal silicide layer disposed thereunder and there is an etching stop layer disposed between the dielectric layer and the metal silicide layer. The method comprises steps of removing a portion of the dielectric layer by using the patterned photoresist layer as a mask so as to form an opening, wherein the opening exposes a portion of the etching stop layer above the metal silicide layer. the patterned photoresist layer is removed by using an oxygen-free plasma.

Abstract: A method of planarizing a semiconductor device is provided. The semiconductor device includes a substrate, first and second components provided on the surface of the substrate, and a first material provided between and above the first and second components. The first component has a height greater than a height of the second component. The method includes performing a first polishing step on the semiconductor device to remove the first material above a top surface of the first component, to remove the first material above a top surface of the second component, and to level the top surface of the first component. The method also includes performing a second polishing step on the semiconductor device to planarize the top surfaces of the first and second components.

Abstract: In one method and embodiment of the present invention, at least one coil layer is formed in a write head, using a two-slurry step of copper damascene chemical mechanical polishing method with a first slurry step removing the undesirable copper that is on top of the tantalum barrier layer and on top of the trenches and a second slurry step removing the remainder of the undesirable copper, the tantalum barrier layer, the silicon dioxide hard mask layer, the hard baked photoresist layer, the magnetic alloy such as NiFe, CoFe, or CoNiFe, and alumina insulating layer for better thin film magnetic head performances.

Abstract: The inventive chemical-mechanical polishing composition comprises a liquid carrier, hydrogen peroxide, benzotriazole, and a halogen anion. The inventive method comprises chemically-mechanically polishing a substrate with the polishing composition.

Abstract: A method for fabricating a semiconductor device having fine contact holes is exemplary disclosed. The method includes forming an isolation layer defining active regions on a semiconductor substrate. An interlayer dielectric layer is formed on the semiconductor substrate having the isolation layer. First molding patterns are formed on the interlayer dielectric layer. Second molding patterns positioned between the first molding patterns and spaced apart therefrom are also formed. A mask pattern surrounding sidewalls of the first and second molding patterns is formed. Openings are formed by removing the first and second molding patterns. Contact holes are formed by etching the interlayer dielectric layer using the mask pattern as an etching mask.

Abstract: An ashing system capable of restraining etching and damage of an oxide film or a nitride film on a semiconductor substrate and ashing a resist uniformly at a very high rate is to be provided. The ashing system includes a reaction tube, a coil and a high frequency power source for inducing and maintaining a high frequency gas discharge at inside of the reaction tube, and a chamber including a susceptor for holding a semiconductor substrate a and directly connected to the reaction tube, in which only oxygen gas is introduced into the reaction tube while exhausting inside of the reaction tube and inside of the chamber, and a pressure at inside of the reaction tube and inside of the chamber in ashing falls in a range equal to or higher than 250 Pa and equal to or lower than 650 Pa.

Abstract: An apparatus for etching a semiconductor substrate may include a bath, a reaction preventing layer, and a nozzle. The bath may receive a chemical solution. Grooves may be formed at the inner wall of the bath. The reaction preventing layer may be formed on the inner wall and in the grooves of the bath to reduce or prevent a chemical reaction between the chemical solution and the bath. The nozzle may supply the chemical solution to the bath. In a method of etching a semiconductor substrate, the semiconductor substrate having trench structures and an insulation layer pattern may be prepared. The semiconductor substrate may then be dipped into the bath having the reaction preventing layer in which the chemical solution is received. The semiconductor substrate may be reacted with the chemical solution by blocking the chemical reaction between the chemical solution and the bath to etch the insulation layer pattern and the trench structure at a uniform rate.

Abstract: A method of forming a gate dielectric layer includes forming a gate dielectric layer over a substrate. The gate dielectric layer is processed with carbon-containing ions. The gate dielectric layer is thermally processed, thereby providing the gate dielectric layer with a level of carbon between about 1 atomic % and about 20 atomic %.

Abstract: Disclosed is a producing method of a semiconductor device comprising: film thinning a silicon oxide film by heating the silicon oxide film formed after a surface of a silicon substrate is etched by chemical liquid, and one of thermal oxidizing by heating the thinned silicon oxide film to oxidize the silicon oxide film by gas including at least oxygen, and plasma oxidizing the thinned silicon oxide film by plasma discharged gas including at least oxygen.

Abstract: Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom insulating layer, a first charge-trapping layer, and a second charge-trapping layer, wherein an interface between the bottom insulating layer and the substrate has a hydrogen concentration of less than about 3×10/cm?2, and methods for forming such memory cells.

Abstract: A lever connector is provided where fitting of a connector holder is reliably performed by rotation of a lever, so that workability is excellent. In a connector holder 2, a provisionally-retaining claw 17 is provided to be elastically held by a first retaining portion 14 at a predetermined rotating position in order to restrict rotation of the lever 5. In a receptacle connector 3, a pressing projection 23 is provided to move the provisionally-retaining claw 17 to a retracted position where the provisionally-retaining claw 17 is not held by the lever 5 in a state that the connector holder 2 is at a standby position, so that restriction of rotation of the lever 5 is cancelled. On the other hand, an abutting surface of the first retaining position 14 of the lever 5 is of a mountain-like shape including a restricting surface 19 and a guiding surface 20.

Abstract: An electrical plug and receptacle relying on magnetic force to maintain contact are disclosed. The plug and receptacle can be used as part of a power adapter for connecting an electronic device, such as a laptop computer, to a power supply. The plug includes electrical contacts, which are preferably biased toward corresponding contacts on the receptacle. The plug and receptacle each have a magnetic element. The magnetic element on one or both of the plug and receptacle can be a magnet, which is preferably a permanent rare earth magnet although electromagnets may also be used. The magnetic element on the plug or receptacle that does not include a magnet is composed of ferromagnetic material. When the plug and receptacle are brought into proximity, the magnetic attraction between the magnet and its complement, whether another magnet or a ferromagnetic material, maintains the contacts in an electrically conductive relationship.

Abstract: An electrically conductive terminal 2, 3 for a circuit board connector has a heat sink fin 16 which is thermally coupled to two connection portions 12, 14 for dissipation of heat generated in the connection portions. The heat sink fin and one of the connection portions 12 extend from a central body portion 10 in the same direction. The heat sink fin is preferably located outside one of the connection portions 12 to protect the latter from physical damage. A lock portion 18, with a barb 26 for retaining the terminal in the connector housing 1, may extend from the central body portion in a direction opposite to the heat sink fin 16. The terminal 2, 3, and particularly the lock portion 18, can be inserted into a cavity 28 in the connector housing 1 by pushing on the distal end 24 of the heat sink fin. The terminal may be stamped from a sheet metal material. Also claimed is a connector having a row of such terminals mounted with a common alignment and with the heat sink fins located outside the connector housing.

Abstract: A solid floor board assembly with duct raceway is composed of a plurality of base blocks, layer plates, and floor boards. A hollow cavity is formed between the base blocks and the layer plates and is partitioned to accommodate a variety of wire ducts and conduit installations neatly and orderly in desired configuration, and the surface thereof is covered with the floor boards so as to further improve the appearance of the whole structure. The solidarity of structure ensures a high compressive strength, and the number of unit floor board for assembly, the size and the configuration is left to the decision of the building owner. Slip resistant stripes, flower-like striae or a picturesque pattern may be provided on the surface of the floor boards. Duct and conduit exits are provide on the surface of the floor boards for extension of wire ducts and conduit installation.

Abstract: An integrated circuit leadless package system includes forming a lead, attaching an integrated circuit die to the lead, and applying an encapsulant including a thin encapsulant region with a thinner section over the lead than a section over the integrated circuit die.

Abstract: A connector that is capable of reducing defects in display apparatuses is presented. The connector includes a body, a plurality of terminals and a cover. The body has a base and a sidewall. The terminals are disposed on the body and arranged to make an electrical connection with the electrical circuit when the electrical circuit is received by the body. The cover includes a rotation axis, a fixing portion extending from the rotation axis such that the fixing portion is substantially parallel to the base of the body, and a protrusion portion protruding from the rotation axis substantially perpendicularly to the base of the body. The connector prevents electrical discharge from the flexible printed circuit board to the electrical circuit and prevents physical damage to the electrical circuit. Therefore, defect rate decreases and a yield of a display apparatus increases.

Abstract: A cable bonding and grounding clamp that includes: a closed end having a first side and a second side; a pair of side walls each having a first section connected to a second section by an offset section; an open end formed by the second sections; an aperture in at least one of the first sections for viewing a cable positioned between the first sections; and an opening in each of the second sections for receiving a fastening device. Another embodiment is a cable bonding and grounding clamp assembly for a cable having one or more pairs of wires and a grounding shield. The assembly includes an annular member and a clamp. The annular member is installed between the grounding shield and the one or more pairs of wire and the clamp is then installed over the grounding shield and the annular member and tightened with a fastening device.

Abstract: A portable energy device having a housing and an energy storage device is disclosed. The housing includes electrical input terminals and electrical output terminals, the input terminals being configured to receive electrical power from a vehicle having an electrical chassis operating at DC voltage, the output terminals being configured to provide electrical power to an electrical distribution system connected to a utility power grid operating at AC voltage. The energy storage device is in electrical communication with the input and output terminals, and is configured to store electrical power received from the vehicle via the input terminals and to provide the stored electrical power to the electrical distribution system via the output terminals. The housing is so dimensioned as to be insertable through a space defined by a trunk opening of the vehicle with the trunk open, or so dimensioned as to be insertable between a doorframe of the vehicle and a seat of the vehicle.

Abstract: The invention relates to a connector that can be easily mated to a jack connector.

Abstract: A connector includes first and second plug-and-socket connector parts and a connection element. The first connector part has a latch operable to connect the connector parts together. The connection element is connected and is displaceable with respect to the first connector part between first and second positions. The connection element has a pair of locking tabs operable with the latch such that the connection element is fixed in the first position until the latch connects the connector parts together and such that the connection element is movable from the first position to the second position when the latch connects the connector parts together. While in the first position the locking tabs release the latch connection such that the connector parts are separable from one another. While in the second position the locking tabs secure the latch connection such that the connector parts are securable connected to one another.

Abstract: A cable connector for a vehicle door has a first connector including a first contact terminal and a fitting member. The fitting member has at least one cam recess, at least one locking recess, and at least one elastic member. The elastic member has at least one latching recess that engages an edge of a connecter mounting opening of a panel of a vehicle body. The contact terminal and the fitting member have a flange with a waterproof seal provided there between. A second connector is engaged with the fitting member of the first connector. The second connector includes a second contact terminal and a slide lever. The slide lever has at least one guide protrusion and at least one locking protrusion. The slide lever is slideable to move the guide protrusion along the cam recess and lock the locking protrusion in the locking recess.

Abstract: A lever type connector in which a connector holder is reliably fit into a receptacle holder to prevent a half-fitting is provided. In the lever type connector, a restricting groove 19 is provided on the front side of an arm plate 6 of a lever 5, and below a multiple force groove 14. When a connector holder 2 is inserted into the receptacle 3, a rear surface of the restricting groove 19 abuts to a rear surface of a receiving portion 18 to restrict rotation of the lever 5. Then, when the connector holder 2 is pushed down to the standby position where the receiving portion 18 is inserted into the multiple force groove 14, the restricting groove 19 is away from the rear surface of the receiving portion 18, so that restriction of rotation of the lever 5 is cancelled.

Abstract: A sinking electrical card connector includes an insulating housing (10) sinking partially into a hole defined on a printed circuit board (30) (PCB), a number of terminals (20) retained in the insulating housing, a shell (40) mounted on the insulating housing, wherein a pair of holding portions 120 and 120? are formed by the opposite lateral walls of the insulating housing extending outwardly, and each holding portion engages with an edge of the hole of the PCB.

Abstract: An electrical card connector (100) comprises an insulating housing (1) receiving a plurality terminals (2), a shield plate (4) mounted on the insulating housing, and an ejecting mechanism (3) assembled on a lateral side of the shield plate. The ejecting mechanism comprises a pushing pole (30) and a handle (32) assembled on the pushing pole. The handle is capable of separating from the pushing pole.