Abstract: A gate driving circuit has a variable current carrying path that switches a current carrying path among a driving target device, a DC power source and a reactor to operate in plural operation modes including at least a hold mode, a preparation mode, and an execution mode. The variable current carrying path includes a backflow path for causing a reactor current flowing through the reactor to flow back to the DC power source when a gate voltage of the driving target device deviates from a preset allowable voltage range. A drive control part sets the operation mode of the variable current carrying path to the hold mode and holds the ON state or the OFF state of the driving target device, and further switches the operation mode in sequence of the preparation mode and the execution mode, and realizes turn-on or turn-off of the driving target device.

Abstract: A fractional-N frequency synthesizer is described that includes a voltage controlled oscillator (VCO), a programmable integer divider, and a glitch-free phase rotator. The phase select inputs of the phase rotator are controlled by a delta-sigma modulator to provide fine frequency resolution in addition to randomization and noise shaping of fractional quantization noise. The delta-sigma modulator is clocked at rates higher than the synthesizer reference clock resulting in an improvement in clock jitter at the output of the frequency synthesizer. A glitch-free phase multiplexer design is used to implement the phase rotator fractional divider to enables operation at rates higher than the reference clock. The over-sampling ratio of the delta-sigma modulator over the reference clock frequency of the PLL translates directly into an improvement in the quality of the output clock with respect to fractional quantization noise, phase mismatch, and digital noise injection.

Abstract: A PLL/DLL circuit is current self-biased responsive to a current Ild provided from a voltage regulator to a VCO or VCDL. Bias current Ibias, which is proportional to Ild, is provided to components of the PLL/DLL, such as a charge pump or loop resistor, from an interconnect coupled to the voltage regulator. In an embodiment of the present invention, a component of the PLL/DLL includes a bias-generating device, such as a MOSFET p-type transistor having a drain coupled to the interconnect. In an embodiment of the present invention, a voltage regulator includes an AMP having a bias-generating device, such as a p-type transistor, acting as a current source, having a source coupled to Vdd and a drain coupled to the interconnect. The gate of the bias-generating device is coupled to the gate of four other p-type devices. Each of the four p-type devices has a source coupled to Vdd. The drains of the first and second p-type transistors are coupled to an output providing Ild.

Abstract: A charge pump includes first and second pairs of differential transistors. Each transistor includes control, first, and second terminals. First and second charge pump drivers communicate with the control terminal of one of the first pair of differential transistors and one of the second pair of differential transistors, respectively. Third and fourth charge pump drivers communicate with the control terminal of the other of the first pair of differential transistors and the other of the second pair of differential transistors, respectively. The first through fourth charge pump drivers include respective pairs of differential transistors that receive control signals from respective control circuits.

Abstract: A delayed locked loop supports increased operation frequency in a semiconductor memory device. An output driver for use in a delay locked loop includes a first driving block for receiving an output from the delay locked loop to generate a first DLL clock for outputting read data corresponding to a read command, and a second driving block for receiving an output from the delay locked loop to generate a second DLL clock for reducing current consumption during a write operation, wherein the first driving block has larger delay amount than the second driving block.

Abstract: Apparatus and methods that reduce the amount of conducted/radiated emissions from a power switch (200) when a transistor (210) is switched OFF are disclosed. In addition, apparatus and methods that reduce the slew rate in a power switch when the power switch is switched off are disclosed. The apparatus comprises a transistor (210) including an inductive load (230) coupled to the transistor, a plurality of current sources (222, 224) coupled to the gate of the transistor, and a clamp (250) coupled to either the gate and the drain of the transistor, or to the gate and to ground depending on the location of the inductive load, wherein the clamp comprises a resistive element (260) to increase the voltage of the clamp when current flows through the clamp, and wherein the increased voltage causes the apparatus to include a different slew rate.

Abstract: An apparatus and method for improving memory cell reliability is disclosed. The slew rate is reduced in an applied voltage signal used to program a memory cell when Fowler-Nordheim (FN) tunneling injection is detected. The applied programming signal is provided by a charge pump that is preferably a regulated charge pump. The charge pump is selectively controlled by a slew rate control circuit when FN tunneling injection is detected by a voltage level detection circuit at a predetermined threshold voltage level.

Abstract: Hysteresis circuit 10 is composed of three inverters 40, 42, 44. Node NB in hysteresis circuit 10 is connected to the input terminal of transition-detecting part 14 of transmission control part 12. Transition-detecting part 14 detects the timing of the start of the output inversion operation and the timing of the completion of the transition in hysteresis circuit 10 corresponding to potential VB of node NB, and it controls activation/deactivation of inverter 50 on the signal transmission path.

Abstract: A contention-free keeper circuit including a keeper circuit having a first node and a second node, is provided. The contention-free keeper circuit may further include a delay element for providing time delay. The contention-free keeper circuit may further include a high-to-low contention element coupled between the first node and a first supply, and coupled to the delay element output. The contention-free keeper circuit may further include a low-to-high contention elimination element coupled between the first node and a second supply, and coupled to the delay element output, (i) wherein responsive to a low-to-high transition at the first node and the time delay, the low-to-high contention elimination element eliminates a low-to-high contention within the keeper circuit, and (ii) wherein responsive to a high-to-low signal transition at the first node and the time delay, the high-to-low contention elimination element eliminates a high-to-low contention within the keeper circuit.

Abstract: An automatic time constant adjustment circuit has an error detection circuit and a variable time constant circuit. The error detection circuit detects, based on the resistance of an error reference resistor and the capacitance of an error reference capacitor provided therein, a resistance/capacitance error resulting from a variation attributable to an IC process, and then outputs a control signal corresponding to the resistance/capacitance error. The variable time constant circuit includes a resistance portion, a capacitance portion, and a switch portion. The resistance portion is build with one or more resistors. The capacitance portion is build with one or more capacitors. The switch portion sets the time constant of the variable time constant circuit according to the resistance/capacitance error by connecting together one of the resistors of the resistor portion and one of the capacitors of the capacitor portion according to the control signal.

Abstract: A bandgap reference circuit, taking two or more power supplies as the input power supply for outputting a reference voltage, includes a first reference circuit, a second reference circuit, a power selection circuit and a switch circuit. The first and second reference circuits receive two respective power supplies for producing first and second voltages, respectively. As the power selection circuit takes the first power voltage level as the input voltage, the power selection circuit outputs a first control signal; while the power selection circuit takes the second power voltage level as the input voltage, the power selection circuit outputs a second control signal. The switch circuit is coupled to the power selection circuit, the first reference circuit and the second reference circuit. As the switch circuit receives the first control signal, it outputs the first voltage; while the switch circuit receives the second control signal, it outputs the second voltage.

Abstract: A semiconductor integrated circuit apparatus capable of controlling the substrate voltage of a MOSFET so hat the drain current for an arbitrary gate voltage value in a subthreshold region or a saturated region will be free from temperature dependence and process variation dependence, thereby enhancing the stable operation. The semiconductor integrated circuit apparatus includes an integrated circuit main body having a plurality of MOSFETs on a semiconductor substrate; a monitor unit for monitoring at least one of the drain currents of the plurality of MOSFETs; and a substrate voltage regulating unit for controlling the substrate voltage of the semiconductor substrate so as to keep constant the drain current.

Abstract: A first transistor is arranged between a reference voltage node and a first node, and is connected at its gate to a second node. A second transistor is arranged between the second node and the reference voltage node, and is connected at its gate to the first node. Charges are supplied to the first and second nodes via capacitance elements receiving first and second control signals, respectively. Further, a third transistor is arranged between the second node and an output node, and is connected at its gate node to a third control signal ?CT via a third capacitance element. A fourth transistor is connected between the output node and a gate node of the third transistor, and is connected at its gate to the second node. An internal voltage at an intended level can be generated with low power consumption while efficiently using charges without causing an ineffective current flow.

Abstract: A power supply circuit includes at least one capacitor, a plurality of switching members, a power supply which outputs a plurality of voltages and a selecting section for controlling said plurality of switching sections to periodically select one of said plurality of voltages and apply the selected voltage to one terminal and the other terminal of the capacitor. The selecting section includes a member for applying the selected voltage to one terminal and the other terminal of the capacitor across a resistor, during a current limiting period immediately after the application of the selected one of said plurality of voltages to one terminal and another terminal of the capacitor is started.

Abstract: A charge pump circuit has a charge pump section and a replica charge pump section. The replica charge pump section produces a replica voltage at which the UP current will match the DOWN current. A comparator compares the replica voltage to the output voltage, and adjusts the bias to the charge pump section and replica charge pump section so that the voltage level produced by the replica charge pump section matches the output voltage.

Abstract: A current driver includes a gate line having a first and second nodes, K driving transistors, a terminal and a voltage generation section. The terminal receives a first current. The voltage generation section generates a bias voltage according to a current value of the first current. The gate line receives, at one of the first and second nodes, the bias voltage generated by the voltage generation section. Gates of the K transistors are connected between the first and second nodes of the gate line. In the voltage generation section, the relationship between the first current and the bias voltage is adjusted in the first mode, according to a current value of an output current flowing in a first driving transistor of the K driving transistors, and in the second mode, according to a current value of an output current flowing in a second driving transistor of the K driving transistors.

Abstract: An internal voltage generator is highly tolerant of electrical parameter changes of transistors occurring due to process deviation. The generator can produce an internal voltage within a short setup time when there is a significant difference between a voltage level of an internal voltage when power is initially supplied to the internal voltage generator and a voltage level of an internal voltage to be produced. In one embodiment, the internal voltage generator of the present invention includes a comparator block and an output driving block to produce an internal voltage. The internal voltage generator further includes a reference voltage generation block, which generates at least two reference voltages to be supplied to the comparator block, and an offset section control block, which supplies a control signal for optimizing an offset section, that is, a voltage difference between the reference voltages, to the reference voltage generation block.

Abstract: Power consumption may be reduced through the use of power gating in which power is removed from circuit blocks or portions of circuit blocks in order to reduce leakage current. One embodiment uses a modified state retention flip-flop capable of retaining state when power is removed or partially removed from the circuit. Another embodiment uses a modified state retention buffer capable of retaining state when power is removed or partially removed from the circuit. The state retention flip-flop and buffer may be used to allow for state retention while still reducing leakage current. Also disclosed are various methods of reducing power and retaining state using, for example, the state retention flip-flops and buffers. For example, software, hardware, or a combination of software and hardware methods may be used to enter a deep sleep or idle mode while retaining state.

Abstract: A switched capacitor CMOS amplifier uses a first stage non-inverting CMOS amplifier driving a second stage inverting CMOS amplifier. The first stage amplifier is provided with positive feedback to substantially increase the gain of the first stage amplifier. In the described examples, the positive feedback is provided either by connecting a capacitor from the output to the input of the first stage amplifier or by connecting a shunt transistor in parallel with an input transistor and driving the transistor from the output of the first stage amplifier. The substantially increased gain resulting from the positive feedback allows the gain of the switched capacitor amplifier to be set by the ratio of the capacitance of an input capacitor to the capacitance of a feedback capacitor. The amplifier also includes switching transistors for periodically discharging the input capacitor and the feedback capacitor.

Abstract: A switch-mode modulator operating at a two-level voltage and including an alternating output stage (3), an optional output filter (5) and a feedback including a function block (14) with a transfer function (MFB). The modulator furthermore includes a forward block (12) provided with means for calculating the difference between the signal (14a) originating from the function block (14) and a reference signal (REF) as well as with a transfer function (MFW). The output (13) of the forward block (12) is the input of a Schmitt-trigger (9), which generates switch on signals (2) for changing the output stage. The output voltage (VOUT) of the modulator applying either after the optional output filter (5) or the output stage (3) is fed back through the function block (14) so as to generate the signal (14a) fed back.

Abstract: A power amplifier circuit for amplifying an input RF signal with respect to a specified RF output power includes an input terminal for supplying the input RF signal to be amplified, an output terminal for the RF signal with the output power specified, an amplification path formed between the input terminal and the output terminal having a power amplification circuit for amplifying the RF signal, a bypass formed between the input terminal and the output terminal for the RF signal to bypass the amplification path, a control terminal for controlling the operation of the amplification path and the bypass, such that an RF signal is either passed through the amplification path or the bypass.

Abstract: A differential amplification circuit includes a differential amplifier and common mode control circuitry configured to control output common mode of the differential amplifier. However, this control circuitry does not use feedback. The circuitry controls the output common mode in either, or in a combination of two ways, neither of which employs feedback from the output common mode. One control technique uses a dummy circuit and comparator to cancel out the effect of variations in process, temperature and supply voltage on output common mode. Another control technique measures input common mode voltage, compares the measured common mode to a reference, and based on the difference, applies a current to the output that compensates for the variation in output common mode that a given input common mode would otherwise cause.

Abstract: An amplifier for amplifying a signal which is applied to a signal input having a first pair of transistors (10), which is connected to the signal input and which contains two transistors (10-1, 10-2), currents flowing through the two transistors (10-1, 10-2) which have a specific operating current ratio (m) in relation to one another, a second pair of transistors (4), which is connected to the first pair of transistors (10) and which contains two transistors (4-1, 4-2), currents flowing through the two transistors (4-1, 4-2) which have the same operating current ratio (m) in relation to one another, and a signal output (3) of the amplifier (1) being provided between the first pair of transistors (10) and the second pair of transistors (4).

Abstract: A multi-level power amplifier architecture using a multi-tap transformer implemented on a single CMOS integrated circuit wireless communications device is described. By providing a multi-tap transformer for coupling a plurality of power amplifiers to a shared output impedance, such as an antenna, power transmission may be made at different levels while maintaining efficiency. With a multi-tap transformer having “N” taps featuring “N” different impedance levels, each tap may be connected to an amplifier cell which delivers power into the transformer at the tap for coupling to the output load. Any one of the “N” amplifier cells can be turned on at once along with any combination of the “N” amplifier cells.

Abstract: An FET amplifier includes an FET for amplifying a high-frequency signal to be input to the gate on the basis of a gate bias voltage from a gate bias control circuit. In the FET amplifier, a high-frequency signal input circuit and the output portion of an inverting amplifier are made conductive to the gate of the FET. A voltage stabilizing circuit generating a positive DC constant-voltage signal is made conductive to the non-inverting input portion of the inverting amplifier, and a gate bias control signal input circuit is made conductive to the inverting input portion through an inverter circuit. When the output voltage from the inverter circuit is 0 V, the inverting amplifier outputs a positive gate bias voltage (in the High state) and, when the output voltage from the inverter circuit is a fixed positive voltage, the inverting amplifier outputs a negative gate bias voltage (in the Low state) lower than the pinch-off voltage of the FET.

Abstract: The present invention provides methods and apparatuses for an amplifier circuit for amplifying an input signal. An amplifier circuit for amplifying an input signal comprises an amplifying transistor circuit having a power transistor and a dc bias circuit having a plurality of current mirror circuits and a discharge transistor wherein the discharge transistor and the power transistor form a combined current mirror circuit to control quiescent current in the power transistor.

Abstract: A method and system to use voltage isolated and floating differential output amplifiers wired in series and parallel to achieve arbitrary output drive voltage and current for the applications load. A second embodiment uses multiple matched voltage-isolated and floating differential output amplifiers in a single chassis to enable selection between a multi-channel amplifier and a high current and/or high voltage mono amplifier. A third embodiment uses a step-up transformer and paralleled unity-gain buffer amplifiers, on input and/or output stages, to produce a zero feedback, high performance, high drive amplifier. A fourth embodiment uses a high voltage unity-gain driver amplifier to bias a unity-gain buffer amplifier and its power supply to achieve an ultra low distortion high voltage buffer amplifier. A fifth embodiment uses multiple voltage-isolated and linearized devices to enable dynamically modifiable, Class A, Class B, and Class AB topologies of predetermined voltage and current performance.

Abstract: A receiving amplifier includes a semiconductor body with a first node, a second node and an amplifier circuit. The amplifier includes at least one field-effect transistor, a first input, and a second input. A capacitive element is arranged between the inputs of the amplifier circuit, and a tuned circuit whose resonant frequency can be tuned is connected upstream of the amplifier circuit and contains a variable-capacitance element that is connected in parallel with the element in the amplifier circuit. Two inductive elements are also provided, wherein the first inductive element is connected to the first node and the second inductive element is connected to the second node. This results in a series tuned circuit, which leads to a voltage increase at the resonant frequency, and results in an improved signal-to-noise ratio for a signal which is supplied to the receiving amplifier.

Abstract: A method for synthesizing frequencies with a low-jitter an all-digital fractional-N phase-locked loop (PLL) electronic circuit adapted to synthesize frequencies with low-jitter, wherein the electronic circuit comprises a digital phase-frequency detector (DPFD) operatively connected to a digital loop filter (DLF), wherein the DPFD adapted to receive a reference signal and a feedback signal; compare a phase and frequency of the reference and feedback signals to determine a phase and frequency error between the reference and feedback signals; and provide a DPFD output comprising a multi-bit output; wherein the DLF is adapted to receive and filter the DPFD output and provide a DLF output, and wherein the DLF output is updated at each reference period.

Abstract: A single chip digital frequency synthesiser (1) for synthesising a frequency swept synthesised output signal of a selectable frequency sweep comprises a direct digital synthesiser (5) which produces the frequency swept synthesised output signal on an output terminal (7) in response to values of a frequency control digital word applied to a frequency control input (8) thereof by an on-chip data processing circuit (25). An on-chip programmable data storing circuit (12) is programmable to store data indicative of a selected mode in which the digital frequency synthesiser (1) is to operate, and to store data indicative of selectable frequency and the time domains of the frequency swept synthesised output signal to be produced.

Abstract: A novel hybrid stochastic gradient adaptation apparatus and method for calibrating the gain of an RF or non-RF digitally controlled oscillator (DCO). The adaptation algorithm determines a true stochastic gradient between a forcing function and its corresponding system measure to estimate the system parameters being adapted. A momentum term is generated and injected into the adaptation algorithm in order to stabilize the algorithm by adding inertia against any large transient variations in the input data. In the case of adaptation of DCO gain KDCO, the algorithm determines the stochastic gradient between time varying calibration or actual modulation data and the raw phase error accumulated in an all digital phase locked loop (ADPLL). Two filters preprocess the observable data to limit the bandwidth of the computed stochastic gradient providing a trade-off between sensitivity and settling time.

Abstract: The effect of supply voltage variations on an oscillator circuit output are compensated for to reduce supply pushing. The change in a value of a first capacitance in a first direction in response to the variation in the supply voltage is canceled using one or more diodes having a capacitance that changes in a second direction, opposite the first direction, in response to the variation in the supply voltage.

Abstract: A test circuit and a test method using a plurality of oscillation circuits for evaluation are provided in order to reduce the measuring time and simplify the test. One measuring terminal is shared by a plurality of oscillation circuits for evaluation that are formed over the same substrate as a semiconductor device such as a display device, and the plurality of oscillation circuits for evaluation can be tested by the measuring output terminal. Then, the measurement results are Fourier transformed to obtain the oscillation frequency of the plurality of oscillation circuits for evaluation at the same time. Thus, variations in semiconductor elements can be evaluated.

Abstract: An oscillator comprising an active device having first, second and third terminals, a plurality of micro-stripline resonators coupled together to form a coupled-resonator network, the coupled-resonator network being coupled to the second terminal of the active device and a tuning network coupled to the coupled-resonator network, the tuning network being operable to adjust the coupling between at least two of the resonators that form the coupled resonator network.

Abstract: A method for operating a torsion oscillator at its resonant frequency. The method performs an open-loop frequency sweep starting with nominal operation parameters saved from the factory or from a previous operation of the torsion oscillator. The sweep determines an open-loop resonant frequency and an open-loop drive level. A closed-loop resonant frequency sweep is performed and a closed-loop steady-state resonant frequency is determined. This frequency is used to calculate a closed-loop overshoot and a closed-loop steady-state drive level. The torsion oscillator is then operated in a closed-loop mode at the closed-loop steady-state resonant frequency and starting at the closed-loop steady-state drive level. Finally, the nominal operation parameters are updated and stored in non-volatile memory. The method minimizes the effects of ambient environmental conditions including air density on the steady-state operation of the torsion oscillator.

Abstract: In various embodiments, the invention provides a clock generator and/or a timing and frequency reference using an LC-oscillator topology, having a frequency controller to control and provide a stable resonant frequency, which is integrated with other, second circuitry such as a processor or controller. Frequency stability is provided over variations in a selected parameter such as temperature and fabrication process variations. The various apparatus embodiments include a sensor adapted to provide a signal in response to at least one parameter of a plurality of parameters; and a frequency controller adapted to modify the resonant frequency in response to the second signal. In exemplary embodiments, the sensor is implemented as a current source responsive to temperature fluctuations, and the frequency controller is implemented as a plurality of controlled reactance modules which are selectively couplable to the resonator or to one or more control voltages.

Abstract: Conductor segments are positioned within a two conductor transmission line in order to generate microwave pulses. The conductor segments are switchably coupled to one or the other of the transmission lines in parallel. Microwave pulses may be induced in the transmission line by closing the switches in a controlled manner to discharge successive segments into the transmission lines. The induced waves travel uninterrupted along the transmission lines in a desired direction.

Abstract: A non-reciprocal element with three central conductors and a communication apparatus are disclosed, in which the insertion loss is small and the bandwidth is wide. Three central conductors are arranged in proximity to a ferrite thin plate in such a manner as to cross each other in a mutually electrically insulated state. A static magnetic field is applied to the ferrite thin plate by a permanent magnet. An end each of the three central conductors makes up three input/output terminals, respectively, and the other end thereof is connected to a common portion. Three matching capacitors are connected between an end each of the three input/output terminals, respectively, and the common portion. At least one of the angle between the first and second central conductors and the angle between the second and third central conductors is not more than 90 degrees.

Abstract: Embodiments of the present invention include wideband attenuator circuits and methods. In one embodiment the present invention includes a first divider circuit coupled in series with two or more second divider circuits. The divider circuits include resistance and capacitance values that may be set according to particular relationships. In one embodiment, a wideband attenuator may include capacitors that are selectively coupled to each output node.

Abstract: A high-frequency circuit device, a high-frequency module, and a communication apparatus, which prevent generation of an undesired wave to prevent electrical power loss and undesired coupling, are provided. The high-frequency circuit device includes a first slot line and a second slot line, which are provided at respective surfaces of a dielectric substrate, are formed with the same shape. An FET is provided on the first slot line. For preventing the mounting of the FET from causing a phase difference to occur between a high-frequency signal, which propagates along the first slot line, and a high-frequency signal, which propagates along the second slot line, a phase-adjusting stub is formed at a position of a stub at the second slot line. The phase is adjusted by changing the length of the stub.

Abstract: A description is given of a BAW apparatus having a first BAW resonator and a second BAW resonator which are connected antiparallel to one another so as to reduce non-linear effects, in particular harmonics.

Abstract: An RF feed-through connector has a single pin or multi-pins supported and hermetically sealed between a first portion of the connector facing the hermetically sealed interior portion of an electronics-containing housing and a second portion of the connector exposed to ambient conditions in which the electronics-containing housing is placed. The invention is particularly directed to a new hermetically sealed RF feed-through connector architecture in which the connector's outer shell contains a relatively low coefficient of thermal expansion (CTE) portion that enables it to be soldered to a low CTE insert that supports one or more hermetically sealed longitudinal signal pins. The connector's outer shell also includes a relatively high CTE portion that allows the shell to be readily joined as by welding to an adjacent support structure, such as a relatively high CTE aluminum housing and the like.

Abstract: Resettable circuit interrupting devices, such as GFCI devices that include a reset lockout mechanism are provided. The GFCI comprises a reset button which is selectively blocked from resetting the GFCI.

Abstract: This publication discloses a switching device combination for capacitive loads (3) connected to a direct voltage. The switching device combination includes an actual switch component (1) for connecting voltage to the capacitive load (3), a charging switch component (2) for connecting charging voltage to the capacitive load in the initial stage, which charging switch component is dimensioned for a lower current than the actual switch component (1), a controller component (4), by means of which the actual switch component (1) is controlled from an open state to a closed state and vice versa, with the aid of a mechanical lever (5), which is connected to a first shaft (6), and delay elements (11) for delaying the connection of the actual switch component (1), so that the closed charging switch component (2) will have time to charge the capacitive load (3) before the connection of the actual switch component (1).

Abstract: The present invention provides a permanent magnet, comprising a cylinder formed with a permanent magnetic material. The cylinder comprises along a radial direction, a magnetic core and a magnetic sheath that are coaxial. The magnetic core is assembled in the magnetic sheath. The magnetization direction of the magnetic core is axial direction, and the magnetization direction of the magnetic sheath changes step by step from a direction which is parallel to the magnetization direction of the magnetic core in one end to a direction which is orthogonal to the magnetization direction of the magnetic core in the other end, along the axial direction of the cylinder. Moreover, a magnetic device for use in MRI using the magnet and manufacturing methods for the permanent magnet and the magnetic device are also provided in the present invention. With the permanent magnet, magnetization strength in the working area generated by the magnetic device for use in MRI can amount to more than 0.5-0.6 T.

Abstract: There is illustrated the assembly of a dual inductor (1) on to a printed circuit board (2). A printed circuit board (2) has a through hole (3). Then the first winding (5), formed from a stamping, is mounted across the hole (3). Then, the first winding (5) is connected to the first face (7) of the PCB (2). Then, a core assembly (10) is inserted into the hole (3) from the direction of a second face (8) of the PCB (2). Then, at some stage, for example as shown, the second winding (6) is inserted into the core assembly (10) and affixed to the bottom face (8) of the PCB (2).

Abstract: A tank for an electrical apparatus immersed in fluid is formed by a couple of long opposite of opposing walls where any of them have one or more supporting folds; and a couple of short opposite or alternate opposing walls joined to the long walls on their lateral ends, which defines a structure generally parallelepiped-shaped and such lateral ends join defines a supporting curvature. There is a base joined to the lower ends of the parallelepiped; and a cover joined to the upper ends of the parallelepiped covering an internal volume that accommodate at least one core, one or more windings, and the electrical apparatus fluid. Supporting folds define channels that allow them to accommodate inside them the lateral legs and the lower yoke of the core. The tank can be applied to electrical apparatus like transformers, autotransformers, and reactors and the like.

Abstract: A magnetic device of smaller size and lower profile comprising a coil conductor of high inductance and low resistance is provided. The magnetic device comprises a coil conductor and a multilayer magnetic layer formed so as to cover the periphery of the coil conductor. Further, a magnetic device having higher inductance value and lower conductor resistance value (AC resistance) by selecting a magnetic layer capable of suppressing the eddy current and having excellent magnetic characteristics even designed with smaller size and lower profile.

Abstract: The invention is directed to a method for manufacturing a metal-insulator-metal transformer together with a capacitor. The method comprises steps of providing a substrate having at least a dielectric layer formed thereon and then forming a first metal layer of the metal-insulator-metal capacitor together with a first metal coil of the transformer over the substrate. An insulating layer is formed to cover the substrate, the first metal layer and the first metal coil. A second metal layer of the metal-insulator-metal capacitor is formed together with a second metal coil of the transformer on the insulating layer.

Abstract: A semiconductor apparatus having a semiconductor chip, a first coil electrically connected to the semiconductor chip and a first electrode electrically connected to the first coil is comprised of a second electrode which can be electrically connected to the first electrode as well as which can be electrically connected to a second coil on the outside of the semiconductor apparatus, and is characterized by that inductance composed of the first coil and the second coil is obtained by electrically connecting the second electrode to the first electrode and the second coil.