Abstract: A flexible semiconductor test structure that may be incorporated into a semiconductor device is provided. The test structure may include a plurality of test pads designed to physically stress conductive lines to which they are attached during thermal cycling. By utilizing test pads with different dimensions (lengths and/or widths), the effects of thermal stress generated by a plurality of conductive lines having corresponding different dimensions may be simulated.

Abstract: Apparatus for detecting vibration of an object adapted to rotate includes one or more vibration processors selected from: a direction-change processor adapted to detect changes in a direction of rotation of the object, a direction-agreement processor adapted to identify a direction of rotation of the object in at least two channels and identify an agreement or disagreement in direction of rotation identified by the at least two channels, a phase-overlap processor adapted to identify overlapping signal regions in signals associated with the rotation of the object, and a running mode processor adapted to identify an unresponsive output signal from at least one of the at least two channels.

Abstract: An apparatus for reader characterization is described. The apparatus includes a rotator for rotating a media. The media can contain a signal having a value for a function of a read/write head being assessed. The rotator is operable in conjunction with said apparatus. The apparatus also includes a proximator for proximalizing the media to the read/write head. The proximator is operable in conjunction with said apparatus. The apparatus further includes a writer operable in conjunction with said assembly. The writer writes the signal upon the media. The signal emits the value of the function. The signal is detectable by a reader of the read/write head. The apparatus additionally includes an interface operable in the apparatus for providing removable orientation of the read/write head in an assessing position. The assessing position enables a reader of the read/write head to detect the signal upon rotation of the signal through the assessing position.

Abstract: In at least one embodiment an apparatus is provided that includes an electromagnetic coupler probe to provide sampled electromagnetic signals and an electronics component to receive the sampled electromagnetic signals from the electromagnetic coupler probe and to provide recovered sampled electromagnetic signals. Other embodiments may be described and claimed.

Abstract: A system and method to detect angular rotation, linear displacement and/or surface deformations is presented. The method is based on the ability of a linear polarized light to interact with magnetic materials and to change its polarization angle due to Faraday effect. A basic structure of the system consists of a magneto-optic (MO) film with a two-domain structure and a single domain wall which are generated by gradient magnetic field produced by opposite polarity permanent magnets placed near the film. An AC magnetic field applied perpendicular to the MO film surface causes the magnetic domain wall in the MO film to oscillate at the same frequency. This leads to a detected output AC modulated signal. By measuring the temporal changes in this signal, information on angular rotation, linear displacement and/or surface deformation can be obtained.

Abstract: An instrument for measuring sub-pico Tesla magnetic fields using a superconducting quantum interference device (SQUID) inductively coupled to an unshielded gradiometer includes a filter for filtering magnetically-and electrically coupled radio frequency interference (RFI) away from the SQUID. This RFI is principally coupled to the SQUID via the unshielded gradiometer. The filter circuit includes a resistor-capacitor (RC) combination interconnected to first and second terminals so that it is parallel to both an input coil of the SQUID and the gradiometer. In addition, a shielding enclosure is used to electromagnetically shield the filter circuit from the SQUID, and a method is employed to increase the impedance between the input coil and the SQUID without diminishing the overall sensitivity of the instrument.

Abstract: A closed loop magnetic sensor system for measuring an input magnetic field from a magnetic field source has a compensation circuit, which can be for example a printed wire board, and a magnetic sensor, such as a Magnetoresistive (MR) sensor, for measuring an input magnetic field. Preferably, the magnetic sensor is magnetically coupled to the compensation circuit by arranging the magnetic sensor in an air gap provided in the compensation circuit. The compensation circuit has a compensating conductor, arranged on or in a dielectric medium, which can be configured as a plurality of nested coils. Electrical control circuitry, electrically, coupled to the magnetic sensor and compensating conductor, is adapted and arranged to drive a feedback current through the compensating conductor according to the output of the magnetic sensor such that the input magnetic field is substantially compensated at the magnetic sensor. The magnetic system can serve as current sensor for sensing current through a primary conductor.

Abstract: An inspection system includes an electromagnetic shield having electrically conductive sidewalls spaced from one another. The shield also includes a conductive third wall which spans the distance between the sidewalls, and is electrically coupled to the sidewalls. The inspection system also has an inductive sensor positioned within the electromagnetic shield. The inductive sensor has two current branches, which exhibit anti-symmetric current flow. Typically, the two current branches are positioned on opposing sides of the medial plane of the electromagnetic shield.

Abstract: An object of the present invention is to acquire data, which is used to construct a water component-enhanced/fat component-suppressed image, with a repetition time TR set to a desired value. Included are a data acquisition unit and an image construction unit. The data acquisition unit acquires data D_?fat according to a steady-state pulse sequence specifying that the phase of an RF pulse is varied in order of 0, 1×?fat, 2×?fat, etc. Herein, ?fat=(2?TR/T_out+2×m)×? is established on the assumption that m denotes an integer equal to or larger than 0 and meets TR/(2×T_out)?1<m<TR/(2×T_out) where TR denotes the repetition time and T_out denotes the time during which spins in water and spins in fat are out of phase with each other due to chemical shifts. The image construction unit constructs an MR image Gw using the data D_?fat.

Abstract: In a method and MR apparatus for acquisition of images of an examination region of a human or animal body by means of measurement parameter sets controlling the image acquisition, selection of an examination region to be acquired is made by a user according to anatomical viewpoints by means of a whole-body representation of an image element of the body (stored in a storage region for image data) on a monitor. A list of measurement parameter sets for the selected region is displayed on the monitor, with the measurement parameter sets in the list each being shown with at least one region-specific image element (stored in a storage region) of an acquisition result that can be obtained with this measurement parameter set. A measurement parameter set for image acquisition is then selected.

Abstract: The present invention presents a new approach to rapidly obtaining precise high-dimensional NMR spectral information, named “GFT NMR spectroscopy”, which is based on the phase sensitive joint sampling of the indirect dimensions spanning a subspace of a conventional NMR experiment. The phase-sensitive joint sampling of several indirect dimensions of a high-dimensional NMR experiment leads to largely reduced minimum measurement times when compared to FT NMR. This allows one to avoid the “sampling limited” data collection regime. Concomitantly, the analysis of the resulting checmical shift multiplets, which are edited by the G-matrix transformation, yields increased precision for the measurement of the chemical shifts. Additionally, methods of conducting specific GFT NMR experiments as well as methods of conducting a combination of GFT NMR experiments for rapidly obtaining precise chemical shift assignment and determining the structure of proteins or other molecules are disclosed.

Abstract: A co-axial magnet configuration for the production of a magnetic field and investigational volume which is suitable for measurement of magnetic resonance has at least one superconducting solenoid coil or solenoid coils which are radially nested within each other, wherein the windings of the solenoid coil(s) in a radial region about the axis of the magnetic configuration are disposed between r1 and r2, wherein r1<r2 is characterized in that the windings are surrounded by at least one rotationally symmetric magnet body made from ferromagnetic material which extends over a radial region between r3 and r4 wherein r3<r4 wherein r2<r3<1.3 r2 and r4>1.

Abstract: An MRI apparatus in which a magnetic field is applied to a subject, a receiver coil attached to the subject receives a magnetic resonance signal generated in the subject, and a magnetic resonance image of the subject is generated from the magnetic resonance signal, the apparatus comprising a gantry which comprises a magnetic-field generating unit for generating the magnetic field, a determining unit which determines the type of the receiver coil, a first memory unit which stores data items representing a plurality of methods of attaching various receiver coils, each method designated for one receiver coil, and a monitor which is provided on the gantry and which displays one of the methods stored in the first memory unit, which pertains to the receiver coil whose type has been determined by the determining unit.

Abstract: An RF coil assembly includes a plurality of coil supports rotatably interconnected to each other. Each coil support is configured to rotate with respect to at least one adjoining coil support. A plurality of RF coils is connected to each coil support.

Abstract: An MRI apparatus includes an imaging signal acquisition unit, a motion signal acquisition unit, a motion amount determination unit, a motion correction unit and an image reconstruction unit. The imaging signal acquisition unit acquires MR signals as imaging signals. The motion signal acquisition unit repetitively acquires MR signals having PE amount less than that of the imaging signals as motion signals. The motion amount determination unit obtains a motion amount using the motion signals. The motion correction unit performs correction processing of the imaging signals in accordance with the motion amount. The image reconstruction unit reconstructs an image using the imaging signals after the correction processing.

Abstract: This invention concerns a method of making airborne geophysical measurements. Such measurements may be made from fixed or moving wing airplanes or dirigibles. The method comprises the following steps: taking first real time measurements from one, or more, geophysical instruments mounted in an aircraft to produce geophysical data related to the ground below that instrument. Taking second real time measurements from navigation and mapping instruments associated with or carried by the aircraft. Computing a background response of each geophysical instrument using the second real time measurements to take account of its time varying altitude, and the time varying topography of the ground below it. Adjusting an operating or data processing condition of each geophysical instrument using the respective background response and the instrument's attitude to enhance the performance of that instrument.

Abstract: A resistivity imaging device injects currents in two orthogonal directions using two pairs of return electrodes and performing impedance measurements of the buttons placed between the returns.

Abstract: A measuring device and a measuring method for non-destructive testing of an ignitor installed in a subassembly, particularly of a motor vehicle. The device and measuring method generate a measuring current with a predefined value, check-test the predefined value of the measuring current while bypassing the ignitor, apply the check-tested measuring current to the subassembly with the installed ignitor for a predefined time interval, determine the internal resistance of the subassembly with the installed ignitor, and derive a test signal indicating the installation condition based on a comparison with a setpoint value.

Abstract: A circuit arrangement for a line test and for feeding a corrosion protection current into a two-wire line comprises a controllable ramp generator for producing a ramp voltage, at least one first test impedance to be connected to a first line of a two-wire line, at least one second test impedance to be connected to a second line of the two-wire line, at least one first and second controllable switches for connecting the ramp voltage to the first and second test impedances, and a programmable control device for controlling the ramp generator and the first and second controllable switches in such a way so that the ramp voltage is coupled to the two-wire line in order to produce a corrosion protection current. The control device switches at least one of the first and second test impedances to the respective of the first and second lines for a line test.

Abstract: A method and system for measuring noise of an on-chip power supply. In an embodiment, the system comprises a delay line that receives as an input a signal such as a square wave. The delay line may comprise a series of inverters connected to the power supply. The output of the delay line may combine the input signal and the noise signal from the power supply to produce a series of delayed versions of the input signal. Analysis of the output signal yields characteristics associated with the noise signal of the power supply such as its spectrum. In another embodiment, the system may comprise at least one mixer that modulates an input signal, such as a sinusoid, with the noise signal of the power supply. Demodulating the mixed signal then yields the noise signal of the power supply for further analysis.

Abstract: A circuit configuration recognizes the occupancy of a seat and triggers a seat belt warning in a motor vehicle. Resistance elements are disposed in a separated and flat manner on a motor vehicle seat, in particular on a sensor seating mat, which alters the resistance values when a force is exerted thereon, for example, perpendicular to the surface of the vehicle seat, or by bending. The weight-sensitive resistance elements contain first resistance elements and additional resistance elements, and the resistance values thereof can be measured in respectively different measuring circuits without the measuring results for the first resistance elements influencing the measuring results for the additional resistance elements.

Abstract: A test fixture couples with a test instrument to measure impedance of a device. An upper layer of the test fixture has (a) a first and a second solder pad for electrical connection to the device, (b) a first, second, third and fourth multi-solder pad for electrical connection to four connectors, (c) a first conductor track for connecting the first solder pad to a signal solder pad of the first multi-solder pad, (d) a second conductor track for connecting the first solder pad to a signal solder pad of the second multi-solder pad, (e) a third conductor track for connecting the second solder pad to a signal solder pad of the third multi-solder pad, and (f) a fourth conductor track for connecting the second solder pad to a signal solder pad of the fourth multi-solder pad. Each multi-solder pad has at least one return path solder pad. A lower layer of the test fixture has conductor tracks connected to the return path solder pad of each multi-solder pad.

Abstract: A novel structure for a probe card that comprises a deformable metal or other deformable material for detecting excess overdrive and a method for using the same are disclosed. This detection structure may be positioned on the substrate along the bending path of the probe, such that should the probe experience excess overdrive, then the detection structure will permanently deform where it is hit by any portion of the probe. Alternatively, the detection structure may be embedded in the substrate, and may also function as a fiducial for alignment detection. Inspection of the probe card, and specifically the detection structure, will reveal whether any probe has experienced excess overdrive. Should the inspection reveal that certain regions of the card experienced excess overdrive, this may indicate a planarity problem that affects production line yield.

Abstract: A fault detection apparatus for surface mount packages is provided. The apparatus can include a retainer for releasably securing a circuit board such as a printed circuit board having an electrical component mounted thereon via a ball grid array surface mount package. When mounted within the apparatus, a test signal is applied to the electrical component. The apparatus includes a mechanical actuator, such as a solenoid, for applying a reciprocating force to the circuit board. The reciprocating force can disturb a defect in the ball grid array manifesting as a mechanically unreliable connection at one of the balls where an electrically intermittent connection is occurring. By disturbing the mechanically unreliable connection, the electrically intermittent connection can be caused to fail altogether and thereby reveal the defect as a test signal is carried through the printed circuit board.

Abstract: A probe card assembly has a probe contractor substrate having a plurality of probe contractor tips thereon and a probe card wiring board with an interposer disposed between the two. Support posts contacting the probe contractor substrate are vertically adjustable until secured by a locking mechanism which is coupled to the probe card wiring board. When the posts are secured in a fixed position, the position is one in which the plane of the plurality of probe contractor substrates is substantially parallel to a predetermined reference plane.

Abstract: An integrated circuit includes a current generator circuit with a first input terminal for applying a reference voltage and a second input terminal for applying an input voltage, which is generated internally from an externally applied supply voltage by a voltage generator circuit. The current generator circuit is connected to an output terminal via an interconnect. A first current flows on the interconnect in a test operating state of the integrated circuit. The current generator circuit generates a first partial current in a first test cycle of a test operating state and a second partial current in a subsequent second test cycle. The partial currents are each superposed on the first current on the interconnect. Consequently, three currents occur at the output terminal during the test operating state. The internally generated input voltage of the current generator circuit is determined from the three currents and the reference voltage.

Abstract: A semiconductor device has a boosting circuit configured to generate a boosting potential to an output line. An internal circuit is supplied with the boosting potential from the boosting circuit via the output line. A test line is connected to the output line. A control circuit is arranged between the output line and the test line and configured to shut off a current flowing into the test line from the output line during a boosting operation of the boosting circuit.

Abstract: An apparatus and method to test components in a semiconductor test structure. On a semiconductor wafer, a test module implemented in one or more scribe lines between a plurality of semiconductor dies is used to test components in the semiconductor test structure. The test module may, for example, test electrical characteristics of chains of vias, transistors, and functional devices, such as oscillators. The test module contains a scan chain control coupled through a plurality of pass gates to each component to be tested. The scan chain control sequentially closes the pass gates to separately test the components in the semiconductor test structure. The test module further interfaces with an external testing device and the results of each test are compared with the expected results to identify faulty components.

Abstract: Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between an automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher clock frequency than the automated testing equipment is configured to operate. In order to do so, the testing interface includes components configured for generating addresses and test data to be provided to the integrated circuit. A variety of test data patterns can be produced and the test data can be address dependent.

Abstract: A burn-in board for burn-in and electrical testing of a plurality of integrated circuit devices that is disposed in one or more processing trays may include a substrate having an interface surface and a plurality of electrical contacts disposed on the interface surface for establishing, through engagement with the one or more processing trays, electrical communication between the leads of the integrated circuit devices and a tester. One or more ports may be defined in the substrate so as to extend between the interface surface and another surface of the substrate wherein the port or ports are sized and configured to enable application of a negative pressure between the substrate and the one or more processing trays upon engagement of the substrate therewith and upon application of a vacuum through the one or more ports.

Abstract: A power MOSFET, comprising main and current mirror MOSFETs, has a current sense resistance coupled between its mirror and source terminals and a monitoring circuit responsive to a first voltage dependent upon current through the current sense resistance. The circuit arrangement includes a circuit that determines a second voltage, different from the first voltage, of a terminal of the current mirror MOSFET, and a circuit arranged to determine current of the power MOSFET in dependence upon the first and second voltages. The second voltage can be the voltage at the drain terminal, or the voltage at the mirror terminal with switching of the current sense resistance or a current that it passes. It can alternatively be determined by a control circuit to be a desired fraction of the drain voltage.

Abstract: An apparatus and a method testing liquid crystal display panel which are able to test whether or not burr remains on longer sides and on shorter sides of a unit liquid crystal display panel using first to fourth testing bars in a touch method, and able to measure a distance between the longer sides and a distance between the shorter sides of the unit liquid crystal display panel.

Abstract: A test probe having a conductive part electrically connected to terminals of a test-object device, including: a silicon substrate; a protrusion made of resin provided on the silicon substrate; a first conductive part which is provided on the protrusion and comes in contact with the terminals; and a second conductive part which is provided in a region other than a region having the protrusion on the silicon substrate and is electrically connected to the first conductive part.

Abstract: A display device includes first and second display signal lines, pixels, first and second sensing signal lines, first through fourth test lines for transmitting first through fourth test signals, a first switching element connected to the first and second test lines, and the first sensing signal line, second switching elements connected to the first switching element, the second test line, and a subset of first display signal lines, a third switching element connected to the third and fourth test lines, and the second sensing signal line, and fourth switching elements connected to the third switching element, the fourth test line, and a subset of second display signal lines.

Abstract: Multiplexer circuits that can be programmed to selectively balance the rising and falling delays through the circuits in the presence of process variations and/or variations in power levels. These multiplexer circuits can be used, for example, as programmable interconnect multiplexers in the interconnect structures of programmable logic devices (PLDs). A multiplexer circuit includes a multiplexer (e.g., driven by a plurality of interconnect lines in a PLD), a logic gate (e.g., an inverter) driven by the multiplexer, and a performance compensation circuit. The performance compensation circuit is coupled to the output terminal of the inverter, and has a compensation enable input terminal. The performance compensation circuit is coupled to adjust a trip point of the logic gate based on a value of a signal provided on the compensation enable input terminal.

Abstract: An apparatus for controlling an on die termination (ODT) includes a counting unit for receiving an external clock signal and a delay locked loop (DLL) clock signal, and counting the toggle number of each of external clock signal and the DLL clock signal from a preset number; a comparing control unit for comparing the counted toggle number of the external clock signal with that of the DLL clock signal in response to an ODT command signal, and outputting an ODT enable signal for controlling the ODT based on the compared result.

Abstract: A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and voltage-measuring and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, or other multiple die configuration. The programmable system-on-a-chip integrated circuit with voltage-measuring, current-measuring and control circuitry performs voltage measurement and control functions and can be used to control and monitor external power supplies connected to external loads.

Abstract: A programmable logic circuit (100) includes a processor element (101) having: a logic cell (300) which can modify the function according to first setting information and generates data by performing a predetermined logic calculation on an input signal; a cross connect switch (301) for generating data by performing alignment, copying, and inversion of the data from the logic calculation means according to second setting information; and a memory control unit (201) which reads out the first or the second setting information from a memory device (102) according to branch setting information and supplies it to the logic calculation means and the data processing means for performing control. According to the first and the second setting information successively read from the memory device (102), each of unit logic circuits successively modifies a part or whole of the logic cell (300) and the cross connect switch (301) and performs a predetermined sequence circuit operation.

Abstract: A field programmable gate array logic cell includes a logic circuit having three inputs and at least one output and a plurality of multiplexers having inputs and outputs. The logic circuit also includes a plurality of programmable elements coupled between the three inputs and at least one output of the logic circuit and the inputs and outputs of the plurality of multiplexers such that a plurality of sequential logic units and combinatorial units can be realized by programming selected ones of the programmable elements, the sequential logic units may include a flip-flop.

Abstract: A circuit board includes a large scale logic device and at least one outrigger device wherein signals having a transmission delay budget that exceed a threshold value are produced to the outrigger device for coupling to circuit devices of the circuit board that are external to the large scale logic device. One embodiment of the invention comprises a plurality of outrigger devices that communicate with the large scale logic device by way of parallel data buses, as well as multi-gigabit transceiver data lines. Logic within the outrigger devices is generally limited to signal routing and transmission logic. The large scale logic device further comprises logic to transmit and receive signals to and from the outrigger devices in a way that is transparent to internal logic of the large scale logic device.

Abstract: Embodiments of a high-speed level shifter are described. The level shifter may include a first transistor having a drain, a source, and a gate and a second transistor having a drain, a source, and a gate. The first and second transistors may be operable to receive a pair of differential signals. The level shifter may further include a third transistor having a drain, a source, and a gate, the drain of the third transistor directly coupled to the source of the first transistor, and the source of the third transistor directly coupled to the source of the second transistor. The gate of the third transistor is driven by a level-shifted version of an output voltage generated from the pair of differential signals.

Abstract: Circuits and methods are provided for transmitting a pseudo-differential output signal with relatively high immunity to noise and jitter. The output driver of the invention receives two differential input signals and outputs a single output signal with low voltage transistors and programmable impedance and on-die termination circuits. The pseudo-differential output driver consumes little circuit area and has low output capacitance.

Abstract: The input buffer is driven by a data input/output supply voltage. The input buffer generates an output signal from an input signal that swings between the data input/output supply voltage and a data input/output ground voltage.

Abstract: Provided is a multi-path input buffer circuit, which passes a signal input to a semiconductor device through different paths in consideration of the voltage level of the input signal. The multi-path input buffer circuit includes an input buffer stage, which can be driven using one of at least two power supply voltages, outputs path signals by passing an input signal through at least two paths, selects and enables one of the path signals in response to a plurality of path selection signals, and maintains the rest of the path signals in a high impedance state. The buffer circuit also includes a level shifter, which shifts the voltage level of a signal output from the input buffer stage via the first path, and a first logic operation circuit, which operates in response to the output signal of the input buffer stage and a signal output from the level shifter.

Abstract: A mixed-voltage interface transfers signals serially between a pair of circuit blocks operating at different voltage levels in a semiconductor integrated circuit. Control, address, and data signals are multiplexed onto a common signal line. The number of necessary signal lines is thereby greatly reduced, as compared with parallel signal transfer, and a separate electrostatic discharge protection circuit can be provided for each signal line without the need to devote excessive space to protection circuitry.

Abstract: A logic circuit for delaying a signal input thereto by a number of clock cycles X is described. In one embodiment, the logic circuit comprises a demultiplexer (“DEMUX”) which includes an input for receiving the signal and N outputs; a register array comprising at least X registers, wherein each of the N outputs of the DEMUX is connected to a corresponding one of the X registers; and a multiplexer (“MUX”) comprising M inputs, wherein each of the M inputs is connected to one of the registers.

Abstract: A gated clock logic circuit includes a pulse generator and a precharged latch. The pulse generator generates a pulse signal in response to a clock signal, and the precharged latch generates a gated clock signal in response to the clock signal, the pulse signal, and a control signal.

Abstract: A switching model to create stable binary sequential devices comprised of one or more logic functions with feedback of which an output signal is uniquely related to an input signal is applied to possible binary logic functions. Static latches of commutative and non-commutative binary functions are designed by using the switching model. Latches can be realized by individually controlled gates sometimes with inverters. Optical and electro-optical latches are disclosed. The application of transmission gates to realize latches is also disclosed.

Abstract: A waveform generator for generating a desired waveform is provided, including a noise kernel configured to store a plurality of samples from a predetermined waveform, the plurality of samples being assigned to a plurality of memory blocks; and an address arrangement configured to randomly select a selected one of the plurality of memory blocks; wherein the noise kernel is configured to communicate the plurality of samples assigned to the selected memory block.

Abstract: In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of ?9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.