Patents Issued in April 29, 2008
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Patent number: 7365378Abstract: A MOSFET structure and method of fabricating the structure incorporates a multi-layer sidewall spacer to suppress parasitic overlap capacitance between the gate conductor and the source/drain extensions without degrading drive current and, thereby, effecting overall MOSFET performance. The multi-layer sidewall spacer is formed with a gap layer having a dielectric constant equal to one and a permeable low-K (e.g., less than 3.5) dielectric layer. Alternatively, the multi-layer sidewall spacer is formed with a first L-shaped dielectric layer having a permittivity value of less than approximately three and a second dielectric layer. The multi-layer spacer may also have a third nitride or oxide spacer layer. This third spacer layer provides increased structural integrity.Type: GrantFiled: March 31, 2005Date of Patent: April 29, 2008Assignee: International Business Machines CorporationInventors: Elbert E. Huang, Philip J. Oldiges, Ghavam G. Shahidi, Christy S. Tyberg, Xinlin Wang, Robert L. Wisnieff
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Patent number: 7365379Abstract: A solid state image pickup device includes: a first area defined on a principal surface of a semiconductor substrate; a second area defined in an area adjacent to the first area along a first direction; and a third area defined in an area adjacent to the second area along the first direction, wherein the first area includes: a plurality of photoelectric conversion elements; and a plurality of vertical transfer channels formed adjacent to the plurality of photoelectric conversion elements; the second area includes: a horizontal transfer channel; and a floating diffusion region and a first stage drive FET of an amplifier; and the third area includes: a first state load FET, a second stage drive FET, a second stage load FET, a third stage drive FET and a third stage load FET, respectively of the amplifier. The solid state image pickup device can be made compact.Type: GrantFiled: June 13, 2005Date of Patent: April 29, 2008Assignee: Fujifilm CorporationInventors: Jin Murayama, Tatsuya Hagiwara
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Patent number: 7365380Abstract: An object of the present invention is to provide a photoelectric conversion device, wherein improvement of charge transfer properties when charge is output from a charge storage region and suppression of dark current generation during charge storage are compatible with each other. This object is achieved by forming a depletion voltage of a charge storage region in the range from zero to one half of a power source voltage (V), forming a gate voltage of a transfer MOS transistor during a charge transfer period in the range from one half of the power source voltage to the power source voltage (V) and forming a gate,voltage of the transfer MOS transistor during a charge storage period in the range from minus one half of the power source voltage to zero (V).Type: GrantFiled: August 31, 2005Date of Patent: April 29, 2008Assignee: Canon Kabushiki KaishaInventors: Hiroshi Yuzurihara, Seiichi Tamura, Ryuichi Mishima
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Patent number: 7365381Abstract: In a photodetector where a circuit section, in which an interconnection is formed, is formed adjacent to a light receiving section, photo sensitivity within a light receiving surface is prevented from being non-uniform due to an interlayer insulating film at a periphery of the light receiving section being increased in thickness. In a circuit region, a buffer region is disposed adjacent to a light receiving section. In the buffer region, in order to reduce irregularity of an interlayer insulating film, a density of planarizing pads disposed between the interconnections is gradually reduced from a standard value in a region as it approaches the light receiving section.Type: GrantFiled: November 17, 2006Date of Patent: April 29, 2008Assignee: Sanyo Electric Co., Ltd.Inventors: Akihiro Hasegawa, Yoji Nomura
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Patent number: 7365382Abstract: A semiconductor memory having charge trapping memory cells, where the direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.Type: GrantFiled: February 28, 2005Date of Patent: April 29, 2008Assignee: Infineon Technologies AGInventors: Josef Willer, Thomas Mikolajick, Christoph Ludwig, Norbert Schulze, Karl-Heinz Kuesters
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Patent number: 7365383Abstract: An EPROM cell includes a control gate and a control transistor. A portion of the control transistor is formed as a portion of the control gate.Type: GrantFiled: March 27, 2006Date of Patent: April 29, 2008Assignee: Semiconductor Components Industries, L.L.C.Inventors: Gennadiy Nemtsev, Yingping Zheng, Rajesh S. Nair
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Patent number: 7365384Abstract: A memory device includes isolation trenches that are formed generally parallel to and along associated strips of active area. A conductive bit line is recessed within each isolation trench such that the uppermost surface of the bit line is recessed below the uppermost surface of the base substrate. A bit line contact strap electrically couples the bit line to the active area both along a vertical dimension of the bit line strap and along a horizontal dimension across the uppermost surface of the base substrate.Type: GrantFiled: October 27, 2006Date of Patent: April 29, 2008Assignee: Micron Technology, Inc.Inventors: Luan C. Tran, Mark Durcan, Howard C. Kirsch
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Patent number: 7365385Abstract: DRAM cell arrays having a cell area of less than about 4F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is non-orthogonal to at least one of the vertical gate electrodes of the vertical transistors.Type: GrantFiled: August 30, 2004Date of Patent: April 29, 2008Assignee: Micron Technology, Inc.Inventor: Todd R. Abbott
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Patent number: 7365386Abstract: A semiconductor device having improved reliability is provided. The semiconductor device has a pixel portion. The pixel portion has a TFT and a storage capacitor. The TFT and the storage capacitor has a semiconductor layer which includes first and second regions formed continuously. The TFT has the first region of the semiconductor layer including a channel forming region, a source region and a drain region located outside the channel forming region, a gate insulating film adjacent to the first region of the semiconductor layer, and a gate electrode formed on the gate insulating film. The storage capacitor has the second region of the semiconductor layer, an insulating film formed adjacent to the second region of the semiconductor layer, and a capacitor wiring formed on the insulating film. The second region of the semiconductor layer contains an impurity element for imparting n-type or p-type conductivity.Type: GrantFiled: August 28, 2003Date of Patent: April 29, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tatsuya Arao, Hideomi Suzawa
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Patent number: 7365387Abstract: An EPROM cell in a printhead control circuit for an inkjet printer, having exactly one polysilicon layer and a conductive layer disposed above the polysilicon layer, includes a control transistor and an EPROM transistor. The control and EPROM transistors each have floating gates comprising a portion of the polysilicon layer, and an electrical interconnection, comprising a portion of the conductive layer, interconnects the floating gate of the control transistor and the floating gate of the EPROM transistor.Type: GrantFiled: February 23, 2006Date of Patent: April 29, 2008Assignee: Hewlett-Packard Development Company, L.P.Inventor: Trudy Benjamin
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Patent number: 7365388Abstract: The cell comprises a substrate having a drain region and a source region. An oxynitride layer is formed over the substrate. An embedded trap layer is formed over the oxynitride layer. An injector layer is formed over the embedded trap layer. A high dielectric constant layer is formed over the injector layer. A polysilicon control gate formed over the high dielectric constant layer. The cell can be formed in a planar architecture or a two element, split channel, three-dimensional device. The planar cell is formed with the high dielectric constant layer and the control gate being formed over and substantially around three sides of the embedded trap layer. The split channel device has a source line in the substrate under each trench and a bit line on either side of the trench.Type: GrantFiled: February 25, 2005Date of Patent: April 29, 2008Assignee: Micron Technology, Inc.Inventor: Arup Bhattacharyya
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Patent number: 7365389Abstract: A semiconductor memory device may include an intergate dielectric layer of a high-K, high barrier height dielectric material interposed between a charge storage layer and a control gate. With this intergate high-K, high barrier height dielectric in place, the memory device may be efficiently erased using Fowler-Nordheim tunneling.Type: GrantFiled: December 10, 2004Date of Patent: April 29, 2008Assignees: Spansion LLC, Advanced Micro Devices, Inc.Inventors: Joong Jeon, Wei Zheng, Mark Randolph, Meng Ding, Hidehiko Shiraiwa
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Patent number: 7365390Abstract: Provided is a method of fabricating a recess transistor in an integrated circuit device. In the provided method, a device isolation region, which contacts to the sidewall of a gate trench and a substrate region remaining between the sidewall of the device isolation region and the sidewall of the gate trench, is etched to expose the remaining substrate region. Thereafter, the exposed portion of the remaining substrate region is removed to form a substantially flat bottom of the gate trench. The recess transistor manufactured by the provided method has the same channel length regardless of the locations of the recess transistor in an active region.Type: GrantFiled: March 26, 2007Date of Patent: April 29, 2008Assignee: Samsung Electronics Co., Ltd.Inventor: Ji-Young Kim
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Patent number: 7365391Abstract: A semiconductor device having high withstand voltage is provided. An active groove 22a includes a long and narrow main groove part 26 and a sub groove part 27 connected to a longitudinal side surface of the main groove part, and a buried region 24 of a second conductivity type whose height is lower than the bottom surface of the base diffusion region 32a of the second conductivity type is provided on the bottom surface of the main groove part 26. An active groove filling region 25 of the second conductivity type in contact with the base diffusion region 32a is provided in the sub groove part 27. The buried region 24 is contacted to the base diffusion region 32a through the active groove filling region 25. Since one gate groove 83 is formed by the part above the buried region 24 in one active groove 22a, the gate electrode plugs 48 are not separated, which allows the electrode pattern to be simplified.Type: GrantFiled: September 28, 2006Date of Patent: April 29, 2008Assignee: Shindengen Electric Manufacturing Co., Ltd.Inventors: Toru Kurosaki, Shinji Kunori, Mizue Kitada, Kosuke Ohshima, Hiroaki Shishido, Masato Mikawa
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Patent number: 7365392Abstract: Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.Type: GrantFiled: December 14, 2004Date of Patent: April 29, 2008Assignee: Fuji Electric Co., Ltd.Inventors: Akio Sugi, Naoto Fujishima, Mutsumi Kitamura, Katsuya Tabuchi, Setsuko Wakimoto
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Patent number: 7365393Abstract: This invention provides a semiconductor device having high operation performance and high reliability. An LDD region 707 overlapping with a gate wiring is arranged in an n-channel TFT 802 forming a driving circuit, and a TFT structure highly resistant to hot carrier injection is achieved. LDD regions 717, 718, 719 and 720 not overlapping with a gate wiring are arranged in an n-channel TFT 804 forming a pixel unit. As a result, a TFT structure having a small OFF current value is achieved. In this instance, an element belonging to the Group 15 of the Periodic Table exists in a higher concentration in the LDD region 707 than in the LDD regions 717, 718, 719 and 720.Type: GrantFiled: September 21, 2004Date of Patent: April 29, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Satoshi Murakami, Jun Koyama, Yukio Tanaka, Hidehito Kitakado, Hideto Ohnumo
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Patent number: 7365394Abstract: Transistors are formed by depositing at least one layer of semiconductor material on a substrate comprising a polyphenylene polyimide. The substrate permits the use of processing temperatures in excess of 300° C. during the processes used to form the transistors, thus allowing the formation of high quality silicon semiconductor layers. The substrate also has a low coefficient of thermal expansion, which closely matches that of silicon, thus reducing any tendency for a silicon layer to crack or delaminate.Type: GrantFiled: August 17, 2004Date of Patent: April 29, 2008Assignee: E Ink CorporationInventors: Kevin L Denis, Yu Chen, Paul S Drzaic, Joseph M Jacobson, Peter T Kazlas
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Patent number: 7365395Abstract: Artificial dielectrics using nanostructures, such as nanowires, are disclosed. In embodiments, artificial dielectrics using other nanostructures, such as nanorods, nanotubes or nanoribbons and the like are disclosed. The artificial dielectric includes a dielectric material with a plurality of nanowires (or other nanostructures) embedded within the dielectric material. Very high dielectric constants can be achieved with an artificial dielectric using nanostructures. The dielectric constant can be adjusted by varying the length, diameter, carrier density, shape, aspect ratio, orientation and density of the nanostructures. Additionally, a controllable artificial dielectric using nanostructures, such as nanowires, is disclosed in which the dielectric constant can be dynamically adjusted by applying an electric field to the controllable artificial dielectric. A wide range of electronic devices can use artificial dielectrics with nanostructures to improve performance.Type: GrantFiled: August 15, 2005Date of Patent: April 29, 2008Assignee: Nanosys, Inc.Inventors: David P. Stumbo, Stephen A. Empedocles, Francisco Leon, J. Wallace Parce
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Patent number: 7365396Abstract: A memory device is formed on a semiconductor-on-insulator (SOI) structure, the SOI structure including a substrate, an insulating layer on the substrate, and a semiconductor film on the insulating layer. The memory device includes a memory array in a memory region of the SOI structure, a plurality of first substrate contacts in the peripheral region of the memory device, and a plurality of second substrate contacts in the memory region of the SOI structure, wherein the first substrate contacts and the second substrate contacts are formed in and over the semiconductor film and in the insulating layer and are electrically connected to the substrate of the SOI structure.Type: GrantFiled: April 14, 2005Date of Patent: April 29, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Ping-Wei Wang
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Patent number: 7365397Abstract: The semiconductor device comprises a resistance element 26 formed of polysilicon film formed on a silicon substrate 10, which includes a resistor part 26a having a resistance value set at a prescribed value, contact parts 26b formed on both sides of the resistor part 26a and connected to a line for applying a fixed potential, and a heat radiation part 26c connected to the contact part 26b, whereby the semiconductor device can include the resistance element having a small parasitic capacitance and good heat radiation.Type: GrantFiled: October 31, 2005Date of Patent: April 29, 2008Assignee: Fujitsu LimitedInventor: Hiroshi Nomura
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Patent number: 7365398Abstract: A highly dense form of static random-access memory (SRAM) takes advantage of transistor gates on both sides of silicon and high interconnectivity made possible by the complex form of silicon-on-insulator and three-dimensional integration. This technology allows one to form p-channel and n-channel devices very compactly by taking advantage of placement of gates on both sides, making common contacts and dense interconnections in 3D.Type: GrantFiled: February 11, 2005Date of Patent: April 29, 2008Assignee: Cornell Research Foundation, Inc.Inventors: Sandip Tiwari, Arvind Kumar
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Patent number: 7365399Abstract: A semiconducting material that has all the advantages of prior art SOI substrates including, for example, low parasitic capacitance and leakage, without having floating body effects is provided. More specifically, the present invention provides a Semiconductor-on-Pores (SOP) material that includes a top semiconductor layer and a bottom semiconductor layer, wherein the semiconductor layers are separated in at least one region by a porous semiconductor material. Semiconductor structures including the SOP material as a substrate as well as a method of fabricating the SOP material are also provided. The method includes forming a p-type region with a first semiconductor layer, converting the p-type region to a porous semiconductor material, sealing the upper surface of the porous semiconductor material by annealing, and forming a second semiconductor layer atop the porous semiconductor material.Type: GrantFiled: January 17, 2006Date of Patent: April 29, 2008Assignee: International Business Machines CorporationInventors: Joel P. de Souza, Keith E. Fogel, Brian J. Greene, Devendra K. Sadana, Haining S. Yang
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Patent number: 7365400Abstract: A method for manufacturing semiconductor device employs an EXTIGATE structure. In accordance with the method, a predetermined thickness of the device isolation film is etched to form a recess. The recess is then filled with a second nitride film. A stacked structure of a barrier metal film, a metal layer and a third nitride film on the second nitride film and the polysilicon film are formed on the entire surface and the etched via a photoetching process to form a gate electrode. An insulating film spacer is deposited on a sidewall of the gate electrode. The exposed portion of the polysilicon film uses the third nitride film pattern and the insulating film spacer as a mask to form a polysilicon film pattern and an oxide film on a sidewall of the polysilicon film pattern.Type: GrantFiled: September 7, 2005Date of Patent: April 29, 2008Assignee: Hynix Semiconductor Inc.Inventor: Sang Don Lee
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Patent number: 7365401Abstract: Embodiments herein present a device, method, etc. for a dual-plane complementary metal oxide semiconductor. The device comprises a fin-type transistor on a bulk silicon substrate. The fin-type transistor comprises outer fin regions and a center semiconductor fin region, wherein the center fin region has a {110} crystalline oriented channel surface. The outer fin regions comprise a strain inducing material that stresses the center semiconductor fin region. The strain inducing material contacts the bulk silicon substrate, wherein the strain inducing material comprises germanium and/or carbon. Further, the fin-type transistor comprises a thick oxide member on a top face thereof. The fin-type transistor also comprises a first transistor on a first crystalline oriented surface, wherein the device further comprises a second transistor on a second crystalline oriented surface that differs from the first crystalline oriented surface.Type: GrantFiled: March 28, 2006Date of Patent: April 29, 2008Assignee: International Business Machines CorporationInventors: Brent A. Anderson, Edward J. Nowak
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Patent number: 7365402Abstract: An LDMOS semiconductor transistor structure comprises a substrate having an epitaxial layer of a first conductivity type, a source region extending from a surface of the epitaxial layer of a second conductivity type, a lightly doped drain region within the epitaxial layer of a second conductivity type, a channel located between the drain and source regions, and a gate arranged above the channel within an insulating layer, wherein the lightly doped drain region comprises an implant region of the first conductivity type extending from the surface of the epitaxial layer into the epitaxial layer covering an end portion of the lightly doped drain region next to the gate.Type: GrantFiled: January 6, 2005Date of Patent: April 29, 2008Assignee: Infineon Technologies AGInventor: Gordon Ma
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Patent number: 7365403Abstract: A semiconductor topography is provided which includes a silicon dioxide layer with a thickness equal to or less than approximately 10 angstroms and a silicon nitride layer arranged upon the silicon dioxide layer. In addition, a method is provided which includes growing an oxide film upon a semiconductor topography in the presence of an ozonated substance and depositing a silicon nitride film upon the oxide film. In some embodiments, the method may include growing the oxide film in a first chamber at a first temperature and transferring the semiconductor topography from the first chamber to a second chamber while the semiconductor topography is exposed to a substantially similar temperature as the first temperature. In either embodiment, the method may be used to form a semiconductor device including an oxide-nitride gate dielectric having an electrical equivalent oxide gate dielectric thickness of less than approximately 20 angstroms.Type: GrantFiled: February 13, 2002Date of Patent: April 29, 2008Assignee: Cypress Semiconductor Corp.Inventor: Krishnaswamy Ramkumar
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Patent number: 7365404Abstract: A semiconductor device has a silicon substrate, an n-type well region formed in the silicon substrate, first and second source/drain regions constructed of a p-type diffusion layer formed on the n-type well region, a gate insulator formed in a region located between the first source/drain region and the second source/drain region and a polysilicon formed on the gate insulator. The semiconductor device has oxygen-rich layers for blocking a silicide reaction, which layers are formed in an uppermost portion of the silicon substrate on the side of the polysilicon, and has an oxygen-rich layer for blocking the silicide reaction, which layer is formed in an upper portion of the polysilicon.Type: GrantFiled: September 13, 2004Date of Patent: April 29, 2008Assignee: Sharp Kabushiki KaishaInventor: Kenichi Nagai
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Patent number: 7365405Abstract: A method of indicating the progress of a sacrificial material removal process, the method, comprising; freeing a portion of a member, the member being disposed in a cage and laterally surrounded by the sacrificial material; and preventing the freed portion of the member from floating away by retaining the freed member.Type: GrantFiled: April 27, 2004Date of Patent: April 29, 2008Inventors: Stephen J. Potochnik, Kenneth Faase
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Patent number: 7365406Abstract: A non-uniform ion implantation apparatus comprises a wide ion beam generator configured to generate a plurality of wide ion beams to irradiate at least two regions on the entire area of a wafer, and a wafer rotating device configured to rotate the wafer in a predetermined direction while the wide ion beams generated by the wide ion beam generator are irradiated to the wafer. Among the wide ion beams, at least one wide ion beam has a different dose from that of at least one different wide ion beam. Since the wide ion beams are irradiated at different doses to the wafer, a smooth circular border is formed between the regions to which the impurity ions are implanted to different concentrations. Since the position of the wafer is suitably changed for the wide ion beams, it is possible to control disposition of the regions implanted with the impurity ions of different concentrations.Type: GrantFiled: December 16, 2005Date of Patent: April 29, 2008Assignee: Hynix Semiconductor Inc.Inventors: Kyoung Bong Rouh, Seung Woo Jin, Min Yong Lee
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Patent number: 7365407Abstract: A packaged circuit and method for packaging an integrated circuit are disclosed. The packaged circuit has a lead frame, an integrated circuit chip, and an encapsulating layer. The lead frame has first and second sections, the first section including a lateral portion, a chip mounting area and a first extension. The integrated circuit chip is mounted in the chip mounting area and is in thermal contact with the chip mounting area. The encapsulating layer has top, bottom, and first and second side surfaces. The first extension is bent to provide a first heat path from the chip mounting area to the bottom surface. The heat path connects the heat chip mounting area to the bottom surface without passing through the first and second side surfaces and provides a heat path that has less thermal resistance than the heat path through either the lateral portion or the second section.Type: GrantFiled: May 1, 2006Date of Patent: April 29, 2008Assignee: Avago Technologies General IP Pte LtdInventors: Kee Yean Ng, Hui Peng Koay, Chiau Jin Lee, Kheng Leng Tan, Wei Liam Loo, Keat Chuan Ng, Alzar Abdul Karim Norfidathul
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Patent number: 7365408Abstract: A bi-layer anti-reflective coating for use in photolithographic applications, and specifically, for use in ultraviolet photolithographic processes. The bi-layered anti-reflective coating is used to minimize pattern distortion due to reflections from neighboring features in the construction of microcircuits. The bi-layer anti-reflection coating features a first layer, an absorption layer, disposed on a second layer, a dielectric layer, which is then disposed between a substrate and a photoresist layer. The dielectric/absorption layer comprises one combination selected from Ta/Al2O3, Ta/SiO2, Ta/TiO2, Ta/Ta2O5, Ta/Cr2O3, Ta/Si3N4, Ti/Al2O3, Ti/SiO2, Ti/TiO2, Ti/Ta2O5, Ti/Cr2O3, Ti/Si3N4, Cr/Al2O3, Cr/SiO2, Cr/TiO2, Cr/Ta2O5, Cr/Cr2O3, Cr/Si3N4, Al/Al2O3, Al/TiO2, Al/Ta2O5, Al/Cr2O3, Al/Si3N4, Ni/Al2O3, Ni/SiO2, Ni/TiO2, Ni/Ta2O5, Ni/Cr2O3, Ni/Si3N4, Ir/Al2O3, Ir/SiO2, Ir/TiO2, Ir/Ta2O5, Ir/Cr2O3, and Ir/Si3N4. At least the absorption and dielectric layers can be formed using vacuum deposition.Type: GrantFiled: April 30, 2002Date of Patent: April 29, 2008Assignee: International Business Machines CorporationInventors: James Bernard Kruger, Clint David Snyder, Patrick Rush Webb, Howard Gordon Zolla
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Patent number: 7365409Abstract: A two-transistor pixel of an imager has a reset region formed adjacent a charge collection region of a photodiode and in electrical communication with a gate of a source follower transistor. The reset region is connected to one terminal of a capacitor which integrates collected charge of the photodiode. The charge collection region is reset by pulsing the other terminal of the capacitor from a higher to a lower voltage.Type: GrantFiled: April 20, 2004Date of Patent: April 29, 2008Assignee: Micron Technology, Inc.Inventor: Eric R. Fossum
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Patent number: 7365410Abstract: A method for forming a semiconductor structure including providing a semiconductor substrate, forming a metallic buffer layer over the semiconductor substrate, forming an amorphous semiconductor layer over the metallic buffer layer, and recrystallizing the amorphous semiconductor layer to form a crystalline semiconductor layer. A semiconductor structure includes a semiconductor substrate, a buffer layer comprising at least one of silicide and germanide formed over the semiconductor substrate, and a crystalline semiconductor layer formed over the metallic buffer layer.Type: GrantFiled: October 29, 2004Date of Patent: April 29, 2008Assignee: Freescale, Semiconductor, Inc.Inventors: Alexander A. Demkov, William J. Taylor, Jr.
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Patent number: 7365411Abstract: A PCRAM memory device having a chalcogenide glass layer, preferably comprising antimony selenide having a stoichiometric formula of about Sb2Se3, and a metal-chalcogenide layer and methods of forming such a memory device.Type: GrantFiled: August 12, 2004Date of Patent: April 29, 2008Assignee: Micron Technology, Inc.Inventor: Kristy A. Campbell
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Patent number: 7365412Abstract: A capacitor structure uses an aperture located within a dielectric layer in turn located over a substrate. A pair of conductor interconnection layers embedded within the dielectric layer terminates at a pair of opposite sidewalls of the aperture. A pair of capacitor plates is located upon the pair of opposite sidewalls of the aperture and contacting the pair of conductor interconnection layers, but not filling the aperture. A capacitor dielectric layer is located interposed between the pair of capacitor plates and filling the aperture. The pair of capacitor plates may be formed using an anisotropic unmasked etch followed by a masked trim etch. Alternatively, the pair of capacitor plates may be formed using an unmasked anisotropic etch only, when the pair of opposite sidewalls of the aperture is vertical and separated by a second pair of opposite sidewalls that is outward sloped.Type: GrantFiled: April 12, 2006Date of Patent: April 29, 2008Assignee: International Business Machines CorporationInventors: Timothy J. Dalton, Jeffrey P. Gambino, Anthony K. Stamper
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Patent number: 7365413Abstract: Electrical interconnects with a slotting pattern are provided in the present invention. In addition, the masks for making such interconnects and semiconductor devices incorporating such interconnects are also provided in the present invention. The slotting pattern may be designed to minimize dishing effects of the interconnects as a result of planarization. Further, the slotting pattern may be designed to minimize resistance in the interconnects. For instance, the slotting pattern may include slots that are staggered, evenly aligned, or a combination of both staggered and evenly aligned. In addition, the slots may be spaced apart such that electrical paths are shorter across the interconnects. By incorporating such interconnects in semiconductor devices, better performing semiconductor devices can be realized.Type: GrantFiled: September 13, 2004Date of Patent: April 29, 2008Assignee: Altera CorporationInventors: Yaron Kretchmer, Fredrik Haghverdian
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Patent number: 7365414Abstract: Dielectric materials comprising release agents are described. Also described are a process for improving the proccessability of dielectric materials during hot embossing, substrates prepared by hot embossing, and integrated-circuit packages comprising the improved substrate.Type: GrantFiled: December 31, 2003Date of Patent: April 29, 2008Assignee: Intel CorporationInventors: Paul A. Koning, James C Matayabas, Jr.
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Patent number: 7365415Abstract: A semiconductor device has a mounting substrate and a semiconductor package mounted on the mounting substrate. The mounting substrate has a substrate body, input/output line conductors on the upper surface of the substrate body, a front-face grounding conductor on the upper surface of the substrate body, spaced from the input/output line conductors, and a lower surface grounding conductor formed on the lower surface of the substrate body and electrically connected to the front-face grounding conductor. The semiconductor package has input/output terminals electrically connected to end portions of the input/output line conductors, a grounding terminal electrically connected to the front-face grounding conductor, and a semiconductor element die-bonded on the grounding terminal and electrically connected to the input/output terminals.Type: GrantFiled: October 10, 2006Date of Patent: April 29, 2008Assignee: Mitsubishi Electric CorporationInventor: Kenichiro Chomei
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Patent number: 7365416Abstract: A semiconductor module is formed by alternately stacking resin boards 3 on which semiconductor chips 2 are mounted and sheet members having openings larger than the semiconductor chips 2 and bonded to the resin boards 3. The resin board 4 located at the bottom out of the resin boards 3 is thicker than the other resin boards 3.Type: GrantFiled: October 5, 2005Date of Patent: April 29, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takeshi Kawabata, Motoaki Satou, Toshiyuki Fukuda, Toshio Tsuda, Kazuhiro Nobori, Seiichi Nakatani
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Patent number: 7365417Abstract: An integrated circuit package system is provided attaching a film to a die paddle, applying an adhesive to the film, and attaching an integrated circuit die over the adhesive and the film to the die paddle.Type: GrantFiled: January 6, 2006Date of Patent: April 29, 2008Assignee: Stats Chippac Ltd.Inventors: Zigmund Ramirez Camacho, Henry D. Bathan, Arnel Trasporto, Jeffrey D. Punzalan
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Patent number: 7365418Abstract: A multi-chip structure at least including a first chip, a second chip and a first thermal-conductive layer is provided. The first chip has a first surface and a plurality of first pads disposed on the first surface. The second chip has a second surface facing the first surface and a plurality of second pads disposed on the second surface. The first thermal-conductive layer is disposed between the first chip and the second chip and includes a thermal-conductive area, a plurality of first electrical connection members and a plurality of first dielectric areas. The first electrical connection members disposed in the first thermal-conductive layer are used to electrically connect the first surface and the second surface. The first dielectric areas surround and insulate the first electrical connection members from the thermal-conductive area.Type: GrantFiled: September 22, 2006Date of Patent: April 29, 2008Assignee: VIA Technologies, Inc.Inventor: Chi-Hsing Hsu
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Patent number: 7365419Abstract: A chip includes a plurality of pins; and a plurality of symbols defined on a surface of the chip, wherein the symbols are arranged as a graduated scale corresponding with the pins. It becomes very easy to find a initial pin from among the plurality of pins of the chip.Type: GrantFiled: August 18, 2006Date of Patent: April 29, 2008Assignee: Hon Hai Precision Industry Co., Ltd.Inventor: Ming-Chih Hsieh
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Patent number: 7365420Abstract: A semiconductor package is provided which includes a substrate having a plurality of semiconductor dice mounted thereon. The substrate is divided into segments by grooves formed in the bottom surface of the substrate. Each semiconductor die is electrically connected to the substrate by electrical connections which extend from bond pads on the semiconductor die to corresponding bond pads on the substrate. An encapsulant is formed over each segment and contains grooves which correspond to the grooves of the substrate. Break points are thus formed at the grooves to permit the segments to be easily detached from the substrate to form individual integrated circuits.Type: GrantFiled: April 18, 2006Date of Patent: April 29, 2008Assignee: Micron Technology, Inc.Inventor: David J. Corisis
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Patent number: 7365421Abstract: An IC chip package includes a substrate (2), a chip (5), a plurality of bonding wires (52), and a cover (6). The substrate has a top surface, a receiving chamber (23) having an opening at the top surface, a plurality of solder pads (3) arranged around the top surface and respectively corresponding to the solder pads arranged at a bottom surface opposite to the top surface, and a plurality of vias (4) having conductive material electrically connecting the top solder pads with the bottom solder pads defined therein. The chip is mounted in the receiving chamber, and has a plurality of chip solder pads (51) arranged around a top surface thereof. The bonding wires respectively electrically connect the top solder pads of the substrate with the chip solder pads. The cover is fastened to the top surface of the substrate, and covers the opening.Type: GrantFiled: October 31, 2005Date of Patent: April 29, 2008Assignee: Altus Technology Inc.Inventors: Steven Webster, Ying-Cheng Wu, Kun-Hsieh Liu, Po-Chih Hsu
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Patent number: 7365422Abstract: A package of a leadframe with heatsinks, including a leadframe, a die, a first heatsink and a second heatsink. The leadframe has a die pad and a plurality of leads, and the leads are disposed around the die pad. The die is disposed on the die pad. The first heatsink is disposed on a first side of the leadframe and has a plurality of first positioning portions. The second heatsink is disposed on a second side of the leadframe. The second heatsink has a plurality of second positioning portions. The second positioning portions correspond to the first positioning portions of the first heatsink, whereby the warping problem of the leadframe is resolved.Type: GrantFiled: December 21, 2005Date of Patent: April 29, 2008Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Pai-Chou Liu, Jun-Cheng Liu, Kenneth Kinhang Ku, Yu-Li Chung
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Patent number: 7365423Abstract: A semiconductor package has a thinned semiconductor die fixed in a shallow opening in a conductive body. The die electrodes at the bottom of the die are plated with a redistributed contact which overlaps the die bottom contact and an insulation body which fills the annular gap between the die and opening. A process is described for the manufacture of the package in which plural spaced openings in a lead frame body and are simultaneously processed and singulated at the end of the process.Type: GrantFiled: April 20, 2007Date of Patent: April 29, 2008Assignee: International Rectifier CorporationInventor: Mark Pavier
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Patent number: 7365424Abstract: The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one particular implementation, a microelectronic component assembly includes a microelectronic component, a substrate, and at least one bond wire. The substrate has a reduced-thickness base adjacent terminals of the microelectronic component and a body having a contact surface spaced farther from the microelectronic component than a bond pad surface of the base. The bond wire couples the microelectronic component to a bond pad carried by the bond pad surface and has a maximum height outwardly from the microelectronic component that is no greater than the height of the contact surface from the microelectronic component.Type: GrantFiled: May 18, 2006Date of Patent: April 29, 2008Assignee: Micron Technology, Inc.Inventors: Eric Tan Swee Seng, Edmund Low Kwok Chung
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Patent number: 7365425Abstract: According to a heat radiation structure of a semiconductor element of the invention, by providing a recess for a thermal conductive sheet on the bottom surface of a mounting seat of a heat sink, disposing the thermal conductive sheet in this recess, and screwing a source electrode of a power FET on the bottom surface of the mounting seat of the heat sink, it is possible to efficiently radiate the heat generated by the semiconductor element without damaging semiconductor chips in the interior of the semiconductor element and without deteriorating electrical properties.Type: GrantFiled: December 10, 2004Date of Patent: April 29, 2008Assignee: NEC CorporationInventor: Makoto Hayakawa
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Patent number: 7365426Abstract: In a semiconductor device adapted to be mounted on a board and to be electrically connected to the board, comprising, at least two semiconductor electric chips, and a substrate on which the semiconductor electric chips are mounted and to which the semiconductor electric chips are electrically connected, in such a manner that the semiconductor electric chips are mounted on and electrically connected to the board through the substrate, according to the present invention, a thickness of each of the semiconductor electric chips in a direction in which the each of the semiconductor electric chips and the substrate are stacked is smaller than a thickness of the substrate in the direction.Type: GrantFiled: April 14, 2006Date of Patent: April 29, 2008Assignee: Renesas Technology Corp.Inventors: Yasuhiro Naka, Naotaka Tanaka, Ikuo Yoshida, Satoshi Imasu, Takahiro Naito
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Patent number: 7365427Abstract: The present invention relates to a stackable semiconductor package, comprising a first substrate, a chip, a second substrate, a plurality of second wires, a plurality of supporting elements and a molding compound. The chip is disposed on and electrically connected to the first substrate. The second substrate is disposed above the chip, and the area of the second substrate is larger than that of the chip. The second substrate is electrically connected to the first substrate by the second wires. The supporting elements are disposed between the first substrate and the second substrate, and are used for supporting the second substrate. The molding compound encapsulates the first surface of the first substrate, the chip, the second wires, the supporting elements and part of the second substrate, and exposes a surface of the second substrate. The overhang portion of the second substrate will not shake or sway during wire bonding process.Type: GrantFiled: December 26, 2006Date of Patent: April 29, 2008Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Yung-Li Lu, Gwo-Liang Weng