Abstract: An apparatus including a micropin thermal solution is described. The apparatus comprises a substrate and a number of micropins thermally coupled to the substrate. The micropins are arranged in a pixel like pattern over the substrate.

Abstract: A fluid-cooled electronic assembly including a base having a fluid inlet and a fluid outlet therein, a cap attached to the base to form a fluid containment chamber therebetween, wherein the fluid containment chamber is in fluid communication with the fluid inlet and the fluid outlet, and an electronic device disposed within the fluid containment chamber and connected to the base, the electronic device having a plurality of microchannels adapted to receive a cooling fluid flow therethrough, wherein the cap is shaped to direct a fluid flow from the fluid inlet to the microchannels such that a pressure drop between the fluid inlet and the fluid outlet is reduced.

Abstract: A liquid cooling device (10) includes a heat sink (12), a reservoir (14) containing liquid therein and distant from the heat sink, and a heat-transfer member. The heat-transfer member includes a heat-absorbing segment (162) contacting the heat sink and a heat-discharging segment (164) submerged in the liquid of the reservoir.

Abstract: A grease protecting apparatus (10) includes a heat sink (12) defining a plurality of receiving cavities (124) therein, a layer of grease (16) spread on a surface (122) of the heat sink, and a grease cover (14) attached to the surface of the heat sink for protecting the grease from contamination. The cover includes a main body (142) defining a protecting space (143) therein for covering the grease, two wings (144) extending from two opposite sides of the main body, and a plurality of projections (148) extending from the wings for being snapped in the receiving cavities of the heat sink. The projection has a trapezium-shaped cross section.

Abstract: A display module having an improved heatsink effect may include a display panel reproducing an image, a chassis supporting the display panel, a driving circuit board disposed on a surface of the chassis opposite to the display panel to generate an electrical signal for driving the display panel, the driving circuit board including at least one heat emissive circuit element, a first heatsink disposed on the heat emissive circuit element and a second heatsink disposed on the chassis. The first heatsink and the second heatsink may be thermally connected by a foldable connecting member.

Abstract: A memory module assembly includes two-plate heat sink attached to one or more of the integrated circuits (e.g., memory devices) of a memory module PCBA by adhesive. The adhesive is either heat-activated or heat-cured. The adhesive is applied to either the memory devices or the heat-sink plates, and then compressed between the heat-sink plates and memory module using a fixture. The fixture is then passed through an oven to activate/cure the adhesive. The two heat sink plates are connected together to form a rigid frame.

Abstract: To prevent occurrence of distortion in a semiconductor cooling device and to prevent a semiconductor chip from being separated away from the semiconductor cooling device in case the semiconductor chip and the semiconductor cooling device are thermally expanded, a semiconductor cooling device includes at least an upper plate, an intermediate plate and a lower plate, and has a coolant inlet portion, an outlet portion and a flow passage portion. The upper plate and the lower plate are composite plates constituted by plating copper maintaining a thickness of not smaller than 0.05 mm on one surface or on both surfaces of auxiliary plates made of a material having a tensile strength of not smaller than 1000 N/mm2, a heat conductivity of not smaller than 100 W/m·K and a coefficient of thermal expansion of not larger than 6.0 ppm/° C.

Abstract: A circuit board having a first IC chip mounted thereon, and a first heat sink having a base portion disposed to contact a surface of the first IC chip and having a plurality of heat-dissipating fins, wherein the heat-dissipating fins extend away from the base portion and are inclined at an angle other than 90° from an imaginary horizontal plane.

Abstract: A graphite heat spreader is provided for use with a flash LED light source for a camera of a handheld device such as a cell phone. Dramatically reduced operating temperatures are provided at substantially increased power levels thus providing both improved lighting and improved operating life of the electronic components.

Abstract: A heat dissipating device mounted onto a VGA card (10) includes a base (22) contacting with a GPU (12) attached on the VGA card, a cover (21) mounted on the base, and a plurality of fins (24) received between and thermally connecting the cover and the base. The base defines a slot (222) above the GPU. A fan (28) is positioned on the base for driving an airflow, wherein one portion of the airflow flows through the fins and another portion of the airflow flows through the slot and blows over other electronic components near to the GPU. Thus, rebounding of the airflow is reduced, and the heat dissipating device has better heat dissipating efficiency.

Abstract: A circuit board arrangement includes a heat dissipater. A cooling body is arranged near a first circuit board and a second circuit board. Both circuit boards have electronic devices on two major surfaces. The cooling body is arranged between the electronic devices on one surface of the first circuit board and the electronic devices on one surface of the second circuit board. The circuit boards are supported by fixing elements of the cooling body.

Abstract: Circuit boards for lighting systems have identical LED landing zones printed on the board. Each zone includes at least two sets of LED contact pads. One pad set is configured to mate with contacts of an LED of a first structural type, e.g. from a first product line or manufacturer. The other pad set is configured to mate with contacts of an LED of a second type, e.g. from a different product line or manufacturer. The layout may enable an easy system re-design, e.g. to shift from one type of LED to another. Alternatively, the layout may enable one system to use LEDs of the two different types in a single LED set or array. Exemplary systems disclosed herein include an element for mixing light produced by LEDs mounted to the landing zones, such as an optical integrating cavity.

Abstract: An electronic circuit package includes a first electronic module, a second electronic module, and an electric shielding layer. The first electronic module and the second electronic module are bonded in such a way that integrated devices are opposite to each other. The electric shielding layer is inserted between the first electronic module and the second electronic module for ensuring electric insulation between the first electronic module and the second electronic module.

Abstract: A mounting apparatus for fixing an expansion card (20) in a base (10), the mounting apparatus includes a receiving portion (30), a bracket (40) and a latch (50). The receiving portion (30) is formed from the base (10) for receiving one end of the expansion card (20) therein, and the bracket (40) is formed from the base (10) opposite to the receiving portion (30). The latch (50) is rotatablely fixed in the bracket (40). The latch (50) includes a main body (55), a handle portion (52) and a pedestal (51) extending from two end of the main body (55) respectively, and the other end of the expansion card (20) is engaged between the handle portion (52) and the pedestal (51).

Abstract: A bracket for an expansion card slot in a rear panel of a computer enclosure includes a main portion, a securing portion, and a connecting portion. The main portion includes an inserting portion formed from one end thereof, a securing portion perpendicularly outwardly bent from another end of the main portion. The securing portion defines a notch therein. The connecting portion recesses inwardly from the main portion, and includes a latching opening and a locating hole. The locating hole and the latching opening cooperatively define a shape that is similar with the connector, for allowing the connector to extend therethrough and then offset to engage with the connecting portion. In assembly the bracket to the rear panel, the inserting portion and the securing potion are engaged on the bracket. The connector can be readily installed or removed to or from the bracket.

Abstract: A power converter may include a transformer having a primary winding and a secondary winding. A first high side switch and a first low side switch may be coupled in series along a first path of a full bridge circuit, having a first node between the first high side switch and the first low side switch. The power converter may also comprise a second high side switch and a second low side switch coupled in series along a second path of the full bridge circuit, having a second node between the second high side switch and the second low side switch. The power converter may further comprise a first path capable of providing a first rectifier drive signal from the first node to a second rectifier switch, and a second path capable of providing a second rectifier drive signal from the second node to a first rectifier switch.

Abstract: A switched-mode power supply for converting a DC input voltage (Uzk) into an output voltage (Ua). The switched-mode power supply comprises a circuit (AST) for triggering at least one controlled switch (S) that periodically applies the input voltage to at least one primary winding (Wp) of a transformer (UET). An auxiliary voltage for the triggering circuit can be switched off with the aid of an auxiliary semiconductor switch (Ts) when the input voltage drops below a given minimum value, the auxiliary voltage consisting of a first auxiliary supply voltage (Uh) diverted from the input voltage and a second auxiliary supply voltage (Uhl) diverted from a secondary winding (Wh) of the transformer by means of rectification.

Abstract: The present invention provides a synchronous switching control circuit for variable switching frequency power converters. It comprises a first circuit to generate a first signal in response to an input synchronous signal of a power converter. A second circuit is coupled to the first circuit to generate a second signal in accordance with the frequency of the first signal. Only when the first signal is operated in a specific frequency range, the synchronous operation is allowed. An oscillation circuit is connected to the first circuit and the second circuit to receive the first signal and the second signal to generate an oscillation signal. The oscillation signal is utilized to enable the switching signal of the power converter. The switching signal is thus synchronized with the input synchronous signal in response to the enable of the second signal. Otherwise, the switching signal will be free running.

Abstract: An unregulated isolated DC/DC converter is configured to receive an input signal and to provide an output signal. A ripple control circuit is coupled to the unregulated isolated DC/DC converter, wherein the ripple control circuit is configured to reduce an amount of low frequency ripple transferred to the output signal from the input signal.

Abstract: In an up-converter supplied by the mains supply and operating in the critical mode, the on-time of the switching element (2) is modulated so that it is increased in the vicinity of the zero crossings of the mains supply voltage. As a result the THD is lowered.

Abstract: A half bridge inverter includes a push/pull control chip outputting a first control signal and a second control signal. Each duty cycle of the two control signals is smaller than 50%. Moreover, both a first buffer circuit and a second buffer circuit are coupled to the push/pull control chip. A driver couples to the first buffer circuit through the push/pull control chip and couples to a DC power for receiving the first control signal. A half bridge switch assembly with two N-MOSes couples to the DC power, the driver, the second buffer circuit and a transformer, and converts the DC power into an AC power by the driver. The AC power is transmitted to a first side of the transformer.

Abstract: The range-specified IP addresses are effectively stored to reduce the number of necessary entries thereby the memory capacity of TCAM is improved. The representative means of the present invention is that: the storage information (entry) and the input information (comparison information or search key) are the common block code such that any bit must be the logical value ‘1’; Match-lines are hierarchically structured and memory cells are arranged at the intersecting points of a plurality of sub-match lines and a plurality of search lines; Further the sub-match lines are connected to main-match lines through the sub-match detectors, respectively and main-match detectors are arranged on the main-match lines.

Abstract: It is proposed that bitline inversion coding data be integrally stored in the structure of a column multiplexer of a storage device. For this purpose, connections to a predefined potential are selectively provided at connection points, which are respectively assigned to one of the bitlines connected to the column multiplexer, in dependence on whether or not the assignment of a first state and of a second state of memory cells, connected to the bitline, to a binary value “0” and to a binary value “1” is inverted for the respective bitline. The connection points are connected to a common nodal point via switching means. The switching means are activated through control signals of the column multiplexer. Selection signals for activating inverter means, in order to effect a selective inversion of values read out from the memory cells, are generated in dependence on the signal level at the common nodal point.

Abstract: A method and apparatus are disclosed for sensing the resistance state of a resistance-based memory element using complementary resistance-based elements, one holding the resistance state being sensed and the other holding a complementary resistance state. A sense amplifier detects voltages discharging through the high and low resistance elements to determine the resistance state of an element being read.

Abstract: A memory capable of suppressing reduction of a reading voltage in data reading regardless of dispersion in a manufacturing process is provided. This memory comprises charge storage means, a first field-effect transistor and data determination means. The memory sets a voltage between a control terminal and a remaining first terminal of the first field-effect transistor to a threshold voltage for bringing the first field-effect transistor into an OFF-state in the vicinity of a boundary state between ON- and OFF-states through the threshold voltage of the first field-effect transistor.

Abstract: A ferroelectric memory device including: a first bit line which extends, from one end toward another end thereof, in a first direction; a plurality of first memory cells, which are connected to the first bit line and store predetermined data; a second bit line which extends, from one end toward another end thereof, in a second direction, which is a direction substantially opposite to the first direction; a plurality of second memory cells, which are connected to the second bit line and store predetermined data; a sense amplifier, which is connected to the one end of the first bit line and the one end of the second bit line, and which amplifies data which have been stored at the first memory cells and the second memory cells; a latch circuit, which is connected to the other end of the first bit line, and which latches data that the sense amplifier has amplified; a data bus, which transfers data which are to be stored at the first memory cells and the second memory cells; and a first switch, which is connected

Abstract: A Static Random Access Memory (SRAM) matrix with a read assist is described. The read assist reduces the probability associated with an SRAM matrix becoming upset by a radiation event. Each SRAM cell within the SRAM matrix includes an active delay for increasing Single Event Upset (SEU) tolerance. The described SRAM matrix also includes a read assist coupled to each column of the SRAM matrix. The read assists store values associated with a row of SRAM cells, one SRAM cell of which is to be written to. If a radiation event occurs on any of the SRAM cells not being written to, the read assist restores an original value associated with the upset SRAM cell.

Abstract: A semiconductor memory device capable of performing a high-speed write operation at lower voltage without increasing the word line activation period at normal voltage. The memory device has a write circuit including two NMOS transistors respectively having sources connected to ground potential. One of the transistors has a drain connected to one of a pair of bit lines, and the other transistor has a drain connected to the other bit line. The memory device also has a column selecting and data input circuit which generates a logical product of inverted data of data to be written and a write column selecting signal, inputs the logical product to the gate of the one transistor, generates a logical product of the data to be written and the write column selecting signal, and inputs the logical product to the gate of the other transistor.

Abstract: In an integrated circuit, a radiation tolerant static random access memory device comprising a first inverter having an input and an output, a second inverter having an input and an output. A first resistor is coupled between the output of the first inverter and the input of the second inverter. A second resistor is coupled between the output of the second inverter and the input of the first inverter. A first write transistor is coupled to the output of the first inverter and has a gate coupled to a source of a first set of write-control signals and a second write transistor is coupled to the output of the second inverter and has a gate coupled to said source of a second set of write-control signals. Finally, a pass transistor has a gate coupled to the output of on of the first and second inverters.

Abstract: A magnetoresistive device is provided with separate read and write architecture. In one embodiment, a magnetic tunnel junction (MTJ) has a nonmagnetic nonconductive barrier layer sandwiched between two ferromagnetic conducting layers. A first read line is coupled to a first ferromagnetic layer and a second read line is coupled to a second ferromagnetic layer such that a voltage difference between the two read lines will produce a current flowing perpendicularly through each layer of the MTJ. A first write line is separated from the first read line by a first insulator and a second write line is separated from the second read line by a second insulator.

Abstract: A TMR element has a free first magnetic layer, a second magnetic layer with a magnetization direction B fixed, a nonmagnetic insulating layer provided between the first magnetic layer and the second magnetic layer, a third magnetic layer provided above a surface of the first magnetic layer and having a fixed magnetization direction, and a first nonmagnetic conductive layer provided between the first magnetic layer and the third magnetic layer, and an area of a cross section of the first magnetic layer perpendicular to a stack direction is not less than 0.001 ?m2, and less than 0.02 ?m2.

Abstract: A low-power memory device that uses hole-mediated ferromagnetism creates substantial advantages over conventional systems. Some of these advantages include reducing power consumption by several orders of magnitude and facilitating wireless monitoring of memory cells. In one implementation, an electronic device is described that includes a plurality of memory cells. Each of the memory cells has a material with first and second magnetic states. The material is in the first magnetic state when a contact associated with the material is at a first voltage, and the material is in the second magnetic state when the contact is at a second voltage. A conductor is positioned proximate to and extending around the plurality of memory cells. An inductive voltage across the conductor varies when at least one of the memory cells changes magnetic state. A detection device determines the magnetic state of the memory cells based on an inductive voltage measurement.

Abstract: A synchronous non-volatile memory device that includes a circuit for performing operations on the memory device, a circuit for receiving a request of operation and operative information required for performing the operation in temporal succession, an activation circuit for activating the circuit in response to the request of operation, a circuit for enabling the execution of the operation in response to the operative information, and a deactivation circuit for deactivating the operations performing circuit in response to the completion of the operation.

Abstract: A multiple level cell memory array has an area that can be programmed as single level cells. The cells to be programmed are initially programmed with the desire data into either the least significant or most significant bit of the cell. A second programming operation the programs reinforcing data that adjusts the threshold level of the cell to the appropriate level for the desired data.

Abstract: A method for programming an electrically programmable memory including a plurality of memory cells arranged in individually-selectable memory cell sets each including at least one memory cell. The programming method includes causing the memory cells of a selected memory cells set to be brought into a predetermined, starting programming state. Receiving a target value for the first data bits groups of the memory cells of the selected memory cells set. Receiving a target value for the second data bits groups of the memory cells of the selected memory cells set. After having received the target values of both the first and the second data bits groups, applying to the memory cells of the selected memory cells set a programming sequence adapted to cause the memory cells of the selected memory cells sets to be brought into a target programming state jointly determined by the target values of the first and second data bits groups.

Abstract: A semiconductor integrated device having a plurality of memory cells, each including a floating gate, a control gate and an auxiliary gate formed over a side surface of the floating gate through an insulator film. Auxiliary gates coupled to selected memory cells function to generate hot electrons and are alternately arranged with other auxiliary gates functioning to prevent write errors in the non-selected memory cells.

Abstract: Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.

Abstract: A method and apparatus for programming one or more bits in an upper page twice depending on the value in a corresponding bit in a corresponding lower page in a multi-level cell device. The method includes the steps of initializing the bit in the lower page and the bit in the upper page by storing a value of one in each of the bits. One or more bits in the lower page are then programmed such that a one is stored in the one or more bits of the lower page. One or more bits in the upper page are then programmed such that a one is stored in the one or more bits of the upper page. The one or more bits in the upper page are then reprogrammed such that the value in the one or more bits of the upper page transitions from a one to a zero. The transition from a one to a zero in the one or more bits of the upper page is used to mark for performance of a block management function the block.

Abstract: In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A control circuit controls the potentials of the word lines and bit lines. The control circuit, when reading data from the memory cell connected to a first one of the bit lines, supplies a first voltage to a second bit line provided next to the first bit line and to a source line of the memory cell array.

Abstract: There is provided a non-volatile memory capable of being supplied with two varieties of externally supplied voltages, stabilizing the operation thereof, at a voltage in the vicinity of a threshold voltage for switching over between the externally supplied voltages, and stabilizing the operation thereof, at the times of writing and erasing, respectively. The non-volatile memory comprises a power supply circuit incorporating a hysteresis comparator having two voltage levels for the threshold voltage, wherein by detection of 2.3V at a time when an externally supplied voltage rises, a detection signal goes to an “H” level, whereupon an internal step-down circuit, made up of a constant voltage circuit, and so forth, comes into action, generating an internal operation voltage at 2.2V to be subsequently supplied, and thereafter, by detection of 2.1V, the detection signal goes to an “L” level, whereupon the externally supplied voltage, as it is, is supplied as the internal operation voltage.

Abstract: We describe a NAND flash memory device including a memory cell array formed on a substrate including a plurality of cell strings each including a string selecting transistor, a ground selecting transistor, and plural memory cells serially coupled between the string selecting transistor and the ground selecting transistor. A high voltage generator is configured to supply a bulk voltage to the substrate and an erase control circuit is configured to stepwise increase the bulk voltage during a first period of an erase operation and to maintain the bulk voltage substantially constant during a second period of the erase operation.

Abstract: A simple method and device for accurately measuring flash memory cell current. The sensing scheme comprises an integrator, an analog to digital converter, and a digital to analog converter. The method comprises the acts of applying an input current and a feedback output current to a summer, integrating the resulting summer output over time, passing the integrated output to a clocked comparator, outputting a comparator output which controls a feedback circuit that keeps the integrator's voltage at the same level as a reference voltage, and outputting a digital average current to a counter. Delta sigma modulation (averaging) is employed to cancel out noise that would otherwise affect the cell current measurement.

Abstract: In a non-volatile memory, the initiation of program verification is adaptively set so that programming time is decreased. In one approach, non-volatile storage elements are programmed based on a lower page of data to have a voltage threshold (VTH) that falls within a first VTH distribution or a higher, intermediate VTH distribution. Subsequently, the non-volatile storage elements with the first VTH distribution either remain there, or are programmed to a second VTH distribution, based on an upper page of data. The non-volatile storage elements with the intermediate VTH distribution are programmed to third and fourth VTH distributions. The non-volatile storage elements being programmed to the third VTH distribution are specially identified and tracked. Verification of the non-volatile storage elements being programmed to the fourth VTH distribution is initiated after one of the identified non-volatile storage elements transitions to the third VTH distribution from the intermediate VTH distribution.

Abstract: A flash memory device includes first to nth banks sharing an I/O line, a page buffer unit commonly connected to a bit line of the first to nth banks, for buffering data to be transmitted to the first to nth banks, a first X-decoder connected to a word line of the first banks, for applying a driving voltage to the word line of the first banks, a nth X-decoder connected to a word line of the nth banks, for applying a driving voltage to the word line of the nth banks, a program/erase pump for generating a program voltage/erase voltage applied to the first to nth banks, a first switch unit that switches the program voltage/erase voltage and transmits the voltage to the first banks and the first X-decoder, and a nth switch unit that switches the program voltage/erase voltage and transmits the voltage to the nth banks and the nth X-decoder.

Abstract: A string of memory cells with a charge trapping structure is read, by selecting part of a memory cell selected by a word line. Part of the memory cell is selected by turning on one of the pass transistors on either side of the string of memory cells. The charge storage state of the selected part is determined by measuring current in a bit line tied to both pass transistors.

Abstract: Methods for minimizing current consumption in a memory array during programming of non-volatile memory cells, such as NROM cells, in the array include: programming a cell without having a direct current flowing from a positive supply to ground through the array, programming a plurality of cells with programming pulses without discharging a global bit line carrying a programming voltage between programming pulses, and programming a cell with transient currents.

Abstract: A flash memory device of SONOS structure and a method for fabricating the same, and programming and erasing operation methods, to improve reliability such as endurance and retention, are disclosed, which includes a first conductive type semiconductor substrate; an ONO layer on the semiconductor substrate; a first control gate on the ONO layer; second and third control gates on the ONO layer at both sides of the first control gate; and source and drain regions in the surface of the semiconductor substrate at both sides of the second and third control gates.

Abstract: The present invention provides a method and apparatus for erasing memory blocks. The apparatus includes a first plurality of memory cells formed in a substrate and a second plurality of memory cells formed in the substrate. The apparatus further includes a bias circuit adapted to provide an erasing voltage differential to the first plurality of memory cells and a compensating voltage differential to the second plurality of memory cells, wherein the erasing voltage differential is larger than the compensating voltage differential.

Abstract: A flash memory system including a flash memory device and a controller, operable according to an advanced data transfer mode is disclosed. The flash memory device is operable both in a “legacy” mode, in which read data is presented by the memory synchronously with each cycle of a read data strobe from the controller, and in which input data is latched by the memory synchronously with each cycle of a write data strobe from the controller. In the advanced mode, which can be initiated by the controller forwarding an initiation command to the memory, the flash memory itself sources the read data strobe, and presents data synchronously with both the falling and rising edges of that read data strobe. In the advanced mode, the input data is presented by the controller synchronously with both edges of the write data strobe. The voltage swing of the data and control signals is reduced from conventional standards, to reduce power consumption.

Abstract: A flash memory system including a flash memory device and a controller, operable according to an advanced data transfer mode is disclosed. The flash memory device is operable both in a “legacy” mode, in which read data is presented by the memory synchronously with each cycle of a read data strobe from the controller, and in which input data is latched by the memory synchronously with each cycle of a write data strobe from the controller. In the advanced mode, which can be initiated by the controller forwarding an initiation command to the memory, the flash memory itself sources the read data strobe at a higher frequency, for example at twice the frequency, of that available in the normal mode. In the advanced mode, the input data is presented by the controller synchronously with a higher frequency write data strobe than is available in the normal mode. The voltage swing of the data and control signals is reduced from conventional standards, to reduce power consumption.