Abstract: A memory device including a simultaneous read circuit design for multiple memory cells on a single interconnect using a fast fourier transform analysis circuit. The simultaneous read circuit can be used with any memory type storing information as an energy-absorbing state.

Abstract: A memory arrangement includes a plurality of switching elements arranged in the form of a binary tree. The memory elements are supplied with data to be stored by the switching elements coupled to the leaves of the binary tree.

Abstract: A multi-ported register cell. The register cell includes a base cell and a plurality of history cells, each of which is coupled to the base cell. Each of the plurality history cells is coupled to write to the base cell through a first port, and each of the plurality of history cells is coupled to receive data from the base cell through a second port.

Abstract: A page buffer for a non-volatile semiconductor memory device includes a switch configured to couple a first bitline coupled to a first memory cell to a second bitline coupled to a second memory cell, a first latch block coupled to the first bitline and configured to transfer a first latch data to the first memory cell, and a second latch block coupled to the second bitline and the first latch block, and configured to transfer a second latch data to the second memory cell.

Abstract: For a nonvolatile memory permitting electrical writing and erasing of information to be stored, such as a flash memory, the load on the system developer is to be reduced, and it is to be made possible to avoid, even if such important data for the system as management and address translation information are damaged, an abnormal state in which the system becomes unable to operate.

Abstract: A ferroelectric memory includes: a memory cell array in which a plurality of memory cells are disposed, a plurality of wordlines, a plurality of platelines, and a plurality of wordline driver circuits, each of the memory cells including a ferroelectric capacitor. A wordline driver circuit circuits includes: a driver DRV which drives a wordline WL; a transfer transistor TRA provided between the driver DRV and the wordline WL; and a gate control circuit. The gate control circuit performs gate control which causes the transfer transistor TRA to be turned on, and performs gate control which causes the transfer transistor TRA to be turned off, before a voltage of the wordline WL is boosted (before a plateline PL is driven) after the transfer transistor TRA has been turned on.

Abstract: A Local Dynamic Power Controller (LDPC) generates and deliver to a load a full swing voltage supply signal and a reduced swing voltage supply signal. Both the full and reduce voltage supply signals are generated from a single power supply. The full swing voltage supply signal is supplied when the load is in full operational mode whereas the reduce voltage supply signal is provided when the load is in a sleep mode. As a consequence, power dissipated in the load is reduced.

Abstract: A semiconductor memory includes: first and second bit lines; a precharge circuit for precharging the first and second bit lines to a predetermined potential; a plurality of memory cells each connected to the first or second bit line, a selected one of the memory cells maintaining or discharging one of the precharged first and second bit lines according to a signal held by the selected memory cell; word lines for selecting the memory cells; first and second reference cells connected to the first and second bit lines, respectively, a selected one of the first and second reference cells discharging the first or second bit line connected to the selected reference cell; and first and second reference cell word lines for selecting the first and second reference cells, respectively.

Abstract: A word line driving circuit may include a first word line driver, a second word line driver and a pass transistor. In response to a word line selecting signal, the first word line driver may drive a word line using a first word line driving voltage signal in a first operation mode or the second word line driver may drive the word line using a second word line driving voltage signal. The pass transistor coupled between the first word line driver and the word line may transmit the first word line driving voltage signal to the word line in response to a control voltage signal, which is self-boosted at an initial stage of the first operation mode and is maintained at a stable voltage level after a time period.

Abstract: A RFID device having a nonvolatile ferroelectric memory regulates bit line capacitance to optimize a bit line sensing margin and minimize power consumption. The RFID device having an analog block adapted and configured to transmit and receive a radio frequency signal to/from an external communication apparatus, a digital block adapted and configured to receive a power voltage and the radio frequency signal from the analog block, transmit a response signal to the analog block and output a memory control signal, and a memory adapted and configured to store data and regulate bit line capacitance.

Abstract: A method of biasing word lines in a flash memory array wherein a selected word line is selected for a reading operation during data access includes the steps of biasing deselected word lines with a deselected word line voltage, delaying for a delay period and after the delay period, biasing the selected word line with a selected word line voltage for performing the reading operation.

Abstract: An input buffer having differential amplifiers for receiving input signals to generate an output signal. The input buffer operates with a relatively low supply voltage and a relatively wide range of input signal levels while improving the symmetry between rising and falling signal transitions of the output signal.

Abstract: A semiconductor device includes an interface which executes an interfacing process with a semiconductor memory, and a circuit which performs control to write serial data to the semiconductor memory while skipping a position of a defective column on the semiconductor memory.

Abstract: A current reduction circuit of a semiconductor device is disclosed which includes an enabling signal generator which outputs a predetermined enabling signal in association with a cell block in which a bridge has been formed between a word line and a bit line, and an isolation controller which is enabled in response to the enabling signal, and outputs a control signal to periodically isolate the bridge-formed cell block from a sense amplifier array for a predetermined period in a standby mode in response to a periodic signal enabled at intervals of a predetermined time.

Abstract: Systems and methods for reducing the latency of data transfers between memory cells by enabling data to be transferred directly between sense amplifiers in the memory system. In one embodiment, a memory system uses a conventional DRAM memory structure having a pair of first-level sense amplifiers, a second-level sense amplifier and control logic for the sense amplifiers. Each of the sense amplifiers is configured to be selectively coupled to a data line. In a direct data transfer mode, the control logic generates control signals that cause the sense amplifiers to transfer data from a first one of the first-level sense amplifiers (a source sense amplifier) to the second-level sense amplifier, and from there to a second one of the first-level sense amplifiers (a destination sense amplifier.) The structure of these sense amplifiers is conventional, and the operation of the system is enabled by modified control logic.

Abstract: A resistive memory device requires a power supply having a reduced number of voltage taps and reduced power consumption. In accordance with one exemplary embodiment, one or more voltages used by a reference circuit which are normally supplied by different taps of a power supply are generated by corresponding power circuits. In accordance with a second exemplary embodiment, the power circuits are coupled to the bit lines and replace the reference circuit in a manner to improve sensing margin.

Abstract: In one embodiment, a sense amplifier includes: a differential amplifier adapted to amplify a voltage difference between a pair of bit lines; and a self-bias generation circuit adapted to reduce an offset bias in the differential amplifier with regard to the amplification of the voltage difference between the pair of bit lines.

Abstract: A dynamic random access memory including a first dynamic random access memory cell, a second dynamic random access memory cell to be refreshed, a sense amplifier, and a control circuit. The control circuit is configured to isolate the sense amplifier from at least one of the first dynamic random access memory cell and the second dynamic random access memory cell in an idle state and to couple the sense amplifier to only the second dynamic random access memory cell to be refreshed in a refresh state.

Abstract: There is provided a bulk bias voltage VBB level detector in a semiconductor memory device capable of improving tWR fail generated at a low temperature by compensating a temperature variance. The VBB level detector includes A bulk bias voltage level detector in a semiconductor memory device, comprising: a voltage divider for generating detection voltage based on an inputted bulk voltage; and a CMOS circuit for generating a output signal having predetermined logic value determined by the detection voltage wherein the voltage divider includes a first transistor having a gate coupled to a ground voltage and a second transistor having a gate coupled to an internal power voltage and a bulk coupled to the inputted bulk voltage.

Abstract: A dual port memory is updated at substantially the same data sampling rate as a clock frequency of the dual port memory. The dual port memory stores data relating to each different parameter value in a stream of data samples, and provides the stored data from an address in the memory corresponding to the received parameter value. An updating element updates stored data and provides the updated data to an input of the dual port memory for writing back into the address corresponding to the received parameter value. A first port of the dual port memory is utilised as the output of the dual port memory coupled to the input of the updating element on a first clock cycle of the dual port memory, and a second port of the dual port memory is normally utilised as the input of the dual port memory coupled to the output of the updating element on a second clock cycle, the next address being accessed via the first port on the second clock cycle.

Abstract: An data output circuit for outputting a data stored in a core of a semiconductor memory device includes a clock generator for generating a rising clock and a falling clock by using an external clock, a clock repeater for outputting the rising clock and the falling clock as one of a high voltage clock and a low voltage clock in response to an external voltage level check signal, a level shifter for outputting a high voltage data generated by shifting the data synchronized with the high voltage clock, a data carrier for outputting a low voltage data synchronized with the low voltage clock, and a data repeater for outputting one of the high voltage data and the low voltage data in response to the external voltage level check signal.

Abstract: Word line driver circuitry for selectively charging and discharging one or more word lines is provided. The driver circuitry uses a dual transistor topology, where a first transistor is driven by a signal, DOUT, and a second transistor is driven by a time-delayed complement of the DOUT, DOUT_BAR. The time delay prevents DOUT_BAR from changing its state immediately after DOUT changes state. As result, both the first and second transistors are turned ON at the same time for a predetermined of time. It is during this time that the voltage on the word line is rapidly driven to a LOW voltage. When the second transistor turns OFF, high impedance circuitry limits the flow of leakage current. This minimizes leakage current when the word line is OFF and when short circuit conditions are present between two or more word lines or between a word line and a bit line.

Abstract: A memory device includes a memory cell array, a row decoding section, a K-bit prefetch section and an output buffer section. The row decoding section decodes a row address in response to a first clock, to activate one of the word lines corresponding to the decoded row address. The K-bit prefetch section decodes a column address in response to a second clock and prefetches K data from K memory cells connected to the activated word line and corresponds to the decoded column address, in response to a second clock, where a frequency of the second clock is 1/M of that of the first clock. The output buffer section outputs the K prefetched data as a data stream in response to a third clock. Therefore, a burden from the physical limit of the access speed may be alleviated when the data I/O speed is increased.

Abstract: A system for processing one or more detection signals from an acoustic signal detection system to image and track one or more contacts within a medium including a computer configured to receive the detection signal and a computer readable medium operatively coupled to the computer, that is capable of applying an image processing method to one or more images derived from the received one or more detection signals to estimate the kinematic characteristics of the one or more contacts.

Abstract: Methods of processing seismic data to remove unwanted noise from meaningful reflection signals are provided for. The methods comprise the steps of assembling seismic data into common geometry gathers in an offset-time domain without correcting the data for normal moveout. The amplitude data are then transformed from the offset-time domain to the time-slowness domain using a Radon transformation. A corrective filter is then applied to enhance the primary reflection signal content of the data and to eliminate unwanted noise events. The corrective filter has a pass region with a lower pass limit and a higher pass limit. The higher pass limit is set within 15% above the slowness of the primary reflection signals and, preferably, it is more closely set to the slowness of the primary reflection signals. The lower pass limit is also preferably set within 15% below the slowness of the primary reflection signals.

Abstract: Seismic sensor systems and sensor station topologies, as well as corresponding cable and sensor station components, manufacturing and deployment techniques are provided. For some embodiments, networks of optical ocean bottom seismic (OBS) stations are provided, in which sensor stations are efficiently deployed in a modular fashion as series of array cable modules deployed along a multi-fiber cable.

Abstract: An embodiment of a method for conducting a bathymetric survey across a seismic spread includes the steps of emitting a signal from a pinger positioned within the seismic spread, measuring the arrival time of a bottom reflection of the signal at a receiver positioned within the seismic spread, measuring the arrival time of a direct arrival of the signal at the receiver, and determining the water depth utilizing the measured arrival times of the signal.

Abstract: An arrangement for signal processing in ultrasonic transducers in flow meters has an ultrasonic transducer acted upon by a drive signal with the ultrasonic transducer being connected to a resonant circuit matched to the frequency of the drive signal. The resonant circuit can be a component of the network which makes switching over the ultrasonic transducer for transmitting operation to a receiving operation possible. An ultrasonic flow meter uses time-of-flight principle for transmitting and receiving ultrasonic signals and signal post-processing of the received ultrasonic signals. To make available an ultrasonic flow meter that produces an improved quality voltage signal for evaluation and at the same time makes possible a reduction of its production costs, a ringing circuit is provided. The ringing circuit may be a series ringing circuit for signal post-processing of the received ultrasonic signals connected to a comparator and using an LC-circuit, a Pi-filter or an RLC-circuit.

Abstract: Gear for day of the month display mechanism in a watch movement, including: a driving organ (1), a driven organ (50), characterized in that said driving organ (1) is provided with z1 first teeth (120) and z2 second teeth (121), the height of the second teeth (121) being lower than the height of the first teeth (120), and in that said driven organ (50) is provided with z3 third teeth (501) and z4 fourth teeth (503), the height of the third teeth (501) being greater than the height of the fourth teeth (503), the height of the z1 first teeth (120) allowing the z3 third teeth (501) as well as the z4 fourth teeth (503) to be driven, the height of the z2 second teeth (121) allowing however only the z3 third teeth (501) but not the z4 fourth teeth (503) to be driven.

Abstract: The invention relates to a display device for a wristwatch comprising a luminescent surface for illuminating the background of a display element consisting of one or more alphanumeric characters. The display device comprises a window in an opaque watch face in which these characters can be displayed. The luminescent surface covers at least one partial area of a supporting surface situated behind said window. The alphanumeric characters of the display element have an opaque material and are located between the watch face and the luminescent surface.

Abstract: A near-field optical head has a main surface confronting a recording medium during use of the near-field optical head. A sharpened tip is disposed on the main surface and has an optical aperture at a front end thereof. An opaque film covers the sharpened tip and has a plastically deformed portion in the vicinity of the optical aperture. The front end of the sharpened tip projects from the plastically deformed portion of the opaque film. At least one stopper is disposed in the vicinity of the sharpened tip and has a height substantially equal to a height of the sharpened tip. At least one air-bearing surface is disposed on the main surface.

Abstract: High speed access to an information recording medium is possible by preparing information relative to a lower level recording unit, e.g., a fragment, which is set smaller than a higher level recording unit, e.g., a session. A fragment identifier, typically, a fragment number is assigned to each fragment, sequentially and in ascending order. A fragment number (greatest fragment number) that is greater than any other fragment number in the session is recorded in the information recording medium for each session. When reproducing a desired fragment, a controller acquires the greatest fragment number of each session sequentially from the first session, and compares the greatest fragment number of the session with the fragment number of the desired fragment. When the greatest fragment number that is equal to or greater than the fragment number of the desired fragment is found, the desired fragment is searched for from the top of the session.

Abstract: The optical head device for carrying recording/reproducing of data by irradiating a recording face of an optical disk with a laser beam, includes a base frame provided with an optical system for guiding the laser beam to the optical disk; and a sub-frame provided with a semiconductor laser for and fixed to the base frame. In this optical head device, a diamond-like carbon (DLC) film is formed on the mating faces of the base frame and the sub-frame, respectively.

Abstract: This invention directs to an optical disc assembly configured to receive an analyte which can be detected by a standard optical disc reader or an optical disc reader modified therefrom. The optical disc assembly may preferably be designed so that the optical disc reader can track the disc and detect the analyte concurrently and discriminably. The optical disc assembly contains or encodes optically readable features which are trackable by the optical disc reader and which have encoded speed information enabling the optical disc reader to rotate the optical disc assembly at a determinable speed. The optical disc assembly also includes an analyte section capable of receiving the analyte that can be detected by the optical disc reader.

Abstract: A disk reproducing apparatus for reproducing a digital audio signal recorded on a DVD or CD has a PLL portion for outputting a synchronizing signal in synchronism with the digital audio signal. When the CD is reproduced at double speed or higher, the PLL portion increases again while seeking tracks, and restores the gain if a predetermined time has passed after the end of seek.

Abstract: An optical disk apparatus and an optical disk recording and reproducing method are provided in which an actuator can be controlled in stable fashion at the time of high-speed recording operation. Before performing the high-speed recording operation under servo control of average type, the learning of a servo signal of average type by application of a disturbance signal is carried out for both the servo control of continuous servo type for reproduction and the servo control of sample-and-hold type for low-speed recording operation. Based on the result of the learning, the gain is set for a servo loop of average servo type for high-speed recording operation.

Abstract: Congested rewriting in the same area is to be evaded to suppress the tendency towards occurrence of defective areas. When a stream 1 has been recorded, the last written address, representing the last written position, is stored. When recording a stream 2 next, recording is started directly following the position indicated by the last written address for the stream 1. The last written address, corresponding to the last address of the recording position, is stored. If the stream 2 is erased for recording a stream 3, recording is started not at a position directly following the last written address of the stream 1, but from a position directly following the last written address of the stream 2. When the stream 3 has reached the end of a recording area, the next following data is recorded as from a position directly following the stream 1.

Abstract: A combined signal Spc in which a pre-pit signal is superposed on a wobble signal is generated based on a radial push-pull signal Spp with a noise component having been removed therefrom. Based on the combined signal Spc, a wobble signal SWB with the phase ?0 not having time fluctuation and a pre-pit signal SPD are generated with the phases compared to each other, and then a phase adjustment signal SCNT corresponding to a phase difference ?e is generated. The phase differences ?e are stored, and an average value ?r thereof generated, the phase difference ?e is compared to the average value ?r, the phase ?0 is shifted according to only by the phase difference ?e only when the phase difference ?e is within the range of (?r±W), and then a wobble signal SWB with the phase ?1 synchronized to the pre-pit signal SPD is generated.

Abstract: A write once disc allowing management of a data area, a method of managing the data area of the write once disc, an apparatus recording data on the write once disc, an apparatus and method of reproducing data from a write once disc. The write once disc, includes a lead-in zone, a data area, and a lead-out zone. The write once disc includes a predetermined area storing area allocation information which indicates whether at least one section of the data area is allocated for disc defect management. In the disc and method, area allocation information specifying a structure of the data area is recorded on the disc, thus allowing a recording/reproducing apparatus to recognize the data area structure. Therefore, allocating areas, such as a spare area, for disc defect management other than an area for storing user data, to the data area is possible. The allocation of the areas for disc defect management to the data area enables effective use of the write once disc.

Abstract: An auto-adjusting system for an optical incident angle comprises a memory, a linear tilt calculation unit, a non-linear tilt calculation unit, a controller, and a tilt actuator. The memory is used for storing a linear tilt compensation table and a non-linear tilt compensation table. The linear tilt calculation unit is used for calculating the corresponding linear tilt dac value by consulting the linear tilt compensation table according to a first radius and a focus output voltage. According to a predetermined comparison procedure, the non-linear tilt calculation unit is used for generating a second radius wherein the compact disc begins to generate non-linear deformation and then obtaining the corresponding non-linear tilt compensation parameter by consulting the non-linear tilt compensation table according to the first radius and the second radius. The controller is used for controlling the pickup head, the memory, the linear tilt calculation unit, and the non-linear tilt calculation unit.

Abstract: According to one embodiment, a storage medium includes a burst cutting area at an inner periphery, wherein the burst cutting area has includes plural burst-cutting-area data areas.

Abstract: The present invention provides a DSV normal controller and a DSV special controller. In only a predetermined region designated on an optical disc, the DSV special control is performed. The DSV special control causes the absolute value of the DSV to increase so that data will be prevented from being normally reproduced. The normal control causes the absolute value of the DSV to converge at 0. When data is reproduced from the optical disc, if the reproduction state of the predetermined region is abnormal, it is determined that the disc is an original disc. An encryption key can be recorded in the predetermined region.

Abstract: In an optical head for performing the reproduction or recording of information for two or more types of different optical disks, the damage caused to an optical disk or an objective lens by collision between the optical disk and the objective lens is avoided. An optical heads device for reproducing or recording two or more types of information recording mediums different from each other comprises a first optical system, a second optical system, and a control unit for avoiding the collision between an optical disk and a second objective lens when a first optical system is in operation.

Abstract: An information recording apparatus is provided with: a recording device for recording information into recording areas of an information recording medium by irradiating laser light; a reference-output-value holding device for holding a reference-output-value of the laser light for recording the information into the recording areas; an estimating device for estimating an output value of the laser light which was irradiated in the past in an already-recorded-area in which the information is already recorded; and a controlling device for controlling said recording device to irradiate the laser light onto the already-recorded-area with an output value larger than the reference output value if the estimated output value is larger than the reference output value.

Abstract: The invention relates to methods and devices for forming marks and lands by applying a radiation beam (32) to a recording surface (301) of an optical record carrier (30). Recording strategies are proposed for recording information at high recording speeds. An intermediate power level (P1, P2) is introduced in between the bottom power level (P0) and the write power level (Pw), its value being dependent on the length of the preceding land (151, 152, 153). A raised write power level (PR1, PR2) is also proposed, its value being dependent on the length of the mark to be recorded (241, 242, 243).

Abstract: An optical recording medium has a phase-change recording layer containing Sb and Te as essential elements therefor, to which is added at least one element selected from the group consisting of Ag, Au, Cu, Zn, B, Al, Ga, In, Si, Ge, Sn, Pb, N, P, Bi, La, Ce, Gd, and Tb, the recording layer being capable of assuming an amorphous phase changed from a crystalline phase by the application of a laser beam thereto, thereby optically recording information. Recording marks are formed in the recording medium by converting a light emission wave of laser beam into a recording pulse train comprising a plurality of on-pulses and off-pulses, with a recording frequency being continuously changed corresponding to the location of each of the recording marks in the radial direction of said recording medium. A recording apparatus has laser beam driving circuit means, signal generation means, and signal transmission means for achieving the above recording method.

Abstract: A signal can be detected based on a level slice system and detection delay time can be reduced by setting the recording density of a header field in a linear direction lower (coarse) than that of a user data recording field. Further, a signal can be detected based on the level slice system and detection delay time can be reduced by using a mark position form having a large detection margin as an information recording system of the header field. A readout error of a sector number due to a detection error is compensated for by recording address marks AM for attaining byte synchronization of the header field in both of a head portion and tail portion of information recorded in the header field.

Abstract: A high-density optical recording medium and method of recording data on the optical recording medium. The optical recording medium includes a plurality of data recording/reproducing surfaces having reflectances for light passing through a pit area, a land/groove area, and a land/groove area on which data are recorded, of a data recording/reproducing surface included between a light source for emitting light and a recording/reproducing surface selected from the plurality of data recording/reproducing surfaces, the reflectances satisfy the expressions r1?r2?r3 and {(r1?r3)/r1}?0.2, where r1, r2 and r3 are the reflectances of the pit area, the land/groove area and the land groove area on which data are recorded, respectively.

Abstract: An optical pickup apparatus for reproducing information from an optical information recording medium or for recording information onto an optical information recording medium, is provided with a first light source for emitting first light flux having a first wavelength; a second light source for emitting second light flux having a second wavelength, the first wavelength being different from the second wavelength; a converging optical system having an optical axis and a diffractive portion, and a photo detector; wherein in case that the first light flux passes through the diffractive portion to generate at least one diffracted ray, an amount of n-th ordered diffracted ray of the first light flux is greater than that of any other ordered diffracted ray of the first light flux, and in case that the second light flux passes through the diffractive portion to generate at least one diffracted ray, an amount of n-th ordered diffracted ray of the second light flux is greater than that of any other ordered diffracted

Abstract: An optical pickup device includes a light source unit an optical system which leads a return light beam to a predetermined light-receiving location and includes an object lens focusing each light beam from the light source unit to a recording surface of a corresponding storage medium and a photodetector arranged at the light-receiving location. The light source unit includes a plurality of light sources outputting light beams respectively, the plurality of light sources being arranged in proximity to each other, and a divergence-angle changing unit changing an angle of divergence of a light beam output from at least one of the plurality of light sources.