Abstract: Disclosed is a composition, an organic insulating film including the same, an organic thin film transistor including the organic insulating film, an electronic device including the organic thin film transistor and methods of fabricating the same. In the composition, an organic polymer material having a carboxyl group and an organic silane material having an electron-donating group are included to thus realize a structure which may further stabilize an unreacted crosslinking material. Thereby, a hysteresis phenomenon may be decreased and transparency may be increased, thus making it possible to assure stability upon exposure to air. Accordingly, the lifetime of the organic thin film transistor may be lengthened.

Abstract: Disclosed is a composition for preparing an organic insulator, including an organic silane material, having a vinyl group, an acetylene group or an acryl group as a functional group for participating in a crosslinking reaction, a crosslinking agent, and a solvent for dissolving the above components. The organic insulator of example embodiments may be provided in the form of a solid insulating film, which may increase charge mobility while decreasing the threshold voltage and operating voltage of OTFTs, and which also may generate relatively slight hysteresis.

Abstract: An electro-optic device manufacturing method comprises providing a first partition on a substrate in a form of a pattern; depositing a metal material onto the substrate, forming a pixel electrode and a signal line on a top surface of the first partition, and forming a gate wire in an area surrounded by the first partition; after depositing, forming a second partition that partitions at least the a gate insulator formation area and a semiconductor layer formation area of which a section overlaps with the gate insulator formation area on the substrate; discharging functional liquid including a formation material for forming an insulator layer in the gate insulator formation area and forming a gate insulator; and after forming the gate insulator, discharging a functional liquid including a formation material for forming an organic semiconductor layer onto the semiconductor formation area and forming an organic semiconductor layer that crosses over the gate electrode and a section of the gate insulator and electr

Abstract: An organic thin film transistor (OTFT) includes an organic semiconductor layer on a substrate, source/drain electrodes spaced apart from each other on the substrate, a mixed layer between the source/drain electrodes and the organic semiconductor layer, the mixed layer including an organic material and a metal oxide or metal salt, and a gate electrode.

Abstract: A thin film transistor array substrate and a fabricating method thereof are disclosed. First, a substrate is provided. A patterned transparent conductive layer is then formed on the substrate. Next, a patterned first metal layer is formed to form a plurality of scan lines and a plurality of gates. Thereafter, a gate insulation layer is formed over the substrate. Moreover, a patterned semiconductor layer is formed to form a channel layer above the gates. The semiconductor layer is patterned with the same mask as that for patterning the transparent conductive layer. Additionally, a patterned second metal layer is formed to form a plurality of data lines, a plurality of sources, and a plurality of drains. After that, a dielectric layer is formed over the substrate. Finally, pixel electrodes are formed on the dielectric layer.

Abstract: A thin film transistor includes a substrate; a semiconductor layer disposed on the substrate, and including polycrystalline silicon having a constant directivity and a uniformly distributed crystal grain boundary; a gate insulating layer; a gate electrode; an interlayer insulating layer; and source and drain electrodes.

Abstract: To provide TFT of improved low-temperature polycrystalline layer that has higher electron mobility and assures less fluctuation in manufacture in view of realizing a liquid-crystal display device having a large display area by utilizing a glass substrate. A TFT having higher electron mobility can be realized within the predetermined range of characteristic fluctuation by utilizing the semiconductor thin-film (called quasi single crystal thin-film) formed of poly-crystal grain joined with the {111} twin-boundary of Diamond structure as the channel region (namely, active region) of TFT.

Abstract: An organic light emitting diode display device (OLED display device) having uniform electrical characteristics and a method of manufacturing the same.

Abstract: A thin film transistor liquid crystal display (TFT-LCD) pixel unit and a method for manufacturing the same. The pixel unit comprises a gate line and a gate electrode formed on a substrate and a first gate insulating layer, an active layer, and a doped layer sequentially that are formed on the gate line and the gate electrode. An intercepting trench is formed on the gate line to cut off the doped layer and the active layer on the gate line. A second insulating layer covers the intercepting trench and the substrate where the gate line and the gate electrode are not formed. A pixel electrode is formed on the second insulating layer and is integrated with the second source/drain electrode.

Abstract: An exemplary thin film transistor substrate (30) includes a bas substrate (31) and a gate electrode (32) formed on the bas substrate. The gate electrode includes a bonding layer (321) formed on the bas substrate and an electrically conductive layer (322) formed on the bonding layer. The bonding layer includes one of aluminum oxide and zirconium dioxide.

Abstract: A pixel structure is disclosed. The pixel structure includes a substrate, a first data line having at least one end formed on the substrate, a first insulation layer overlying the first data line and exposing a part of the end of the first data line, a shielding electrode disposed on the first insulation layer and overlapped with the first data line, a second data line formed on the first insulation layer and electrically connected to the exposed end of the first data line, a second insulation layer overlying the shielding electrode and the second data line, and a pixel electrode formed on the second insulation layer and overlapped with the shielding electrode. The invention also provides a method for fabricating the pixel structure.

Abstract: Provided is a vertical light emitting device having improved light extraction efficiency and a method of manufacturing the same. The vertical light emitting device may include a p type electrode, a p type semiconductor layer, an active layer, and an n type semiconductor layer which may be sequentially formed on the p type electrode, and an n type electrode on a portion of a surface of the n type semiconductor layer, wherein the portion of the surface of the n type semiconductor layer may be at an inclined plane inclined from an area near a circumference of the n type electrode towards the active layer. The p type electrode may include a current blocking layer which is made of an insulating material and on the p type electrode directly under the n type electrode. Accordingly, a voltage increase may be minimized or reduced, and light extraction efficiency may be improved.

Abstract: A light-emitting diode comprises: a coupling base; a plurality of light-emitting chips; and a sealant, wherein a plurality of frame pairs having an amount corresponding to that of the light-emitting chips are mounted inside the coupling base. The frame pairs have a plurality of first and second frames having different areas. The light-emitting chips are respectively coupled with a plurality of large-area coupling parts of the first frames, and the light-emitting chips are electrically connected with the second frames, respectively. The coupling base is packaged by the sealant. Accordingly, the volume of the light-emitting diode can be reduced significantly.

Abstract: An LED assembly comprises an LED and a lens disposed adjacent to a light emitting surface of the LED. The area of cross-section of the lens projected onto the light emitting surface of the LED is substantially equal to or less than the area of the LED's light emitting surface. The light emitting device can comprise an array of LEDs and an array of lenses, in which at least one lens is associated with each member of the LED array and wherein the area of a cross-section of each lens projected onto the light emitting surface of its associated LED is substantially equal to or less than the area of the LED's light emitting surface.

Abstract: A semiconductor light emitting device capable of precisely detecting a cleavage position is provided. A second light emitting device is layered on a first light emitting device. The second light emitting device has stripe-shaped opposed electrodes that are respectively arranged oppositely to respective p-side electrodes of the first light emitting device and electrically connected to the p-side electrodes of the first light emitting device, connection pads respectively and electrically connected to the respective opposed electrodes, a connection pad electrically connected to a p-side electrode, and marks arranged with one end in the plain face of cleavage face S3 or cleavage face S4 on an insulating layer formed on the side of a second substrate facing to a first substrate.

Abstract: A light-emitting module includes a semiconductor light-emitting element with a generally oblong shape, and a planar electrode formed on a surface of the semiconductor light-emitting element. The planar electrode has a generally right triangular electrode portion that is defined by an oblique cut-off line on any one of four corners of the semiconductor light-emitting element. The planar electrode is formed with a wire bonding portion that establishes a current-carrying connection with the generally right triangular electrode portion.

Abstract: The present invention allows the growth of InGaN with greater compositions of Indium than traditionally available now, which pushes LED and LD wavelengths into the yellow and red portions of the color spectrum. The ability to grow with Indium at higher temperatures leads to a higher quality AlInGaN. This also allows for novel polarization-based band structure designs to create more efficient devices. Additionally, it allows the fabrication of p-GaN layers with increased conductivity, which improves device performance.

Abstract: The present invention relates to a white light emitting diode device, which comprises a light emitting diode device; a base case, which is provided with a fillister for placing the LED and a rabbet; and a covering element, which is installed over the fillister and fixed on the rabbet and consists of two transparent sheets; wherein a light-pervious binding agent containing phosphors is sandwiched between the two transparent sheets, thereby phosphors contained in the binding agent is excited by the light source emitted from the light emitting diode and generates white light emitted from the device.

Abstract: An (Al, Ga, In)N light emitting diode (LED) in which multi-directional light can be extracted from one or more surfaces of the LED before entering a shaped optical element and subsequently being extracted to air. In particular, the (Al, Ga, In)N and transparent contact layers (such as ITO or ZnO) are embedded in or combined with a shaped optical element comprising an epoxy, glass, silicon or other material molded into an inverted cone shape, wherein most of the light entering the inverted cone shape lies within a critical angle and is extracted. In addition, the present invention stands the LED on end, i.e., rotates the position of the LED within the shaped optical element by approximately 90° as compared to a conventional LED, in order to extract light more effectively from the LED.

Abstract: A New Phosphor-converted LED Device (“NPCLD”) is disclosed. The NPCLD may include a lens over a phosphor body, in which the lens and the phosphor body each have a substantially convex upper surface. The NPCLD may alternatively include first and second lenses, the first lens having a substantially flat interface with a phosphor body.

Abstract: An LED package which employs a high temperature plastic or polymeric material which is compatible with widely used gold-tin eutectic solder and which can replace the higher cost ceramic used in conventional LED packages. The novel LED package has a high thermal conductivity substrate, a high reflectivity for visible light and/or UV light, and good aging properties. The high temperature material is a high temperature liquid crystal polymer (LCP) having a melting temperature greater than about 340° C. and has small filler particles near the surface, the particles having a refractive index greater than about 2.0, and a size range of about 0.2 to 0.3 microns. For an LED package which is reflective to UV light, a UV stabilizer can be included in the plastic material to improve reflectivity in the ultraviolet spectrum and to protect from UV degradation of the plastic material which can be caused by UV light emitted by some LEDs.

Abstract: AN LED chip package body provides an LED chip with a pad-installed surface, a plurality of pads disposed on the pad-installed surface and a rear surface formed opposite the pad-installed surface. The LED chip package body further has a light-reflecting coating disposed on the pad-installed surface of the LED chip and a plurality of pad-exposed holes for exposure of the corresponding pads of the LED chip. The LED chip package body further comprises a light-transparent element disposed on the rear surface of the LED chip and a plurality of conductive projecting blocks. Each of the conductive projecting blocks is disposed on the corresponding pad of the LED chip.

Abstract: The present invention is a through-hole LED light source with capability of emitting a beam angle of less than 75 degrees. The light source presents a three-dimensional lead frame with a well, into which at least one LED is mounted, and an optical housing which serves as a directional lens. Through adjustment of the housing and lead well properties, beam angle is adjusted to any angle. The frame is three-dimensional, preferably cylindrical, with both inner and outer portions, electrically isolated. The inner portion serves as the mounting area for the LEDs (and contains the well) and the LED serves as the electrical conduit between the portions, completing a circuit an illuminating the LED.

Abstract: A power module includes a power semiconductor, a non-power semiconductor, one resin substrate and a cooling device. The power semiconductor and the non-power semiconductor configure a power supply circuit for performing power conversion. Both the power semiconductor and the non-power semiconductor are mounted on the resin substrate. The cooling device is disposed in order to cool the power semiconductor.

Abstract: A method of making a two-dimensional detector array (and of such an array) comprising, for each of a plurality of rows and a plurality of columns of individual detectors, forming an n-doped semiconductor photo absorbing layer, forming a barrier layer comprising one or more of AlSb, AlAsSb, AlGaAsSb, AlPSb, AlGaPSb, and HgZnTe, and forming an n-doped semiconductor contact area.

Abstract: An electronic device can include a first transistor having a first channel region further including a heterojunction region that, in one aspect, is at most approximately 5 nm thick. In another aspect, the first transistor can include a p-channel transistor including a gate electrode having a work function mismatched with the associated channel region, and the heterojunction region can lie along a surface of a semiconductor layer closer to a substrate than an opposing surface of the substrate. The electronic device can also include an n-channel transistor, and the subthreshold carrier depth of the p-channel and n-channel transistors can have approximately a same value as compared to each other. A process of forming the electronic device can include forming a compound semiconductor layer having an energy band gap greater than approximately 1.2 eV.

Abstract: The present invention provides an integrated semiconductor device that includes a semiconductor substrate, a first device containing a heterojunction bipolar transistor (HBT) located in a first region of the semiconductor substrate, wherein the HBT includes a base region containing a first portion of a SiGe or SiGeC layer, and a second device located in a second region of the semiconductor substrate, wherein the second device includes an interconnect containing a second portion of the SiGe or SiGeC layer. In a specific embodiment of the present invention, the second device is a memory device including a trench capacitor and a field effect transistor (FET) that are electrically connected together by the second portion of the SiGe or SiGeC layer. Alternatively, the second device is a trench-biased PNPN silicon controlled rectifier (SCR). The present invention also provides a novel reversibly programmable device or a novel memory device formed by a novel trench-biased SCR device.

Abstract: An electronic device includes an n-channel transistor and a p-channel transistor. The p-channel transistor has a first gate electrode with a first work function and a first channel region including a semiconductor layer immediately adjacent to a semiconductor substrate. In one embodiment, the first work function is less than the valence band of the semiconductor layer. In another embodiment, the n-channel transistor has a second gate electrode with a second work function different from the first work function and closer to a conduction band than a valence band of a second channel region. A process of forming the electronic device includes forming first and second gate electrodes having first and second work functions, respectively. First and second channel regions having a same minority carrier type are associated with the first and second gate electrodes, respectively.

Abstract: Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a layer which is doped with impurities in order to provide a preselected workfunction. It is further disclosed how this, and further improvements for FET devices, such as raised source/drain and multifaceted gate on insulator, MODFET on insulator are integrated with strained Si based layer on insulator technology.

Abstract: In a method of forming a semiconductor device on a semiconductor substrate (100), a photoresist layer (102) is deposited on the semiconductor substrate; a window (106) is formed in the photoresist layer (102) by electron beam lithography; a conformal layer (108) is deposited on the photoresist layer (102) and in the window (106); and substantially all of the conformal layer (108) is selectively removed from the photoresist layer (102) and a bottom portion of the window to form dielectric sidewalls (110) in the window (106).

Abstract: An integrated circuit has a power rail formed of a first wire in a lower metal layer and a second wire in an upper metal layer and that run in the same direction in their respective layers. A number of vias connect the first and second wires, to form a sandwich power rail structure. Other embodiments are also described and claimed.

Abstract: An interconnect layout, an image sensor including the interconnect layout and a method for fabricating the image sensor each use a first electrically active physical interconnect layout pattern within an active pixel region and a second electrically active physical interconnect layout pattern spatially different than the first electrically active physical interconnect layout pattern within a dark pixel region. The second electrically active physical interconnect layout pattern includes at least one electrically active interconnect layer interposed between a light shield layer and a photosensor region aligned therebeneath, thus generally providing a higher wiring density. The higher wiring density within the second layout pattern provides that that the image sensor may be fabricated with enhanced manufacturing efficiency and a reduction of metallization levels.

Abstract: A semiconductor device is described, including a substrate, a transistor, a hard mask layer and an anti-reflection layer. The substrate includes a first area and a second area, wherein the second area includes a photosensing area. The transistor is disposed on the substrate in the first area and the hard mask layer over the substrate in the second area. The anti-reflection layer is disposed between the hard mask layer and the substrate.

Abstract: A protective structure for a semiconductor sensor integrated in a semiconductor substrate for use in a state that is in direct contact with a measuring medium has a semiconducting layer that is applied to the semiconductor substrate, a metal layer and an insulating layer. The insulating layer is disposed between the semiconducting layer and the metal layer and electrically insulates same.

Abstract: The present invention provides structures and methods for providing facets with different crystallographic orientations than what a semiconductor substrate normally provides. By masking a portion of a semiconductor surface and exposing the rest to an anisotripic etch process that preferentially etches a set of crystallographic planes faster than others, new facets with different surface orientations than the substrate orientation are formed on the semiconductor substrate. Alternatively, selective epitaxy may be utilized to generate new facets. The facets thus formed are joined to form a lambda shaped profile in a cross-section. The electrical properties of the new facets, specifically, the enhanced carrier mobility, are utilized to enhance the performance of transistors. In a transistor with a channel on the facets that are joined to form a lambda shaped profile, the current flows in the direction of the ridge joining the facets avoiding any inflection in the direction of the current.

Abstract: A field effect transistor with a fin structure having a first and a second source/drain region; a body region formed within the fin structure and between the first and the second source/drain region; a metallically conductive region formed within a part of the first source/drain region, the metallically conductive region being adjacent to the body region or to a lightly doped region disposed between the body region and the first source/drain region; and a current ballasting region formed within a part of the second source/drain region.

Abstract: An integrated circuit device having vias having good resistance to migration causing the breaking of a wiring line, or an integrated circuit device having a wiring structure that is fined by breaking the limit of lithography technique is provided. The former device comprises a plurality of elements fabricated on a semiconductor substrate, wiring lines for making the elements and the integrated circuit device function, and vias for interconnecting wiring lines in separate layers, the via being formed of one or more cylindrical structures made up of carbon atoms. The latter device comprises a plurality of elements fabricated on a semiconductor substrate and wiring members for making the elements and the integrated circuit device function, at least part of the wiring members being formed of one or more cylindrical structures made up of carbon atoms.

Abstract: A transfer transistor of a CMOS image sensor is described, including a substrate of a first type, a gate dielectric layer on the substrate, a gate on the gate dielectric layer, a first doped region of the first type, a buried channel region of the first or second type, a second doped region of the first type, and source/drain regions of the second type. The first doped region is in the substrate directly under the gate dielectric layer under the gate, the buried channel region is in the substrate under the first doped region, and the second doped region is in the substrate under the buried channel region. The source/drain regions are in the substrate beside the gate.

Abstract: A method for forming semiconductor devices is provided. A gate stack is formed over a surface of a substrate. A plurality of cycles for forming polymer spacers on sides of the gate stack is provided, where each cycle comprises providing a deposition phase that deposits material on the sides of the polymer spacer and over the surface of the substrate, and providing a cleaning phase that removes polymer over the surface of the substrate and shapes a profile of the deposited material. Dopant is implanted into the substrate using the polymer spacers as a dopant mask. The polymer spacers are removed.

Abstract: Disclosed herein is a method for manufacturing a semiconductor device, the method including the step of forming a gate electrode that contains a metal over a semiconductor substrate with intermediary of a gate insulating film, the step including the sub-steps of, forming a first gate electrode layer that defines a work function of the gate electrode on the gate insulating film, forming a second gate electrode layer that has a barrier property for underlayers on the first gate electrode layer, and forming a third gate electrode layer of which resistance is lower than a resistance of the first gate electrode layer on the second gate electrode layer by chemical vapor deposition.

Abstract: An improved coupling stability between the source region and the source electrode of the transistor is achieved. In the method for manufacturing the MOSFET, the p-type base region is formed in a semiconductor layer, and after the p-type base region is formed in the surface portion of the n+ type source region, the higher concentration source region extending from the side edge of the n+ type source region to the lateral side of the n+ type source region is formed in the surface portion of the p-type base region. Then, the source electrode coupled to the higher concentration source region is formed. This allows providing an improved coupling stability between the source electrode and the source region when a misalignment is occurred in the location for forming the source electrode during the formation of the source electrode to be coupled to the first source region.

Abstract: A pixel comprises a substrate comprising a first well region formed in a top portion of the substrate, having a first conductivity type. A plurality of shallow trench isolation (STI) structures is formed in the first well region of the substrate, defining a pixel region over the substrate. A second well region is formed in a potion of the first well region of the pixel region, having a second conductivity type opposite to the first conductivity type. A top surface region is formed in a top portion of the second well region, having the first conductivity type. A MOS transistor formed on portions the pixel region, having a pair of source/drain regions formed in the first well region, wherein the source/drain regions are formed of the second conductivity type and one thereof electrically connects the first and well doping regions and the first well region is formed with a depth greater than that of the adjacent STI structure.

Abstract: Provided are an image sensor and a method of sensing the same. The image sensor includes: a light receiving device; a signal conversion unit including a transfer transistor having a plurality of transfer gates and for converting photocharges generated by the light receiving device into a voltage to output the voltage; and a sensing control unit for generating at least two reset signals and/or at least two transfer signals applied to the transfer gates of the transfer transistor during a one-time photosensing cycle. The image sensor is obtained by changing the structure and driving method of a transfer transistor of a typical 4-transistor CMOS image sensor and employs a deep depletion operation and a multiple reset operation, thereby reducing an image lag and increasing the well capacity of the light receiving device.

Abstract: In a node structure under a capacitor in a ferroelectric random access memory device and a method of forming the same, top surfaces of the node structures are disposed at substantially the same level as a top surface of an interlayer insulating layer surrounding the node structures, and thus crystal growth of a ferroelectric in the capacitor can be stabilized. To this end, a node insulating pattern is formed on a semiconductor substrate. A node defining pattern surrounding the node insulating pattern is disposed under the node insulating pattern. A node conductive pattern is disposed between the node defining pattern and the node insulating pattern.

Abstract: The present invention provides a method for manufacturing a semiconductor device, including the steps of: forming a first ferroelectric film on a first conductive film by a film-forming method including at least a step of forming a film by a sol-gel method; forming a second ferroelectric film on the first ferroelectric film by a sputtering method; forming a second conductive film on the second ferroelectric film; and forming a capacitor provided with a lower electrode, a capacitor dielectric film and an upper electrode by patterning the first conductive film, the first and second ferroelectric films and the second conductive film.

Abstract: A ferroelectric capacitor is formed over a semiconductor substrate (10), and thereafter, interlayer insulating films (48, 50, 52) covering the ferroelectric capacitor are formed. Next, a contact hole (54) reaching a top electrode (40) is formed in the interlayer insulating films (48, 50, 52). Next, a wiring (58) electrically connected to the top electrode (40) through the contact hole (54) is formed on the interlayer insulating films (48, 50, 52). At the time of forming the top electrode (40), conductive oxide films (40a, 40b) are formed, and then a cap film (40c) composed of a noble metal exhibiting less catalytic action than Pt and having a thickness of 150 nm or less is formed on the conductive oxide films (40a, 40b).

Abstract: A memory device comprises an array of memory cells, the memory cells being at least partially formed in a semiconductor substrate having a surface, each of the memory cells including an access transistor and a storage capacitor for storing data, the storage capacitor including a first and a second capacitor electrodes and a capacitor dielectric disposed between the first and second capacitor electrodes. The first capacitor electrode extends to a first electrode height. The memory device also includes a peripheral portion including peripheral circuitry and a wiring layer. The wiring layer includes first lines, wherein a bottom surface of each of the first lines is disposed at a bottom surface height which is greater than 0.25 times the first electrode height, and each of the first lines has a line thickness less than 200 nm.

Abstract: A method of forming a vertical DRAM device. A lower trench is filled with polycrystalline or amorphous semiconductor for a capacitor. An upper trench portion has exposed sidewalls of single-crystal semiconductor. The method then includes etching the single-crystal semiconductor sidewalls to widen the of the upper trench portion beyond the exposed upper surface of the semiconductor fill of the capacitor to form exposed regions of single-crystal semiconductor on a bottom portion of the upper trench adjacent to the exposed upper surface of the semiconductor fill. A trench top insulating layer is deposited on the bottom portion of the upper trench, over the upper surface of the semiconductor fill and over the adjacent regions of single-crystal semiconductor. The method then includes forming a vertical gate dielectric layer, wherein the trench top insulating layer extends below the vertical gate insulating layer.

Abstract: Disclosed are embodiments of a transistor that operates as a capacitor and an associated method of tuning capacitance within such a capacitor. The embodiments of the capacitor comprise a field effect transistor with front and back gates above and below a semiconductor layer, respectively. The capacitance value exhibited by the capacitor can be selectively varied between two different values by changing the voltage condition in a source/drain region of the transistor, e.g., using a switch or resistor between the source/drain region and a voltage supply. Alternatively, the capacitance value exhibited by the capacitor can be selectively varied between multiple different values by changing voltage conditions in one or more of multiple channel regions that are flanked by multiple source/drain regions within the transistor. The capacitor will exhibit different capacitance values depending upon the conductivity in each of the channel regions.

Abstract: A non-volatile electrically erasable programmable read only memory (EEPROM) capable of storing two bit of information having a non-conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the two bit EEPROM device. The non-conducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. A left and a right bit are stored in physically different areas of the charge trapping layer, near left and right regions of the memory cell, respectively. Each bit of the memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and to either the left or the right region while the other region is grounded.