Abstract: It is made possible to provide a memory device that can be made very small in size and have a high capacity while being able to effectively suppress short-channel effects. A nonvolatile semiconductor memory device includes: a first insulating film formed on a semiconductor substrate; a semiconductor layer formed above the semiconductor substrate so that the first insulating film is interposed between the semiconductor layer and the semiconductor substrate; a NAND cell having a plurality of memory cell transistors connected in series, each of the memory cell transistors having a gate insulating film formed on the semiconductor layer, a floating gate formed on the gate insulating film, a second insulating film formed on the floating gate, and a control gate formed on the second insulating film; a source region having an impurity diffusion layer formed in one side of the NAND cell; and a drain region having a metal electrode formed in the other side of the NAND cell.

Abstract: A semiconductor device comprises a first transistor having a composite gate structure containing a lamination of a first polycrystalline silicon film, an interlayer insulating film, and a second polycrystalline silicon film; and a second transistor having a single gate structure containing a lamination of a third polycrystalline silicon film and a fourth polycrystalline silicon film, wherein the first polycrystalline silicon film and the third polycrystalline silicon film have substantially the same thickness; the first polycrystalline silicon film and the third polycrystalline silicon film have different impurity concentrations controlled independently of each other; the second polycrystalline silicon film and the fourth polycrystalline silicon film have substantially the same thickness, and the second polycrystalline silicon film, the fourth polycrystalline silicon film, and the third polycrystalline silicon film have substantially the same impurity concentration.

Abstract: In a flash memory device, which can maintain an enhanced electric field between a control gate and a storage node (floating gate) and has a reduced cell size, and a method of manufacturing the flash memory device, the flash memory device includes a semiconductor substrate having a pair of drain regions and a source region formed between the pair of drain regions, a pair of spacer-shaped control gates each formed on the semiconductor substrate between the source region and each of the drain regions, and a storage node formed in a region between the control gate and the semiconductor substrate. A bottom surface of each of the control gates includes a first region that overlaps with the semiconductor substrate and a second region that overlaps with the storage node. The pair of spacer-shaped control gates are substantially symmetrical with each other about the source region.

Abstract: A nonvolatile memory (NVM) device includes a floating gate on a semiconductor substrate and a gate insulating layer between the semiconductor substrate and the floating gate. A tunnel insulating layer is disposed between the semiconductor substrate and the floating gate. The tunnel insulating layer is thinner than the gate insulating layer. A first inter-gate insulating layer is disposed on the floating gate, and a sensing gate is disposed on the first inter-gate insulating layer. The sensing gate covers a first portion of the floating gate. A control gate is disposed to cover a top surface and a sidewall of a second portion of the floating gate. A second inter-gate insulating layer is disposed between the control gate and the sensing gate and between the control gate and the floating gate. Operation methods and fabrication methods of the NVM device are also provided.

Abstract: A buried contact etch stop layer (CESL) is disposed between adjacent diffusions in a semiconductor device, such as between bitlines in a memory array. The CESL may be self-aligned to the diffusions, and may prevent misaligned bitline (BL) contacts from contacting silicon outside of the corresponding bitlines. The bitline contacts may have sufficient overlap of the bitlines to ensure full coverage by the bitlines. STI trenches may optionally be formed under the CESL. The CESL may comprise nitride or any other material that is harder (more resistant) to etch than the material on top of it.

Abstract: A flash memory device and a method of manufacturing the same comprises source and drain diffusion regions formed at fixed intervals in an active area of a silicon semiconductor substrate, charge storage layers of multi-layers formed on the substrate, and a control gate formed on the charge storage layers, wherein the charge storage layers include a tunnel oxide film formed on the silicon semiconductor substrate, and a silicon nitride film formed on the tunnel oxide film, and the silicon nitride film includes a plurality of minute crystals formed by ion-implanting 14-group elements into the silicon nitride film. The flash memory device maintains the good programming and erasing operation of SONOS devices, and also improves trap density and memory window. Because of the difference of energy barrier between the minute crystal and the silicon nitride, the electrons or holes trapped in the minute crystal as the deep trap are not easily detrapped therefrom, thereby improving the data storage property of the device.

Abstract: A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.

Abstract: In one embodiment, there is an asymmetric multi-gated transistor that has a semiconductor fin with a non-uniform doping profile. A first portion of the fin has a higher doping concentration while a second portion of the fin has a lower doping concentration. In another embodiment, there is an asymmetric multi-gated transistor with gate dielectrics formed on the semiconductor fin that vary in thickness. This asymmetric multi-gated transistor has a thin gate dielectric formed on a first side portion of the semiconductor fin and a thick gate dielectric formed on a second side portion of the fin.

Abstract: A transistor structure comprising a single-crystal gate conductor disposed on a single-phase high-K dielectric gate dielectric is disclosed. The transistor structure is particularly suitable for fully-depleted silicon-on-insulator electronics.

Abstract: This disclosure concerns a semiconductor memory device comprising a semiconductor substrate; a buried insulating film provided on the semiconductor substrate; a semiconductor layer provided on the buried insulating film; an N-type source layer formed in the semiconductor layer; an N-type drain layer formed in the semiconductor layer; a body region formed in the semiconductor layer to be provided between the source layer and the drain layer, the body region being in an electrically floating state and holding data according to a state of accumulating majority carriers in the body region; a gate insulating film provided on the body region; a gate electrode provided on the gate insulating film; and a P-type diffusion layer provided on a surface of the semiconductor substrate present under the drain layer, wherein a conduction type of a surface of the semiconductor substrate present under the body region is an N type.

Abstract: An integrated circuit structure is formed on a substrate. The integrated circuit structure includes a logic area and a memory cell area. The memory cell area includes a charge storage area and a non-charge storage area. A dielectric layer is formed on the substrate in the charge storage area. A thyristor is formed on the dielectric layer. A transistor is formed on the substrate in the non-charge storage area.

Abstract: A substrate for a semiconductor device is disclosed including, in one embodiment, a plurality of semiconductor-on-insulator (SOI) wafers bonded to one another in a single stack. A distal end of the stack includes a first SOI region with a first semiconductor layer having a thickness and a first surface orientation. A surface of the single stack may further include a non-SOI region and/or at least one second SOI region. The non-SOI region may include bulk silicon that extends through all of the insulator layers of the single stack and has a thickness different than that of the first silicon layer. Each second SOI region has a second semiconductor layer having a thickness different than that of the first semiconductor layer and/or a different surface orientation than the first surface orientation. The substrate thus allows formation of different devices on optimal substrate regions that may include different surface orientations and/or different thicknesses and/or different bulk or SOI structures.

Abstract: A method and the resultant memory is described for forming an array of floating body memory cells and logic transistors on an SOI substrate. The floating bodies for the cells are formed over the buried oxide, the transistors in the logic section are formed in the bulk silicon.

Abstract: An electronic circuit that drives a driven element to which driving voltage or driving current is supplied. The electronic circuit includes a signal line, a unit circuit connected to the signal line, and a voltage supply line. The unit circuit includes a driving transistor, a switching element, and a capacitive element. The driving transistor includes a gate terminal, a first terminal, a second terminal connected to the voltage supply line, and a channel formed between the first terminal and the second terminal. The switching element controls electrical connection between the gate terminal of the driving transistor and one of the first terminal and the second terminal. The capacitive element includes a first electrode connected to the gate terminal of the driving transistor and a second electrode connected to the signal line. A conductive state between the first terminal and the second terminal is controlled by a gate voltage applied to the gate terminal.

Abstract: There is provided a high-voltage-withstanding semiconductor device a fabrication method thereof capable of suppressing Vt fluctuation induced by plasma damage in a via hole forming step. In the high-voltage-withstanding semiconductor device, a gate electrode of a transistor having a gate insulating film formed on a semiconductor substrate and having a thickness of 350 ? or more and a diode composed of a first conductive well region formed in a surface layer region of the semiconductor substrate and a second conductive diffusion layer formed in the surface layer region of the semiconductor substrate and on the well region are electrically connected by a wire directly connected to contacts formed respectively on the gate electrode and the diode, via the contacts.

Abstract: This invention discloses a ballasting resistor for an electrostatic discharge (ESD) device that comprises at least one first active region forming a source/drain of an ESD discharge transistor, at least one resistive element with a serpentine shape formed in a single layer of a semiconductor structure, wherein the resistive element has a first terminal coupled to the first active region and a second terminal coupled to a bonding pad including power supply (Vdd or Vss) pads.

Abstract: A FinFET includes a silicon layer deposited on a silicon substrate and configuring source/drain regions and a channel region. The gate of the FinFET includes a pair of first electrode layers sandwiching therebetween the channel region in the horizontal direction with an intervention of first gate insulation films, and a second gate electrode layer overlying the channel region with an intervention of a second gate insulation film and formed in contact with top of the first electrode layers.

Abstract: A planar, double-gate transistor structure comprising upper and lower gate stacks that each comprises a single-phase high-K dielectric gate dielectric is disclosed. The transistor structure is particularly suitable for fully-depleted silicon-on-insulator electronics having gate-lengths less than 65 nm.

Abstract: A DRAM device includes contact pads having a bottom in contact with a corresponding source/drain region 21 and a top in contact with a bottom of an overlying contact plug. The source/drain region has a recess caused by misalignment of the contact pad with respect to the source/drain region, the recess causing division of the original source/drain region. An additional diffused region is formed by ion-implantation to couple the divided source/drain region to reduce the junction leakage current flowing across the source/drain region.

Abstract: A MISFET includes source/drain regions each including a plurality of divided substrate regions divided by intervening insulation films, and a selectively-grown silicon layer formed on the divided substrate regions and intervening insulation film to electrically couple together the divided substrate regions. The resultant MISFET has a reduced junction capacitance across the p-n junction of the source/drain regions, to improve the operation speed of the MISFET.

Abstract: A stacked semiconductor device includes a first gate structure formed on a substrate, a first insulating interlayer covering the first gate structure on the substrate, a first active pattern formed through and on the first insulating interlayer and contacting the substrate, a second gate structure formed on the first active pattern and the first insulating interlayer, a buffer layer covering the second gate structure on the first active pattern and the first insulating interlayer, a second insulating interlayer formed on the buffer layer, and a contact plug formed through the first and second insulating interlayers, which contacts with the substrate and is insulated from the second gate structure by the buffer layer. Operation failures of a transistor in the stacked semiconductor device can be reduced because the buffer layer prevents a word line from being electrically connected to the contact plug.

Abstract: Example embodiments relate to a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may have reduced disturbances during reading operations and a reduced short channel effect. The semiconductor device may include a semiconductor substrate having a body and a pair of fins protruding from the body. Inner spacer insulating layers may be formed on an upper portion of an inner sidewall of the pair of fins so as to reduce the entrance to the region between the pair of fins. A gate electrode may cover a portion of the external sidewalls of the pair of fins and may extend across the inner spacer insulating layers so as to define a void between the pair of fins. Gate insulating layers may be interposed between the gate electrode and the pair of fins.

Abstract: Embodiments of the present invention provide a method of forming a conductive stud contacting a semiconductor device. The method includes forming a protective layer covering the semiconductor device; selectively etching an opening down through the protective layer reaching a contact area of the semiconductor device, the opening being away from a protected area of the semiconductor device; and filling the opening with a conductive material to form the conductive stud. One embodiment may further include forming a dielectric liner directly on top of the semiconductor device, and forming the protective layer on top of the dielectric liner. Embodiments of the present invention also provide a semiconductor device made thereof.

Abstract: Provided is a method for manufacturing a semiconductor device. In the method, a gate oxide layer, a gate polysilicon layer, and a capping oxide layer are sequentially formed on a semiconductor substrate. A photoresist pattern is formed on the capping oxide layer. The capping oxide layer, gate polysilicon layer, and gate oxide layer are sequentially etched using the photoresist pattern as an etch mask. Ions are then implanted into the semiconductor substrate using the photoresist pattern as a mask. A thermal diffusion process is performed to form source/drain regions. The capping oxide layer is removed, and ions are implanted into the gate polysilicon layer. After metal is deposited on the gate polysilicon layer, a silicide is formed.

Abstract: Embodiments of the present invention provide a method of forming a conductive stud contacting a semiconductor device. The method includes forming a protective layer covering the semiconductor device; selectively etching an opening down through the protective layer reaching a contact area of the semiconductor device, the opening being away from a protected area of the semiconductor device; and filling the opening with a conductive material to form the conductive stud. One embodiment may further include forming a dielectric liner directly on top of the semiconductor device, and forming the protective layer on top of the dielectric liner. Embodiments of the present invention also provide a semiconductor device made thereof.

Abstract: An encapsulated device includes a micro device on a substrate, a cover bonded to the substrate thereby forming a chamber to encapsulate the micro device, and a desiccant material on the cover and in the chamber. An anti-stiction material is absorbed in the desiccant material.

Abstract: A method for manufacturing an image sensor includes forming first to third photodiodes and first to third color filters corresponding thereto; forming a photoresist film including photosensitive materials on the upper surfaces of the first to third color filters; forming a first exposed part by exposing the photoresist film with a first exposure energy using a first pattern mask with a first light transmitting part having a first width at boundaries between the individual color filters; forming a second exposed part overlapping a portion of the first exposed part by exposing the photoresist film with a second exposure energy smaller than the first exposure energy using a second pattern mask with a second light transmitting part having a second width wider than the first width; and forming microlenses by developing the photoresist film.

Abstract: A photodiode that can separately detect the intensities of the three wavelength ranges of ultraviolet light of 400 nm or below includes an insulating layer; and a plurality of silicon semiconductor layers having different thicknesses formed on the insulating layer, wherein each of the plurality of silicon semiconductor layers has a low-concentration diffusion layer formed by diffusing one of a P-type impurity or an N-type impurity therein with a low concentration; a P-type high-concentration diffusion layer formed by diffusing a P-type impurity therein with a high concentration; and an N-type high-concentration diffusion layer formed by diffusing an N-type impurity therein with a high concentration, and wherein the P-type high-concentration diffusion layer and the N-type high-concentration diffusion layer formed in a respective one of the plurality of silicon semiconductor layers are arranged to face each other with the low-concentration diffusion layer interposed there between.

Abstract: A method of processing a substrate having first and second surfaces applies a first dopant in liquid form on the first surface of the substrate, and applies a second dopant in liquid form on the second surface of the substrate. The method then causes the first and second dopants to diffuse into the substrate.

Abstract: A high-voltage semiconductor device includes a semiconductor layer having a plurality of pillars of a first conductivity type defined by a plurality of trenches which extend from a top surface of the semiconductor layer toward a bottom surface thereof. A charge compensation layer of a second conductivity type is disposed over at least sidewalls of each trench to a predetermined thickness to form a groove in each trench. A charge compensation plug of the first conductivity type substantially fills each groove.

Abstract: An integrated circuit device includes an integrated circuit substrate and a first gate pattern on the substrate. A non-conductive barrier layer pattern is on the first gate pattern. The barrier layer pattern has openings at selected locations therein extending to the first gate pattern. A second gate pattern is on the barrier layer pattern and extends into the opening in the barrier layer pattern to electrically connect the second gate pattern to the first gate pattern.

Abstract: A semiconductor device includes: a first element isolation film that is formed by a LOCOS oxidation method on a semiconductor substrate for isolating a first element region from other regions; a second element isolation film embedded in a groove formed in the semiconductor substrate for isolating a second element region from other regions; a first semiconductor element formed in the first element region; a second semiconductor element formed in the second element region; and a resistance element formed on the first element isolation film.

Abstract: The present invention provides antifuse structures having an integrated heating element and methods of programming the same, the antifuse structures comprising first and second conductors and a dielectric layer formed between the conductors, where one or both of the conductors functions as both a conventional antifuse conductor and as a heating element for directly heating the antifuse dielectric layer during programming.

Abstract: Herein described are at least a layout of an integrated circuit chip that is resistant to the negative effects of IR power supply voltage drops and a method of implementing the integrated circuit chip. The integrated circuit chip layout comprises one or more capacitors positioned in between adjacent functional blocks. The one or more capacitors provide a charge reservoir for use by functional blocks that are affected by IR power supply voltage drops. The method for implementing the integrated circuit chip comprises positioning one or more capacitors in between adjacent functional blocks and connecting one end of each of the one or more capacitors to a power supply rail while connecting the other end to a ground rail. Each of the one or more capacitors may be implemented using a polysilicon layer and an N-well layer.

Abstract: A capacitance structure of a semiconductor device and a method for manufacturing the structure are provided. The capacitance structure comprises a plurality of capacitance elements and a plurality of supports. Each of the capacitance elements has a column, and each of the supports is disposed between two adjacent columns by partially connecting onto the outer surface of each of the two adjacent columns. Thereby, the mechanical properties of the capacitance structure can be enhanced.

Abstract: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

Abstract: A method for fabricating a hybrid orientation substrate provides for: (1) a horizontal epitaxial augmentation of a masked surface semiconductor layer that leaves exposed a portion of a base semiconductor substrate; and (2) a vertical epitaxial augmentation of the exposed portion of the base semiconductor substrate. The resulting surface semiconductor layer and epitaxial surface semiconductor layer adjoin with an interface that is not perpendicular to the base semiconductor substrate. The method also includes implanting through the surface semiconductor layer and the epitaxial surface semiconductor layer a dielectric forming ion to provide a buried dielectric layer that separates the surface semiconductor layer and the epitaxial surface semiconductor layer from the base semiconductor substrate.

Abstract: An integrated circuit package system is provided including forming an external interconnect having a lead body and a lead tip, forming a lead protrusion in the lead tip, connecting a device and the external interconnect, and encapsulating the device and the external interconnect.

Abstract: A component arrangement comprising a carrier, a component in a housing with electrical contacts and a moulding compound that encloses the carrier, the semiconductor component in the housing and the electrical contacts, wherein the component is applied on the carrier, and wherein the carrier is provided with holes, and a method for producing a component arrangement, wherein the carrier is provided with holes, the component is positioned on the carrier, the component is connected to the carrier, the component with the carrier is positioned in the leadframe, and this arrangement is enclosed by a moulding compound.

Abstract: An integrated circuit package system is provided including forming a paddle, forming a ring with a recess in the paddle, mounting a device in the recess, forming a slot in the ring, and mounting a heat sink in the slot over the device.

Abstract: An integrated circuit package system is provided including forming a paddle having holes with a hole size in a range about tens to hundreds of micrometers, mounting a device over the paddle, and filling an encapsulation in the holes.

Abstract: Embodiments in accordance with the present invention relate to packaging designs for vertical conduction semiconductor devices which include low electrical resistance contacts with a top surface of the die. In one embodiment, the low resistance contact may be established by the use of Aluminum ribbon bonding with one side of a leadframe, or with both of opposite sides of a leadframe. In accordance with a particular embodiment, the vertical conduction device may be housed within a Quad Flat No-lead (QFN) package modified for that purpose.

Abstract: A circuit board assembled with an electronic package having a first and a second inner leads is provided. The first inner lead has a first and a second ends. The circuit board includes an insulating layer, a first pad, a second pad, an extension portion, a conductive via, and a ground layer. The first and the second pads are disposed on the insulating layer. The first end of the first inner lead is electrically connected to the second pad. The extension portion disposed on the insulating layer is electrically connected to the first pad and extends to the position under the second end of the first inner lead. The conductive via passing through the insulating layer is electrically connected to the extension portion and under the second end of the first inner lead. The ground layer disposed on the insulating layer is electrically connected to the conductive via.

Abstract: A power MOSFET is provided on a semiconductor die to withstand radiation exposure. The semiconductor die is mounted on a die flag of a leadframe. The MOSFET includes a substrate and epitaxial layer formed over the substrate. A source region is formed in a surface of the semiconductor die. The source region is coupled to the die flag. A contact pad is formed on the source region. A base region is formed in the surface of the semiconductor die adjacent to the source region. The base region is electrically connected to the contact pad. A drain region is formed in the surface of the semiconductor die. The drain region is coupled to a first wire bond pad on the leadframe. A gate structure is formed over a channel between the source region and drain region. The gate structure is coupled to a second wire bond pad on the leadframe.

Abstract: An integrated circuit package system is provided including mounting a first device on a carrier, mounting a second device over the first device and the carrier in an offset face-to-face configuration, and connecting the first device and the second device at an overlap.

Abstract: The present invention disclosed a wafer level chip size packaged chip device with a double-layer lead structure and methods of fabricating the same. The double-layer lead is designed to meet a tendency of increasing quantity per area of peripheral arrayed compatible pads on a semiconductor chip, and also to save more space for layout of lead on the chip bottom surface for avoiding potential short inbetween which happen in increasing probability with increasing quantity per area on the condition of one-layer lead.

Abstract: Embodiments of the present invention provide a MSP having an upper and lower package, with a recess opening in the substrate of the upper package. The upper package may also include multiple stacked semiconductor chips. A lower package may include a substrate and at least one semiconductor chip. During assembly, portions of a lower package are placed into the recess opening in the substrate of the upper package. The beneficial result is a two-package MSP assembly with a reduced total height. In addition, the size and pitch of solder balls or other joints between the upper package substrate and the lower package substrate may also be reduced.

Abstract: Provided is a semiconductor device package. The semiconductor device package includes: stacked semiconductor chips having bonding pads; a PCB (printed circuit board) mounting the stacked semiconductor chips thereon, and including bonding electrodes that correspond to the bonding pads; and interposers respectively covering the stacked semiconductor chips and interposed between the stacked semiconductor chips. The interposers comprise wire patterns connecting the bonding pads with the bonding electrodes, and connecting the interposers to each other.

Abstract: Example embodiments of the invention may provide for a multi-package system. The multi-package system may include a first package having a plurality of first organic dielectric layers, where the first package includes at least one first conductive layer positioned between two of the plurality of first organic dielectric layers, and where the at least one first conductive layer is circuitized to form at least one first passive device. The multi-package system may also include a second package having a plurality of second organic dielectric layers, where the second package includes at least one second conductive layer positioned between two of the plurality of second organic dielectric layers, and where the at least one second conductive layer is circuitized to form at least one second passive device. An electrical connector may be provided between a bottom surface of the first package and a top surface of the second package to electrically connect the first package and the second package.

Abstract: In one embodiment, a semiconductor package structure includes a plurality of upright clips having ends with mounting surfaces for vertically mounting the package to a next level of assembly. A semiconductor chip is interposed between the upright clips together with one or more spacers.