Abstract: A design structure embodied in a machine readable medium used in a design process includes a circuit that employs an anti-tamper sensor. The circuit employs an anti-tamper sensor that includes a circuit element that is responsive to a first input and to a second input. A selective coupling element couples the circuit element to the first input and is responsive to the anti-tamper sensor. The selective coupling element has a first state that allows the circuit element to operate normally when the anti-tamper sensor does not detect a tamper condition and is configured to enter a second state that causes the circuit element to become inoperable when the anti-tamper sensor detects a tamper condition. A decoy coupling element is disposed between the second input and the circuit element and has an appearance corresponding to the selective coupling element.

Abstract: An output buffer circuit for improving an output during state transitions of CMOS buffers driving transmission line loads. The circuit generates variable output impedance proportional to the load transmission line impedance. The buffer includes an output stage, such as pull up/pull down drivers for receiving an input signal and generating an output signal. The pull up/pull down drivers are biased by a circuit that generates a control signal and varies its conductivity according to the control signal. The pull up/pull down drivers initially provide a relatively low impedance to reach a desired level during the initial transition period of the output and then slowly varies its impedance in response to the control signal to suppress the ringing effect. The control circuit coupled to the input node, output node and the power supply node to generate a control signal that biases the pull up/pull down driver.

Abstract: An application-specific integrated circuit (ASIC) for use with a programmable I/O module includes programmable circuitry that enables the ASIC to be configured to support various different I/O functions. The ASIC includes a pin interface, a data interface, a digital section, and an analog section. The pin interface supports analog and digital signal communication and the data interface supports digital data communication. The digital section includes registers for storing digital data such as configuration commands, signal control commands, and digital signal information. The analog section is in electrical signal communication with pin interface and digital data communication with the registers.

Abstract: In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.

Abstract: An n-valued switch with n?2, with an input enabled to receive a signal in one of n states, an output enabled to provide a signal in one of at least 2 states, under control of a control signal having one of at least 2 states is disclosed. Signals are instances of a physical phenomenon, an instance representing a state. N-valued inverters are also disclosed. Different types of signals are disclosed, including optical signals with different wavelengths, electrical signals with different frequencies and signals represented by a presence of a material. A kit including an n-valued switch is also disclosed.

Abstract: A method of calibrating longitudinal balance for a subscriber line interface circuit includes providing a first and a second driver of a differential driver pair for driving a subscriber line. An output of each of the first and second drivers is coupled to a common output. The common output is coupled to an input of the first driver. The gain of at least one of the first and second drivers is adjusted until a calibration signal (V1) present at the input of the first driver is substantially the same as a calibration signal (V2) present at the input of the second driver.

Abstract: A detection device includes a detection circuit and a reference voltage supply circuit. The detection circuit includes an amplifier circuit, a synchronous detection circuit, and a filter section. The reference voltage supply circuit includes a first supply circuit which includes a reference-voltage first-type operational amplifier and supplies an analog reference voltage to the amplifier circuit, and a second supply circuit which includes a reference-voltage second-type operational amplifier and supplies the analog reference voltage to the filter section.

Abstract: An electronic device for determining a type of a memory includes a comparator and a reset controller. The comparator for generating a discrimination signal according to a reference voltage and a first voltage of the memory, includes a first input end for receiving the first voltage, a second input end for receiving the reference voltage, a logic circuit coupled to the first input end and the second input end, for comparing the first voltage and the reference voltage so as to generate the discrimination signal, and an output end coupled to the logic circuit, for outputting the discrimination signal. The reset controller is used for determining the type of the memory according to the discrimination signal.

Abstract: An input receiver includes a negative voltage generator and an amplifier for amplifying an input signal. The negative voltage generator generates a negative voltage. The amplifier is coupled to the input signal, a supply voltage, and the negative voltage, and amplifies the input signal to generate an amplified signal accordingly.

Abstract: The input buffer circuit includes: a first buffer adapted to buffer a clock enable signal in modes other than a self refresh mode; a second buffer adapted to buffer the clock enable signal in the self refresh mode; and an output unit adapted to select output signals of the first and second buffers. In the input buffer circuit, the first buffer operates at a higher speed than the second buffer, and the amount of current consumed by the second buffer is smaller than the amount of current consumed by the first buffer.

Abstract: A driving adjustment circuit that increases the driving capability of amplifier by adding a driving current directly to an output stage of the amplifier is provided. The driving adjustment circuit adjusts the driving capability according to an external load. Thus, the present invention not only solves the problem of insufficient driving capability of a digital-to-analog converter, but also effectively reduces unnecessary high power consumption and improves the stability of the system by adjusting the driving capability of the amplifier according to the external load.

Abstract: A buffer circuit buffers incoming signals, from a local oscillator generator to a mixing circuit and has a push-pull circuit having two inputs, a first being coupled to a first incoming signal, and a second of the inputs being coupled to one of the buffered versions of the incoming signals, having a phase related to that of the first incoming signal. By coupling a second input to a buffered version rather than to the incoming signal, the load presented to the preceding circuit can be halved, while maintaining reduced power consumption. By using as a second input, a signal which is phase related to the first incoming signal, the normal operation of the push-pull circuit can be maintained. The incoming signals from the LO generator can be differential IQ signals and the buffered version of the further incoming signal be in phase with the first incoming signal.

Abstract: A ramp generation circuit including, a charge supply unit which generates predetermined charges every predetermined time, an integration circuit which accumulates the charges generated from the charge supply unit and converts the charges into a voltage, and, an attenuation unit which outputs, to an output terminal, a voltage obtained by attenuating a noise value of an output voltage from the integration circuit.

Abstract: Aspects of the present invention include a method, apparatus and device for generating a power on reset (POR) signal in relation to the crossing point of two currents wherein at least one current is a quadratic function and the other is an exponential function, where each has a mathematical correlation to a function of a predetermined power supply voltage.

Abstract: A power-up reset circuit includes a sensing circuit and an output circuit. The sensing circuit outputs a node voltage in response to an external power supply voltage. The output circuit outputs a voltage sensing signal in response to the node voltage. A signal generation circuit outputs a reset signal in response to the voltage sensing signal. A first resistance adjustment circuit adjusts the level of the node voltage in response to an externally input first control signal. A second resistance adjustment circuit adjusts the level of the voltage sensing signal in response to an externally input second control signal.

Abstract: A switching booster power circuit includes a power switch, a booster circuit, a switching control, a voltage detector and a delay circuit. The voltage detector detects an input voltage value at a predetermined point of an electricity supply line from the power switch to an electric load, and determines the input voltage value to be larger than a predetermined voltage threshold or not. The delay circuit outputs an enabling signal enabling the switching control to operate, when a predetermined time period is elapsed after the input voltage value becomes larger than the voltage threshold.

Abstract: A DLL circuit includes a clock selection control unit configured to generate a clock selection signal on the basis of a phase difference between a reference clock and a feedback clock and, after the clock selection signal is generated, to generate an initialization signal. A delay control unit, when the initialization signal is enabled, transfers an initial voltage to be generated by dividing an external power supply voltage to a delay unit as a control voltage, and controls a delay operation of a delay reference clock to be selected on the basis of the clock selection signal.

Abstract: The data output control signal generating circuit includes a delay correction signal generating unit that delays an input signal by a phase difference between a clock and a delay locked loop clock, and latches the delayed signal to generate a plurality of output enable signals. A column address strobe latency control multiplexer selects the output enable signal corresponding to column address strobe latency among the plurality of output enable signals, on the basis of the signal obtained by delaying the input signal by the phase difference between the clock and the delay locked loop clock, and outputs the selected signal as the data output control signal.

Abstract: A high speed, low jitter phase locked loop (PLL) with feed forward phase frequency detection is disclosed. The phase frequency detector can include a phase difference sensor providing an output signal indicating a phase difference duration between a rising edge of a reference signal and a rising edge of a feedback signal. The apparatus can also include a lead lag sensor to provide an out put signal indicating when the reference signal leads the feedback signal. In addition, a steering logic module can be coupled to the output of the phase difference sensor and the lead lag sensor and the steering logic module can steer the phase difference duration signal to a first output when the reference signal leads the feedback signal, and can steer the phase difference signal to a second output when the reference signal lags the feedback signal.

Abstract: A charge pump circuit is provided with a capacitor for generating a boosted voltage from a power supply voltage in response to a clock signal; and an output node from which the boosted voltage is externally outputted. The capacitor includes a first well formed within a substrate, a second well formed within the first well, first and second diffusion regions formed within the second well to receive the clock signal, a channel region provided between the first and second diffusion regions in which channel region a channel is formed in response to the clock signal; and an electrode positioned over the channel region across a dielectric and connected with the output node. The output node is also connected with the first well to apply said boosted voltage to the first well.

Abstract: A novel wideband, low bit-error rate, dual-loop data recovery architecture is disclosed. The architecture employs a wideband clock receiver PLL that receives a synchronizing clock and generates the necessary high frequency clock for data transmission and recovery. The wideband PLL translates operating frequency information into a current reference that is transmitted to all data receiver channels. This current reference is employed to control a matched open-loop delay line at each data receiver. The phase clocks generated by this matched delay line maintain their angular relationship with respect to the primary clock transmitted by the wideband PLL over the entire range of frequencies. A bang-bang algorithm employed in the data receivers renders any delay mismatch between data receiver delay lines and the primary PLL inconsequential.

Abstract: An apparatus for setting an operation mode in a DLL circuit generates a locking completion signal according to a level of a phase comparing signal obtained by comparing phases of a reference clock and a feedback clock. During three or more cycles of a pulse signal, it is determined whether a logic value of levels of the phase comparing signal is a specific combination, and the locking completion signal is selectively enabled.

Abstract: A tunable delay line is calibrated to maintain the delay of the delay line at a desired value or within a desired range of values. In some aspects a signal is passed through a delay line multiple times so that the cumulative delay of the signal through the delay line (e.g., as indicated by a count) may be calculated over a period of time. The count is compared with an expected count and, based on this comparison, the delay of the delay line is adjusted as necessary. In some aspects the signal may comprise a digital signal. In some aspects a delay through a delay line may be calculated based on analysis of amplitude changes in a signal caused by a phase shift imparted on the signal by the delay line. In some aspects a delay line is incorporated into a transmitted reference system to generate and/or process transmitted reference signals.

Abstract: A cycle modulation circuit capable of limiting peak voltage to provide a pulse width control signal to a rear end power driving unit includes a comparison unit, an input voltage source and a linear voltage generation unit. The comparison unit compares an oscillation waveform signal generated by the linear voltage generation unit against a base value of a waveform signal level generated by the input voltage source to modulate and output the pulse width control signal of a combined cycle consisting of a high level and a low level. The pulse width control signal is input to the rear end power driving unit to limit the power driving unit in an equal restricted voltage peak value zone and determine the allowable duty cycle according to the level waveform signal.

Abstract: A pulse controller with dual latches includes a first latch unit and a second latch unit, in which two latch units are used to latch signal level for ensuring a sufficient conducting amount of the switching element in the rear end power output unit, and through a mutual interaction between the first and the second latch units, a complementary turning-on and turning-off situation therebetween is formed, and further, the signal from a trigger signal source and the feedback from the power output unit are employed to generate the duty cycle signal for the power output unit so as to replace the conventional pulse width modulation circuit.

Abstract: A method, an apparatus, and a computer program are provided to measure and/or correct duty cycles. Duty cycles of various signals, specifically clocking signals, are important. However, measurement of very high frequency signals, off-chip, and in a laboratory environment can be very difficult and present numerous problems. To combat problems associated with making off-chip measurements and adjustments of signal duty cycles, comparisons are made between input signals and divided input signals that allow for easy measurement and adjustment of on-chip signals, including clocking signals.

Abstract: A reset transistor is prevented from being deteriorated when power-down occurs during a programming operation or an erasing operation. It is made possible to protect the reset transistor as well as other transistors in a circuit to which a high voltage is applied when the power-down occurs during the erasing operation on an EEPROM, because the system is not reset all at once based only on a first reset signal POR of a power-on reset circuit, but is reset based on the first reset signal POR and a low voltage detection signal LD from a low voltage detection circuit so that the reset transistor is not turned on while the high voltage is applied to it.

Abstract: A method and latch circuits are provided for implementing enhanced noise immunity performance. Each latch circuit includes an L1 latch and an L2 latch coupled to the L1 latch. Data is first latched in the L1 latch during a first half clock cycle and then latched in the L2 latch during a second half clock cycle. A path opposite a latched data state is gated off in both the L1 latch and the L2 latch, where a path to a voltage supply rail is gated off with a latched low data state and a path to ground is gated off with a latched high data state.

Abstract: A broad frequency range phase shift circuit is responsive to a radio-frequency signal generated by a radio-frequency source and generates a lagging phase signal and a leading phase signal, 90° out of phase with the lagging phase signal, corresponding to the radio-frequency signal. An operational amplifier has a signal input that receives the radio-frequency signal from the radio-frequency source and generates a low impedance amplified output signal. A series resonant circuit receives the amplified signal from the operational amplifier and shifts the phase of the amplified signal in an amount that approaches 90° as the amplified signal frequency approaches DC to 0° as the amplified signal frequency increases to the cut-off frequency. A transmission line receives the amplified signal from the operational amplifier and has an electrical length substantially equal to one-fourth of a wavelength corresponding to the cut-off frequency.

Abstract: A variable delay element includes first and second input stages, each input stage comprising a charge pumping circuit and a discharging circuit, each charge pumping circuit and each discharging circuit associated with the first and second input stages configured to operate on opposite phases of an input signal, and an output stage comprising at least two transistors. The transistors are independently controlled by the first and second input stages and produce an output signal which is a delayed version of the input signal.

Abstract: A voltage level shifter converts an input signal into an output signal. While the input signal is high to the output signal is high either. Moreover, while the input signal is low the output signal is low either.

Abstract: A level conversion circuit includes a high-potential-side level conversion unit which is connected between a first high-voltage power supply and a first low-voltage power supply, and converts a high-potential-side voltage of an input signal, a low-potential-side level conversion unit which is connected between a second high-voltage power supply with a lower voltage than the first high-voltage power supply and a second low-voltage power supply with a lower voltage than the first low-voltage power supply, and converts a low-potential-side voltage of the input signal, and an output unit to which an output of the high-potential-side level conversion unit and an output of the low-potential-side level conversion unit are input, and which outputs a voltage level of the first high-voltage power supply and a voltage level of the second low-voltage power supply.

Abstract: A power switching circuit in CMOS technology has a power MOS transistor and a driver stage. The power MOS transistor is operated at a higher supply voltage in excess of its maximum allowable gate-source voltage; and the driver stage of the level shifter is operated at a lower supply voltage substantially lower than the supply voltage for the power MOS transistor. The driver stage includes a pair of driver MOS transistors coupled in series between a higher supply voltage rail and a reference potential rail, and at an interconnection node coupled to the gate of the power MOS transistor. The gates of the driver MOS transistors are AC-coupled to drive signals of mutually opposite phase; and the gates of the driver MOS transistors are each connected to the higher voltage supply rail through a respective parallel connection of a first resistor and a second resistor connected in series with a non-linear component.

Abstract: A pumping voltage generating apparatus includes a detection signal generating unit that generates a detection signal when a pumping voltage is lower than a reference value. A pumping unit elevates a first external voltage by a second external voltage to be output as the pumping voltage, in response to the detection signal. In this case, the second external voltage is lower than the first external voltage.

Abstract: A voltage pumping device is disclosed. The device may include a voltage level detector for detecting a level of a voltage fed back thereto and generating a voltage pumping enable signal according to the detected voltage level, an oscillator for operating in response to the voltage pumping enable signal and generating a desired pulse signal in a normal operation mode, a clock supply controller for receiving an external clock signal, operating in response to the voltage pumping enable signal and outputting the external clock signal in a low-power operation mode, and a voltage pump for performing a voltage pumping operation in response to the pulse signal from the oscillator in the normal operation mode and performing the voltage pumping operation in response to the clock signal from the clock supply controller in the low-power operation mode.

Abstract: A semiconductor device comprising an internal current generating section (1) for supplying an output current (i2) dependent on an input current (i1) into an IC, an external terminal (2) for connecting an external resistor (Rex) to the input end side of the internal current generating section (1), a current limiting element (3) connoted between the input end of the internal current generating section (1) and the external terminal (2), a first current limiting section (4) for pulling in the input current (i1) when one end voltage VA of the current limiting element (3) is higher than a first threshold voltage VB, and a second current limiting section (5) for pulling in the input current (i1) when the terminal voltage VC of the external terminal (2) is higher than a second threshold voltage. System down can be avoided by operating the internal circuit surely regardless of the state of the external terminal.

Abstract: A flash memory device applies a low read voltage at increased flash memory device temperatures. A high read voltage is applied when a supply voltage is high, thereby maintaining a stable threshold voltage margin of a programmed cell or an erased cell. As a result, the reliability of the flash memory cell is enhanced.

Abstract: A method and system for automatically detecting and optimally compensating a wide range of die leakage currents in dynamic circuits is presented. A self-adaptive keeper tracks the leakage and reduces the leakage effects by optimally controlled compensation current. The self-adaptive keeper utilizes a 2-stage embedded current mirror circuit, a dummy cell and a keeper transistor to compensate leakage current. The load impact of the self-adaptive keeper on the dynamic circuit components (for example, the impact on memory cells) is minimized by a dummy cell which detects and matches the instant leakage current. Amplification in the 2-stage embedded current mirror circuit provides an optimal current strength in the keeper transistor. The optimally amplified leakage current is utilized to compensate for a leakage induced voltage drop at the circuit's output. Thus, the self-adaptive keeper ensures the robustness of the circuit in real time and does not create any negative trade-off on read latency.

Abstract: An apparatus and a method to reduce temperature dependence of a reference voltage have been presented. In one embodiment, the method includes generating a reference voltage associated with a difference between a first threshold voltage of a first transistor and a second threshold voltage of a second transistor. The method may further include biasing the first transistor and the second transistor at a predetermined ratio of currents of the first and the second transistors to reduce temperature dependence of the reference voltage.

Abstract: A DC offset cancellation block is provided for canceling a DC offset in a signal path. The signal path may include an input and an output. The DC offset cancellation block may include an active integrator coupled between the input and the output to provide a negative feedback to the signal path. The active integrator may include an operational-amplifier (op-amp), a capacitive component with a capacitance C, and a resistive component with a resistance R, and the capacitive component may be coupled to the op-amp via a closed feedback loop. The DC offset cancellation block may also include a first amplifier with a gain of GA coupled with the capacitive component in the closed feedback loop such that a RC time constant of the active integrator is changed from RC to RCGA.

Abstract: The present invention relates to an H-bridge controller and method for controlling a common-mode voltage and/or current of an H-bridge circuit. The H-bridge controller comprises a section for receiving a signal indicating at least one of a common-mode voltage and common-mode current of the H-bridge circuit, and a section for generating control signals which determine switching of the H-bridge circuit so as to control at least one of the common-mode voltage and common-mode current of the H-bridge circuit.

Abstract: Noise reduction for a switching amplifier system having a differential output stage and demodulator filter responsive to complementary PWM signals includes generating in-phase PWM signals and gradually adjusting their duty cycle between a low duty cycle and the full duty cycle of the complementary PWM signals, generating full duty cycle PWM signals and gradually shifting their relative phase between in-phase and out-of-phase; and in response to a turn-on signal, adjusting the in-phase PWM signals from low to full duty cycle and shifting the relative phase from in-phase to out-of-phase, and in response to a turn-off signal shifting the relative phase from out-of-phase to in-phase and adjusting the in-phase PWM signals from full to low duty cycle for maintaining balanced charge on the demodulation filter to reduce audible noise.

Abstract: An amplifier circuit with current noise reduction employs first and second variable impedance devices between a signal source and an amplifier. A modulation frequency generator establishes a modulation frequency fmod to alter the first and second impedance values out of phase from one another at the modulation frequency so that the sum of the first and second impedance values at the input of the amplifier is relatively constant. The modulation at frequency fmod shifts the signal to side bands about the modulation frequency. The output from the amplifier is passed to a bandpass filter centered on the modulation frequency in order to remove all frequencies outside the bandwidth of interest. The signal itself is recovered by demodulating the output of the bandpass filter using a synchronization signal that is derived from the modulation signal.

Abstract: One embodiment of the invention includes an amplifier system. The system comprises a digital predistortion (DPD) system configured to receive an input signal and to provide the input signal as a first digital signal component along a first amplifier path and a second digital signal component along a second amplifier path. The system also comprises a first digital-to-analog converter (DAC) configured to convert the first digital signal component to a first analog signal component and a second DAC configured to convert the second digital signal component to a second analog signal component. The system further comprises a Doherty amplifier comprising a main amplifier in the first amplifier path that is configured to amplify the first analog signal component and a peak amplifier in the second amplifier path that is configured to amplify the second analog signal component.

Abstract: A level control circuit is responsive to some parameter of an input signal, e.g., signal level, to selectively bypass around an active circuit (e.g., amplifier stage) rendered unnecessary in view of the detected condition of the input signal, e.g., a signal level satisfying some threshold criteria. In addition to bypassing the active circuit, the control circuit may interrupt power to the circuit. In the case of amplifier stage that may be part of a radio frequency (RF) input stage of a receiver or tuner, upon detecting some threshold input signal level, the amplifier circuit is bypassed, i.e., taken out of the circuit and power to the circuit removed.

Abstract: The present invention provides a class D amplifier and method for driving a tri-wired stereo amplifier. Additionally, the class D amplifier includes a first filter, a second filter, a processor, a 2D-quantitizer, a signal generator, and a logic circuit. The class D amplifier and method of the invention can reduce cost of production and increase processing efficiency. More particularly, the class D amplifier and method of the invention are processed in an optimal feedback mode, so as to reduce the reciprocal effect between the two channels, and avoid mismatch of the two amplifiers.

Abstract: A detection device includes a detection circuit. The detection circuit includes an amplifier circuit, a synchronous detection circuit, and a filter section. The amplifier circuit includes a first-type operational amplifier, and the filter section includes a second-type operational amplifier. When a channel width and a channel length of a differential-stage transistor of a differential section of the first-type operational amplifier are respectively referred to as W1a and L1a, a bias current flowing through the differential section is referred to as Ia, a channel width and a channel length of a differential-stage transistor of a differential section of the second-type operational amplifier are respectively referred to as W1b and L1b, and a bias current flowing through the differential section is referred to as Ib, W1b×L1b>W1a×L1a and Ia>Ib are satisfied.

Abstract: A rail-to-rail class-AB operational amplifier includes a first differential pair unit for receiving a pair of differential signals and generating a first control signal; a second differential pair unit for receiving the pair of differential signals and generating a second control signal; and an output stage for receiving the first control signal and the second control signal and then generating an output voltage. The first differential pair unit includes a first active load, a first transistor differential pair and a first current source. The second differential pair unit includes a second current source, a second transistor differential pair and a second active load.

Abstract: An analog circuit includes a first circuit including a first-type operational amplifier of which a frequency of an amplification target signal is a first frequency, and a second circuit including a second-type operational amplifier of which a frequency of an amplification target signal is a second frequency lower than the first frequency. When a channel width and a channel length of a differential-stage transistor of a differential section of the first-type operational amplifier are respectively referred to as W1a and L1a, a bias current flowing through the differential section is referred to as Ia, a channel width and a channel length of a differential-stage transistor of a differential section of the second-type operational amplifier are respectively referred to as W1b and L1b, and a bias current flowing through the differential section is referred to as Ib, W1b×L1b>W1a×L1a and Ia>Ib are satisfied.

Abstract: Disclosed is a data driver including a zero compensation resistor connected in series with a phase compensation capacitor between an output node of an input differential amplification stage and an output node of a succeeding amplification stage, and a control circuit that controls to switch a resistance value of the zero compensation resistor. The control circuit switches the resistance value of the zero compensation resistor to a first resistance value or a second resistance value larger than the first resistance value in response to turning off or on of an output switch that controls connection between the output terminal of an amplifying circuit and a data line.