Abstract: The disclosure provides methods for the determination of the enantiomeric excess of chiral compounds. The methods involve doping a chiral analyte into an achiral liquid crystal host to form a chiral dopant/host liquid crystal mixture. An electro-optic signature of the mixture is then determined and is used to calculate the enantiomeric excess of the chiral analyte. The disclosure also provides systems for performing the disclosed methods of determining enantiomeric excess.

Abstract: A test strip for the use of the determination of an analyte in a fluid sample according to one embodiment of the present invention is disclosed. The test strip comprises of a base having a top and a bottom, a collection chamber that extends between the top and the bottom of the base, a containing ring that is disposed on the bottom of the base and surrounds the collection chamber, and a capillary channel formed in top of the base that has an inlet fluidly coupled to the collection chamber and a test element disposed within the capillary channel. A lid is attached to the top of the base and covers the collection chamber, the test area, and at least a portion of the capillary channel.

Abstract: An immunochemical assay device for determining the presence of NT-proBNP alone or conjunctively with Cardiac Troponin I comprising a base member, an array disposed on the base member, and at least one assay indicia zone. The array comprises (i) a reservoir pad to receive sample liquid, (ii) a wicking membrane, and (iii) at least one filter zone interposed between the wicking membrane and the reservoir pad. The filter zone being operable to permit passage of any specific immunocomplex to the wicking membrane while impeding passage of larger components.

Abstract: A system and an apparatus for use in detecting a target microorganism or agent is disclosed which involves a solid support carrying a binding partner specific for the particular microorganism or agent and the solid support being characterised in that it defines means for protecting the binding partner from being dislodged or scraped off the solid support by physical means. The provision of protection against the binding partner being dislodged from or scraped off the solid support improves the reliability of tests such as immunoassays being conducted with the solid support and also enables such tests to be automated. Modules and machines for use with the solid support, and the automated conduct of tests ate also disclosed.

Abstract: Methods of patterning a magnetic stack of a magnetic memory cell and structures thereof. At least the top magnetic material layer of a magnetic stack is patterned using a hard mask, and a conformal insulating material is deposited over the patterned top magnetic material layer and hard mask. The conformal insulating material is anisotropically etched to remove the conformal insulating material over vertical sidewalls of at least the patterned top magnetic material layer and the hard mask. The remaining conformal insulating material comprises a sidewall spacer hard mask that is used as a mask to pattern the remaining material layers of the magnetic stack. The sidewall spacer hard mask may be left remaining in the magnetic memory cell structure.

Abstract: A ferroelectric random access memory (FRAM) includes a semiconductor substrate and an interlayer insulating layer on the substrate. A diffusion preventive layer is on the interlayer insulating layer. The diffusion preventive layer and the interlayer insulating layer have two node contact holes formed therein. Node conductive layer patterns are aligned with the node contact holes, respectively, and are disposed so as to protrude upward from the diffusion preventive layer. Lower electrodes are disposed on the diffusion preventive layer that cover the node conductive layer patterns, respectively. Thicknesses of the lower electrodes are gradually reduced from a line extending from upper surfaces of the node conductive layer patterns toward the diffusion preventive layer.

Abstract: The present invention discloses a ferroelectric register and a method for manufacturing a capacitor of the same. The ferroelectric register is configured to reduce probability of data storage failure due to a weak state capacitor, by connecting a plurality of capacitors in parallel in a ferroelectric capacitor unit for storing data, instead of using a single capacitor, thereby improving storage reliability and stability. In addition, the ferroelectric register obtains a data sensing margin by pumping a cell plate signal into not a power voltage level but a pumping voltage level.

Abstract: The present invention provides a method of manufacturing a silicon wafer where a defect does not exist at a wafer surface layer part on which a device is formed, without affecting productivity and production costs of the wafer. An ingot of a silicon single crystal is grown by way of Czochralski single crystal pulling method, this silicon single crystal ingot is sliced to produce a wafer, then a surface layer of the wafer is annealed for between 0.01 microseconds and 10 seconds (inclusive) by means of a laser spike annealing apparatus such that a temperature of a wafer surface layer part is between 1250° C. and 1400° C. (inclusive).

Abstract: A method for preserving semiconductor feature opening profiles for metrology examination including providing semiconductor wafer having a process surface comprising semiconductor feature openings; blanket depositing over the semiconductor feature openings to substantially fill the semiconductor feature openings at least one layer of material comprising silicon oxide; and, preparing a portion of the semiconductor wafer in cross sectional layout for metrology examination.

Abstract: A system and method are provided for qualifying or calibrating lithographic apparatus or parts therefor, using a predetermined objective criterion such as Chauvenet's criterion is used to reject measurement points, individually, by field or by substrate.

Abstract: A light emitting semiconductor bonding structure includes a structure formed by bonding a substrate onto a light emitting semiconductor. The substrate is a structure containing electric circuits. The ohmic contact N electrode layer and P electrode layer are formed on the N-type contact layer and the P-type contact layer of the light emitting semiconductor respectively. A first metallic layer and a second metallic layer are formed on the surface of the substrate by means of immersion plating or deposition. The metallic layers are connected electrically to the corresponding electric signal input/output nodes of the electric circuit of the substrate. The first metallic layer and the second metallic layer are bonded onto the N electrode layer and the P electrode layer respectively through supersonic welding, and as such the light emitting semiconductor is bonded onto the substrate, and thus realizing the electric connection in-between.

Abstract: A two-wavelength semiconductor laser device includes a first conductive material substrate having thereon first and second regions separated from each other. A first semiconductor laser diode is formed on the first region. A non-active layer is formed on the second region and has the same layers as those of the first semiconductor laser diode. A second semiconductor laser diode is formed on the non-active layer. A lateral conductive region is formed at least between the first and second semiconductor laser diodes.

Abstract: Methods and systems are provided of fabricating a compound nitride semiconductor structure. A substrate is disposed within a processing chamber into which a group-III precursor and a nitrogen precursor are flowed. A layer is deposited over the substrate with a thermal chemical-vapor-deposition process using the precursors. The substrate is transferred to a transfer chamber where a temperature and a curvature of the layer are measured. The substrate is then transferred to a second processing chamber where a second layer is deposited.

Abstract: An insulated gate field effect transistor, a solid-state image pickup device using the same, and manufacturing methods thereof that suppress occurrence of a shutter step and suppress occurrence of punch-through and injection. An insulated gate field effect transistor (30) having a gate electrode (32) on a semiconductor substrate (11) with a gate insulating film (31) interposed between the semiconductor substrate (11) and the gate electrode (32), and having a source region (33) and a drain region (34) formed in the semiconductor substrate (11) on both sides of the gate electrode (31), the insulated gate field effect transistor including: a first diffusion layer (12) of a P type formed in the semiconductor substrate (11) at a position deeper than the source region (33) and the drain region (34); and a second diffusion layer (13) of the P type having a higher concentration than the first diffusion layer (12) and formed in the semiconductor substrate (11) at a position deeper than the first diffusion layer (12).

Abstract: The contrast offered by a spatial light modulator device may be enhanced by positioning nonreflective elements such as supporting posts and moveable hinges, behind the reflecting surface of the pixel. In accordance with one embodiment, the reflecting surface is suspended over and underlying hinge-containing layer by integral ribs of the reflecting material defined by gaps in a sacrificial layer. In accordance with an alternative embodiment, the reflecting surface is separated from the underlying hinge by a gap formed in an intervening layer, such as oxide. In either embodiment, walls separating adjacent pixel regions may be recessed beneath the reflecting surface to further reduce unwanted scattering of incident light and thereby enhance contrast.

Abstract: The present invention advantageously provides for, in different embodiments, low-cost deposition techniques to form high-quality, dense, well-adhering Group IBIIIAVIA compound thin films with macro-scale as well as micro-scale compositional uniformities. In one embodiment, there is provided a method of growing a Group IBIIIAVIA semiconductor layer on a base, and includes the steps of depositing on the base a film of Group IB material and at least one layer of Group IIIA material, intermixing the film of Group IB material and the at least one layer of Group IIIA material to form an intermixed layer, and forming over the intermixed layer a metallic film comprising at least one of a Group IIIA material sub-layer and a Group IB material sub-layer. Other embodiments are also described.

Abstract: The use of atomic layer deposition (ALD) to form a nanolaminate layered dielectric layer of cerium oxide and aluminum oxide acting as a single dielectric layer with a ratio of approximately two to one between the cerium oxide and the aluminum oxide, and a method of fabricating such a dielectric layer is described. The described arrangement produces a reliable structure with a high dielectric constant (high-k) for use in a variety of electronic devices. The dielectric structure is formed by depositing cerium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing aluminum oxide onto the substrate using precursor chemicals, and repeating to form the thin laminate structure.

Abstract: A semiconductor device in the form of a resin sealed semiconductor package is disclosed, wherein a gate terminal connected to a gate pad electrode formed on a surface of a semiconductor chip and a source terminal connected to a source pad electrode formed on the chip surface exposed to a back surface of a sealing resin portion, a first portion of a drain terminal connected to a back-surface drain electrode of the semiconductor chip is exposed to an upper surface of the sealing resin portion, and a second portion of the drain terminal formed integrally with the first portion of the drain terminal is exposed to the back surface of the sealing resin portion.

Abstract: The present invention relates to an apparatus for stacking semiconductor chips, a method for manufacturing a semiconductor package using the same and a semiconductor package manufactured thereby. The apparatus for stacking semiconductor chips may comprise two tables for supporting wafers, a picker for picking up semiconductor chips and a picker transfer unit for moving the picker vertically and horizontally. The method for manufacturing a semiconductor package using the same may allow easy and rapid stacking of semiconductor chips, thereby improving the productivity of semiconductor package manufacture. Further, a semiconductor chip having a relatively thick film is attached onto another semiconductor chip having a relatively thin film. The thicker semiconductor chip may protect the thinner semiconductor chip from faults such as chipping or warpage which may occur due to external shocks such as that caused by a picker, thereby improving the reliability of the package.

Abstract: In multi-stack chip size packaging a plurality chips, a first chip is electrically interconnected on a top surface of a substrate using a bump. Next, an epoxy is coated on the first chip and is stacked a second chip thereon, wherein the second chip is electrically interconnected to the substrate through an inner lead bonding. A potting solution is coated on the substrate and the second chip and installed thereon a heat spreader and then cured. An encapsulation resin is coated on a bottom surface of the substrate and electrically interconnected a third chip to the bottom surface of the substrate through a bump and an inner lead bump.

Abstract: A method of using a contact printing stamp, including forming a transfer material on a plurality of stamping surfaces. The plurality of stamping surfaces are disposed on a plurality of stamp protrusions adapted from the forming of a stamp material in a plurality of recessed regions formed in an exposed end-region of a multilayer thin film structure.

Abstract: The present invention relates to a semiconductor package having a conductive molding compound to prevent static charge accumulation. By using a conductive molding compound heat conductivity is also increased and heat generated by the semiconductor chip is more effectively dissipated externally. Additionally, the conductive compound blocks electromagnetic waves making possible an optimal semiconductor package satisfying the electromagnetic compatibility (EMC) and increasing the reliability of the semiconductor chip especially when processing high-speed signals.

Abstract: The yield of semiconductor devices is to be enhanced. A tray is provided with a plurality of pockets each capable of accommodating a wafer level CSP, and each of the pockets is provided with a base for supporting a plurality of bumps of the wafer level CSP and side walls formed around the base. In the step-to-step carriage in the post-production process of the manufacture of wafer level CSPs and on like occasions, the base supports not the organic film but the plurality of solder bumps. For this reason, it is made possible to prevent the organic film from being flawed or coming off and adhering to the product as foreign matter, and as a result the quality and yield of the wafer level CSPs (semiconductor devices) can be improved.

Abstract: An integrated circuit has a semiconductor substrate and an interconnect layer that mechanically relatively weak and susceptible to cracks and delamination. In the formation of the integrated circuit from a semiconductor wafer, a cut is made through the interconnect layer to form an edge of the interconnect layer. This cut may continue completely through the wafer thickness or stop short of doing so. In either case, after cutting through the interconnect layer, a reconditioning layer is formed on the edge of the interconnect layer. This reconditioning layer seals the existing cracks and delaminations and inhibits the further delamination or cracking of the interconnect layer. The sealing layer may be formed, for example, before the cut through the wafer, after the cut through the wafer but before any packaging, or after performing wirebonding between the interconnect layer and an integrated circuit package.

Abstract: A micro package, a multi-stack micro package, and a manufacture method therefor are provided. A micro package according to the present invention includes a device substrate for mounting a devices, being a circuit module; a protection cap for protecting the device; bonding substances which, formed by patterning on predetermined areas on the device substrate, bond the device substrate and the protection cap; layers formed on a portion of the device substrate and a portion of the protection cap and exterior sides of the bonding substances; vias which are formed by etching away another portion of the protection cap, and electrically connected to an upper surface of the device substrate through the bonding substances; under barrier metals (UBMs) formed on the vias; and solder bumpers, being connection terminals for an external signal, formed on the UBMs.

Abstract: Improvement in the reliability of a semiconductor device is aimed at. By heating a lead frame, after preparing a lead frame with a tape, until a resin molding is performed, at the temperature 160 to 300° C. (preferably 180 to 300° C.) for a total of more than 2 minutes in the atmosphere which has oxygen, crosslinkage density becoming high in resin of adhesives, a low molecular compound volatilizes and jumps out outside, therefore as a result, since a low molecular compound does not remain in resin of adhesives, the generation of copper migration can be prevented.

Abstract: A thyristor-based semiconductor device includes a thyristor body that has at least one region in the substrate and a thyristor control port in a trenched region of the device substrate. According to an example embodiment of the present invention, the trench is at least partially filled with a dielectric material and a control port adapted to capacitively couple to the at least one thyristor body region in the substrate. In a more specific implementation, the dielectric material includes deposited dielectric material that is adapted to exhibit resistance to voltage-induced stress that thermally-grown dielectric materials generally exhibit. In another implementation, the dielectric material includes thermally-grown dielectric material, and when used in connection with highly-doped material in the trench, grows faster on the highly-doped material than on a sidewall of the trench that faces the at least on thyristor body region in the substrate.

Abstract: A method of forming a transistor reduces leakage current and hot carrier effects, and therefore improves current performance. The method of forming a transistor includes selectively etching the semiconductor substrate to form a substrate protrusion and expose a buried source/drain implant region. A gate insulating layer covers the substrate protrusion and the first source/drain region. A gate conductor layer is selectively etched to form a gate pattern covering the sidewalls of the substrate protrusion and a portion of the semiconductor substrate adjacent to the sidewalls of the substrate protrusion. A second source/drain region is stacked over the top of the substrate protrusion. Contacts connected to the gate pattern and the first and second source/drain regions.

Abstract: When a gettering sink is removed by using alkaline solution of etchant having a high selectivity to the gettering sink and a barrier film functioning as an etching stopper, residue of gettering is left. However, according to the present invention, a semiconductor film that serves as a gettering sink contains nitrogen at concentration of 1×1018 atoms/cm3 or lower, oxygen at concentration of 8×1019 atoms/cm3 or lower, and noble gas at concentration is of 1×1020 atoms/cm3 or higher. In order to achieve the above-described impurity concentrations, a concentration of oxygen that is an impurity element in a chamber is reduced by using a flammable gas for heating and exhausting oxygen.

Abstract: It is an object of the present invention to improve the usability of a material, and to provide a display device which can be manufactured by simplifying the manufacturing process and a manufacturing technique thereof. It is also an object of the invention to provide a technique in which a pattern of a wiring or the like constituting these display devices can be formed to have a desired shape with favorable controllability. One feature of a droplet discharge device of the invention comprises: a discharge means for discharging a composition including a pattern forming material; and a shape means for shaping the shape of the composition before the composition is attached to a formation region, in which the shape means is provided between the discharge means and the formation region.

Abstract: A mask is formed selectively on a crystalline silicon film containing a catalyst element, and an amorphous silicon film is formed so as to cover the mask. Phosphorus is implanted into the amorphous silicon film and the portion of the crystalline silicon film which is not covered with the mask. The silicon films are then heated by rapid thermal annealing (RTA). By virtue of the existence of the amorphous silicon film, the temperature of the crystalline silicon film is increased uniformly, whereby the portion of the crystalline silicon film covered with the mask is also heated sufficiently and the catalyst element existing in this region moves to the phosphorus-implanted, amorphous portion having high gettering ability. As a result, the concentration of the catalyst element is reduced in the portion of the silicon film covered with the mask. A semiconductor device is manufactured by using this portion.

Abstract: A bottom gate thin film transistor and method of fabricating the same are disclosed, in which a channel region is crystallized by a super grain silicon (SGS) crystallization method, including: forming a gate electrode and a gate insulating layer on an insulating substrate; forming an amorphous silicon layer on the gate insulating layer followed by forming a capping layer and a metal catalyst layer; performing heat treatment to crystallize the amorphous silicon layer into a polysilicon layer; and forming an etch stopper, source and drain regions and source and drain electrodes. The thin film transistor includes: an insulating substrate; a gate electrode formed on the substrate; a gate insulating layer formed on the gate electrode; a polysilicon layer formed on the gate insulating layer and crystallized by an SGS crystallization method; and source and drain regions and source and drain electrodes formed in a predetermined region of the substrate.

Abstract: A field effect transistor and a method of fabricating the field effect transistor. The field effect transistor includes: a silicon body, a perimeter of the silicon body abutting a dielectric isolation; a source and a drain formed in the body and on opposite sides of a channel formed in the body; and a gate dielectric layer between the body and an electrically conductive gate electrode, a bottom surface of the gate dielectric layer in direct physical contact with a top surface of the body and a bottom surface the gate electrode in direct physical contact with a top surface of the gate dielectric layer, the gate electrode having a first region having a first thickness and a second region having a second thickness, the first region extending along the top surface of the gate dielectric layer over the channel region, the second thickness greater than the first thickness.

Abstract: An object of the present invention is to provide a method for manufacturing a thin film transistor which enables heat treatment aimed at improving characteristics of a gate insulating film such as lowering of an interface level or reduction in a fixed charge without causing a problem of misalignment in patterning due to expansion or shrinkage of glass. A method for manufacturing a thin film transistor of the present invention comprises the steps of heat-treating in a state where at least a gate insulating film is formed over a semiconductor film on which element isolation is not performed, simultaneously isolating the gate insulating film and the semiconductor film into an element structure, forming an insulating film covering a side face of an exposed semiconductor film, thereby preventing a short-circuit between the semiconductor film and a gate electrode.

Abstract: A high voltage MOS transistor with a gate extension that has a reduced electric field in the drain region near the gate is provided. The high voltage MOS transistor includes a first and second gate layers, and a dielectric layer between the gate layers. The first and second gate layers are electrically coupled togther and form the gate of the transistor. The second gate layer extends over the drain of the transistor above the dielectric and gate oxide layers to form the gate extension. The gate extension reduces the peak electric field in the drain by providing a wide area for the voltage to drop between the drain and the gate of the transistor. The dielectric layer also reduces the peak electric field in the drain near the gate by providing insulation between the gate and the drain. A lower electric field in the drain reduces the impact generation rate of carriers.

Abstract: Manufacture of TFTs corresponding to various circuits makes structures thereof complex, which involves a larger number of manufacturing steps. Such an increase in the number of the manufacturing steps leads to a higher manufacturing cost and a lower manufacturing yield. In the invention, a high concentration of impurities is doped by using as masks a tapered resist that is used for the manufacture of a tapered gate electrode, and the tapered gate electrode, and then the tapered gate electrode is etched in the perpendicular direction using the resist as a mask. A semiconductor layer under the thusly removed tapered portion of the gate electrode is doped with a low concentration of impurities.

Abstract: Embodiments of methods, apparatuses, devices, and/or systems for forming a thin film component are described.

Abstract: The linear laser beam generally has a width of 1 mm or less, and it is necessary to adjust the optical system with high accuracy in order to form the laser beam having such a narrow width and having a homogeneous intensity distribution. The adjustment of the optical system requires a large amount of time, and the laser irradiation apparatus using this optical system cannot be used during the adjustment of the optical system. This causes the throughput to decrease. The present invention is made to facilitate a readjustment of the optical system and to shorten the time required for it. When the misalignment of the laser beam is corrected to keep the incident position in the optical system the same by moving the laser beam parallel with the use of a single optical element, it is no longer necessary to readjust all the optical elements, and therefore the time can be saved.

Abstract: In a field effect transistor (FET), and a method of fabricating the same, the FET includes a semiconductor substrate, source and drain regions formed on the semiconductor substrate, a plurality of wire channels electrically connecting the source and drain regions, the plurality of wire channels being arranged in two columns and at least two rows, and a gate dielectric layer surrounding each of the plurality of wire channels and a gate electrode surrounding the gate dielectric layer and each of the plurality of wire channels.

Abstract: A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both the gate and the substrate and impose forces on adjacent substrate areas. Another embodiment comprises compressive stresses imposed in the plane of the channel using SOI sidewall spacers made of polysilicon that is expanded by oxidation. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance have been demonstrated.

Abstract: A field effect transistor and method of fabricating the field effect transistor. The field effect transistor, including: a gate electrode formed on a top surface of a gate dielectric layer, the gate dielectric layer on a top surface of a single-crystal silicon channel region, the single-crystal silicon channel region on a top surface of a Ge including layer, the Ge including layer on a top surface of a single-crystal silicon substrate, the Ge including layer between a first dielectric layer and a second dielectric layer on the top surface of the single-crystal silicon substrate.

Abstract: Flash memory and methods of fabricating the same are disclosed. An illustrated example flash memory includes a first source formed within a semiconductor substrate; an epitaxial layer formed on an upper surface of the semiconductor substrate; an opening formed within the epitaxial layer to expose the first source; a floating gate device formed inside the opening; and a select gate device formed on the epitaxial layer at a distance from the floating gate device.

Abstract: A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and aligned by the fabrication process, without photolithographic patterning.

Abstract: In a silicon-oxide-nitride-oxide-silicon (SONOS) memory device and a method of manufacturing the same, a SONOS memory device includes a semiconductor substrate, an insulating layer deposited on the semiconductor substrate, an active layer formed on a predetermined region of the insulating layer and divided into a source region, a drain region, and a channel region, a first side gate stack formed at a first side of the channel region, and a second side gate stack formed at a second side of the channel region opposite the first side of the channel region. In the SONOS memory device, at least two bits of data may be stored in each SONOS memory device, thereby allowing the integration density of the semiconductor memory device to be increased without increasing an area thereof.

Abstract: The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate having a plurality of gate stacks in a memory cell region and at least one gate stack in a peripheral device region; forming caps made of one or more layers of a cap material over said plurality of gate stacks in said memory cell region and over said at least one gate stack in said peripheral device region; forming a first contact hole between two neighboring gate stacks in said memory cell region; depositing a first protective layer over said memory cell region and peripheral device region; exposing said cap of said at least one gate stack in said peripheral device region; modifying said exposed cap of said at least one gate stack in said peripheral device region in a process step wherein said first protective layer acts as a mask in said memory cell region; forming a second protective layer over said modified cap in said peripheral device region; partly

Abstract: A method of forming a capacitor includes forming a first capacitor electrode over a semiconductor substrate. A capacitor dielectric region is formed onto the first capacitor electrode. The capacitor dielectric region has an exposed oxide containing surface. The exposed oxide containing surface of the capacitor dielectric region is treated with at least one of a borane or a silane. A second capacitor electrode is deposited over the treated oxide containing surface. The second capacitor electrode has an inner metal surface contacting against the treated oxide containing surface. Other aspects and implementations are contemplated.

Abstract: A bismuth titanium silicon oxide having a pyrochlore phase, a thin film formed of the bismuth titanium silicon oxide, a method for forming the bismuth-titanium-silicon oxide thin film, a capacitor and a transistor for a semiconductor device including the bismuth-titanium-silicon oxide thin film, and an electronic device employing the capacitor and/or the transistor are provided. The bismuth titanium silicon oxide has good dielectric properties and is thermally and chemically stable. The bismuth-titanium-silicon oxide thin film can be effectively used as a dielectric film of a capacitor or as a gate dielectric film of a transistor in a semiconductor device. Various electronic devices having good electrical properties can be manufactured using the capacitor and/or the transistor having the bismuth-titanium-silicon oxide film.

Abstract: A nonvolatile semiconductor memory device including a memory cell and a selection transistor, and the memory cell includes a floating gate formed on a semiconductor substrate via a first gate insulation film, a pair of first diffusion layers positioned on the opposite sides of the floating gate and formed in the substrate, first and second control gates formed on the opposite sides of the floating gate to drive the floating gate, and an inter-gate insulation film formed between the first and second control gates and the floating gate. The selection transistor includes a selection gate formed on the substrate via a second gate insulation film, and a pair of second diffusion layers formed in the substrate positioned on the opposite sides of the selection gate and one of which is electrically connected to one of the pair of first diffusion layers.

Abstract: Semiconductor memory devices and methods to fabricate thereof are described. A first gate base is formed on a first insulating layer on a substrate. A first gate fin is formed on the first gate base. The first gate fin has a top and sidewalls. Next, a second insulating layer is formed on the top and sidewalls of the first gate fin and portions of the first gate base. A second gate is formed on the second insulating layer. Source and drain regions are formed in the substrate at opposite sides of the first gate base. In one embodiment, the first gate fin includes an undoped polysilicon and the first gate base includes an n-type polysilicon. In another embodiment, the first gate fin includes an undoped amorphous silicon and the first gate base includes an n-type amorphous silicon.

Abstract: A method of manufacturing flash memory devices includes depositing a nitride film over a semiconductor substrate and forming an oxide film below the nitride film using an oxidization process involving an anneal process. A tunnel oxide film or an ONO2 oxide film having a thin thickness and a good film quality is formed and the operating performance of memory cells is improved.